Name: ____________________________________
Student ID: _____________________
Department of Electrical and Computer Engineering McGill University ECSE 221 Introduction to Computer Engineering I Mid Term Exam Examiner: F.P. Ferrie Question 1
Date: October 17, 2005
(2 points)
A modified version of the IEEE 754 single precision floating point scheme can represent decimal numbers to 6 significant figures, resulting in a shorter mantissa. The bits removed from the mantissa are added to the exponent field. Determine the lengths (# bits) of the mantissa and exponent fields respectively, and the range of numbers that can be represented. Question 2
(4 points)
Encode the number –4.341 x 10-12 using IEEE 754 encoding and express your result as a 8-digit hexadecimal number. (Hint: decimal to binary fraction conversion is easier in Base16). Question 3
(2 points)
Determine the range of decimal numbers that can be represented by a 5-digit, Base18 number assuming that negative numbers are represented using a complement scheme. Question 4
(2 points)
Perform the following operation by long division (integer): 1D0316 ÷ 1716 Question 5
(2 points)
Determine what is produced by the following "C" program, assuming that integers in this particular machine are 2 bytes in length. int main() { int a=21, b=-27; printf("The sum of %x and %x is %x\n",a,b,a+b); } Question 6
(2 points)
Assuming that your computer does not support an exclusive-OR operator, how would you compute A " B ? Question 7
(2 points)
!Let F(a,b) be a Base function of two Base variables. How many different functions F are 3 3 possible? All variables (including the function itself) are single digits. (turn page over – more questions on back)
Question 8
(6 points)
Derive the minimal ∑∏ and ∏∑ forms for a function F =
" (3,4,6,9,11,12,14) .
Prove the
A,B ,C ,D
resulting forms are equal, and show the corresponding NAND-NAND and NOR-NOR implementations. Draw the circuit diagram for a 2-input NAND gate and 2-input NOR gate respectively using LogicWorks X-gates (no resistors). ! Question 9
(4 points)
Show the implementation of F in Question 8 using a 8-input multiplexer (clearly label all inputs). Assuming the multiplexer is implemented using a cascade of 2-way routing switches, calculate Tpd for this circuit assuming all identical gate delays of 1 nS. Question 10 (2 points) Write down the state transition table for a J-K flip-flop and derive the corresponding next state equation Qˆ = F(J, K,Q) . Question 11 (2 points) Fill in the timing diagram corresponding to the circuit shown below. You may do this directly on the question sheet (make sure to put your name on the question sheet and hand it in with your answer booklet). S
Q
C
R
Q'