Negative Bias Temperature Instability ... - Purdue Engineering
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007
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Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits Bipul C. Paul, Senior Member, IEEE, Kunhyuk Kang, Student Member, IEEE, Haldun Kufluoglu, Student Member, IEEE, Muhammad A. Alam, Fellow, IEEE, and Kaushik Roy, Fellow, IEEE
Abstract—Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold-voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm, taking the NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area, one can ensure a reliable performance of circuits for ten years. Index Terms—Design for reliability, negative bias temperature instability (NBTI), performance degradation, threshold-voltage degradation.
I. I NTRODUCTION
W
ITH THE continuous scaling of transistor dimensions, the reliability degradation of circuits has become an important issue in sub-100-nm technologies. Due to increasing electric field across the thin oxide, the generation of interface traps under a negative bias (Vgs = −Vdd ) at elevated temperature [also known as negative bias temperature instability (NBTI)] in pMOS transistors has become one of the most critical reliability issues that determine the lifetime of CMOS devices [1]–[3]. In conventional MOSFETs, due to crystal mismatch at the Si-SiO2 interface, traps are present in the form of Si dangling bonds after the growth of a gate oxide. Traditionally, these interface traps are passivated in ambient hydrogen to improve the device characteristics. However, due to aggressive oxide thickness scaling and process modifications such as the choice of p-poly gates for pMOS and oxide nitridation to prevent boron penetration from the gate, the Si–H bond breaking is accelerated at the interface (degrading the threshold voltage) over time during device operation. This results in temporal performance degradation in nanoscale circuits. Hence, an early Manuscript received June 9, 2005; revised November 16, 2005. This paper was recommended by Associate Editor S. Saxena. B. C. Paul is with Toshiba America Research Inc., San Jose, CA 95131 USA (e-mail: [email protected]). K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TCAD.2006.884870
estimation of reliability is necessary in the design phase, and it should be considered as one of the design parameters to ensure the reliable operation of circuits for a desired period of time. Due to NBTI, the threshold voltage (Vth ) of the transistor increases with time resulting in the reduction in drive current [4]. The reduction in drive current in turn results in temporal degradation in the performance of a circuit causing reliability degradation over time. Hence, an efficient design technique to minimize this temporal reliability degradation is very essential for digital circuit operation. Considerable efforts have been put in to estimate the threshold-voltage degradation [5], [6] as well as to analyze its impact on the drive current and circuit delay [7]–[9]. An analytical model is also recently proposed to estimate the temporal performance degradation of digital circuits due to NBTI [10]. However, a good design technique taking the temporal reliability degradation as one of the design constraints is rarely available. In this paper, we analyze the impact of the NBTI on the temporal performance degradation of combinatorial circuits and show that by taking this degradation into account during sizing, a desired performance can be ensured with a reasonable area overhead. We also propose a sizing algorithm to size the gates in a circuit, taking the temporal performance degradation into account. This algorithm estimates the threshold-voltage degradation of all individual pMOS transistors in a circuit based on their activities and accordingly sizes the circuit for a desired performance. The proposed sizing tool uses Lagrangian relaxation (LR) algorithm [11] for global optimization of gate sizes. We estimate the performance degradation of several ISCAS benchmark circuits implemented in 70-nm Berkeley Predictive Technology model (BPTM) [12] and show that the performance degradation of all the circuits has the same power-law dependence as the threshold voltage on time. We also size the circuits using the proposed algorithm taking the temporal performance degradation into account and compare the area overhead with that of nominal design. The rest of this paper is organized as follows. Section II briefly explains the analytical model for estimating the performance degradation of circuits due to NBTI. We describe the proposed sizing algorithm in Section III to size circuits considering the temporal performance degradation into account. Section IV discusses the experimental results on
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several ISCAS benchmark circuits followed by the conclusion in Section V. II. A NALYSIS OF T EMPORAL P ERFORMANCE D EGRADATION In this section, we will briefly describe the analytical model to estimate the performance degradation of circuits due to NBTI.
B. Circuit Delay Degradation The drain current of a transistor in the saturation region can be approximately represented as
A. Vth Degradation NBTI is the result of trap generation at the Si/SiO2 interface in negatively biased pMOS transistors at elevated temperatures. The interaction of inversion layer holes with hydrogenpassivated Si atoms can break the Si–H bonds, creating an interface trap and one H atom that can diffuse away from the interface (through the oxide) or can anneal an existing trap. The interface trap generation is modeled successfully in the reaction-diffusion framework [5]. In this model, the interface trap density (∆NIT ) is expressed as kf N0 ∆NIT (t) = (DH t)0.25 (1) kr where kf and kr are the bond-breaking and hydrogen annealing rates, respectively, N0 is the maximum available Si–H density, and DH is the diffusion coefficient. The bond-breaking rate depends on the accumulation of holes in the inversion layer and the tunneling of the holes into the oxide to dissociate the Si–H bonds [13]. Thus, kf depends on the hole density p, hole capture cross section σ0 , tunneling coefficient Tp , and the bond dissociation coefficient B, and can be expressed as kf ∝ Bσ0 pTp , where p(= Cox (Vg − Vth ) ∝ Eox ) and Tp ( e(Eox /E0 ) ) depend on the electric field (Eox ) across the oxide. E0 is the field acceleration factor. B, σ0 , and kr are assumed to have weak field dependence [13]. Substituting kf , (1) can be simplified to ∆NIT (Eox , t) ≡ χ Eox e
Eox E0
t
0.25
(2)
where χ represents the field independent terms. The change in the threshold voltage due to the increase in interface charge, hence, can be given by ∆Vth (Eox , t) =
Further, the frequency-dependent effect on Vth degradation [5] can be included by modifying the parameter “kf ” in (1) by a constant factor and, hence, will not change the time exponent. The factor can be obtained based on the switching activity of the transistor. However, due to the unavailability of a proper model to obtain this factor, we did not include quantitative results considering an ac recovery in this paper.
qNIT (Eox , t) Cox
(3)
where q is the electronic charge. Furthermore, the interface traps increase scattering resulting in mobility degradation. The mobility degradation can be expressed as an additional Vth shift [9]. The effective threshold-voltage degradation can be expressed as ∆Vth (Eox , t) = (1 + m)
qNIT (Eox , t) Cox
(4)
where m is a constant representing the equivalent Vth shift due to mobility degradation for a given technology.
Id = β(Vg − Vth )α ,
β=
µCox Weff Leff
(5)
where Vg and Vth are the gate voltage and the threshold voltage of the transistor, respectively. µ is the mobility, Cox is the oxide capacitance, and Leff and Weff are, respectively, the channel length and width of the transistor. α is a constant, whose value ranges from 1 to 2. The delay of a gate can be approximately expressed as [8], [9] τ= K1 =
K1 CL Vdd = Id (Vg − Vth )α CL Vdd β
(6)
where CL is the load capacitance and Vdd is the supply voltage. Differentiating (6) with respect to Vth , we get δτ αδVth = . τ (Vg − Vth )
(7)
Integrating (7), we get τ0+∆τ
τ0
dτ = τ
Vth0 +∆Vth0
Vth0
αdVth (Vg − Vth )
∆τ ∆Vth ln 1 + = −α · ln 1 − τ0 Vg − Vth0
(8)
where Vth0 is the threshold voltage at any time instant t and τ0 is the corresponding gate delay. Using Taylor series expansion on both sides of (8) and neglecting the higher order terms (assuming ln(1 + x) ∼ x), we get ∆τ ∆Vth =α . τ0 Vg − Vth0
(9)
Substituting ∆Vth from (4) in the form of Atn (n = 0.25), (9) can be rewritten as ∆τ αA log = n · log (t) + log τ0 Vg − Vth0 E ox qχ Eox e E0 A = (1 + m) . (10) Cox
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Fig. 2. Example circuit for sizing with reliability constraint.
Fig. 1. Percentage degradation in inverter and ring oscillator delays with time under NBTI stress. The delays of the inverter and the ring oscillator are obtained through HSPICE simulation using BPTM 70-nm technology.
The second term in the right-hand side of (10) is not constant because Vth is a function of time. However, due to the logarithmic dependence, this term can be treated as constant for a specific range of time (e.g., ten years [10]). In this period, log(∆τ /τ ) will linearly change with log(t) with the same slope n as the Vth degradation. Therefore, by monitoring the threshold-voltage degradation, the change in gate delay can be easily estimated with a high degree of accuracy. The degradation in the delay of a circuit, τckt ( N i=1 τg,i ) can further be estimated as [10] N n αAτg,i ∆τckt i=1 (Si · t) Vg −Vth,i log = log N τckt i=1 τg,i
N αA(Si )n τg,i = n log (t) + log , τ (V − Vth,i ) i=1 ckt g τg , τckt : (t = 0)
(11)
where N is the number of gates in the critical path and τg,i is the delay of ith gate. Si · t represents the ON-time of a pMOS transistor in a particular gate i based on its switching activity. Note that Si is typically calculated over a period of time and shows a negligible change. Hence, the slope (n) of log(∆τckt /τckt ) versus log(t) will not change. Fig. 1 shows the degradation of threshold voltage and the corresponding gate (inverter) delay with time. The thresholdvoltage degradation was obtained using (4). The inverter delay was measured through an HSPICE simulation using 70-nm BPTM technology (Vdd = 1 V). It can be observed that both the threshold voltage and the gate-delay degradation have the same slope (= 0.25) as expected from (10). This is also observed experimentally in ring oscillators [15]. It can also be observed from Fig. 1 that the degradation in delay is less than the degradation in threshold voltage. This can be understood from (9). Since Vg − Vth0 is greater than Vth0 (within the time range shown in Fig. 1) and α is close
to one for short-channel transistors, the percentage degradation in delay will be less than that of the threshold voltage and can be quantified as log[(α/(Vg − Vth0 )]. For example, with Vg = 1 V and Vt0 = 0.3 V, a 20% degradation in Vth will cause approximately 10% degradation in the gate delay (9). Fig. 1 also shows the performance degradation of a ninestage ring oscillator with time. The delay was also measured through the HSPICE simulation using the 70-nm BPTM technology with 1-V supply. As expected, the circuit performance degradation also has the same slope as Vth degradation. However, the percentage degradation is further less than that of a single gate. This is because in a circuit, a low-to-high switching is always followed by a high-to-low switching. While a lowto-high switching is affected due to the NBTI-induced Vth degradation, the high-to-low switching is not affected. Hence, the overall performance degradation is approximately half of that of a single gate. III. S IZING FOR R ELIABILITY I MPROVEMENT In this section, a gate-sizing algorithm is proposed, which considers the temporal performance degradation of the circuit into account. The algorithm proposed here is based on a technique called Lagrangian Relaxation (LR) [14] for solving nonlinear optimization problem. Chen et al. [11] proposed the use of LR for simultaneous sizing of gate and interconnects of a combinational circuit to optimize the total area while maintaining a delay constraint. The convergence of the algorithm was proven, and the optimality was verified. In our experiments, we ignored interconnects since interconnects do not play a role in NBTI. However, the algorithm can easily incorporate interconnects. A. Problem Formulation Fig. 2 shows an example circuit representation for sizing with reliability constraint. The circuit consists of n gates, which are to be sized, and s primary inputs. Logic gates and primary inputs are called components. In addition, we add two virtual components, one connecting all primary inputs (component 9 in Fig. 2) and the other connecting primary outputs (component 0). Therefore, for a circuit with n gates and s inputs, there are n + s + 2 components. Edge numbers follow their driver gates, i.e., the output of gate i is denoted as edge i. Note that the components and edges are numbered in reverse topological order. Our objectiveis to minimize the total area which can be represented by αi xi , i = 1, . . . , n where xi is the gate size and αi is an arbitrary constant multiplier for gate i, which can
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vary depending on the objective of optimization. Hence, the sizing problem can be formulated as follows: Minimize
n
αi xi
delay constraints on all the paths are transformed into the delay constraints on each gate in the circuit. Therefore, the sizing problem (which is called the primal problem; PP) is redefined as follows:
i=1
Subject to
Di ≤ A0 ,
∀p ∈ P
PP : Minimize
i∈p
Li ≤ xi ≤ Ui ,
n
αi xi
i=1
i = 1, . . . , n
(12)
Subject to aj ≤ A0 ,
where Li and Ui represent the lower bound and upper bound of the size of gate i, respectively. P is the set of possible paths in a circuit. Di represents the delay of gate i in a path p. Note that threshold voltages of the transistors in all individual gates will be different due to the NBTI depending on their switching activities. The proposed algorithm first calculates the thresholdvoltage degradation of all transistors in a circuit depending on their switching activities and then sizes the circuit to ensure the performance for a desired period of time (e.g., ten years).
aj +Di ≤ ai ,
B. Vth Estimation This algorithm calculates the switching activities of all gates in a circuit for given signal switching probabilities at all primary inputs [16]. Based on the switching activity, the ON-time (Vgs = −Vdd ) of all pMOS transistors is calculated for a desired period of time Tmax (e.g., ten years). Using the ON-time, the thresholdvoltage degradation (∆Vth ) of all pMOS transistors is then calculated from (4). We calculate the delay of each gate using Sakurai’s gatedelay model [17]. In [11], Elmore delay model was used for calculating the arrival-time information. However, we use the Sakurai’s delay model for better accuracy. This model uses precomputed device parameters that are obtained from the I–V characteristics of a particular transistor. However, in our analysis, since the threshold voltage of different transistors is different (hence, the I–V characteristics), we use a lookup table to obtain device parameters corresponding to a particular transistor (threshold voltage). We first obtain and store the device characteristics required for Sakurai’s delay model for different threshold voltages of the transistor. The detailed explanation on how to obtain these parameters for a particular threshold voltage can be found in [17]. In static timing analysis, the worst case delay of each gate is considered to obtain the circuit delay. Hence, based on the circuit topology and the type of the gate, we first find the transistor that is responsible for maximum gate delay. The device parameters corresponding to the threshold voltage of that transistor are then obtained from the lookup table and used in the delay calculation. C. Sizing Algorithm In this section, we explain how to size the circuit using the LR taking the temporal performance degradation into account. Note that the complexity of the problem defined in (12) is exponentially dependent on the number of components in the circuit (O(en )). To reduce the complexity to a linear one, the
j ∈ input(node : 0)/∗ outputs∗ / i = 1, . . . , n
Di ≤ ai ,
∀j ∈ input(i)
i = n+1, . . . , n+s
Li ≤ xi ≤ Ui ,
i = 1, . . . , n
/∗ inputs∗ / (13)
where ai represents the signal arrival time at edge i and Di is the delay associated with gate i considering the temporal performance degradation based on its switching activity. Hence, this algorithm globally optimizes the gate sizes and is not a pathbased algorithm. Also note that the delay constraint A0 is on the circuit delay and not on any specific path in the circuit. In the previous problem, PP is solved by introducing a Lagrangian multiplier λ for each constraint on arrival time as follows:
Minimize : Lλ (x, a) =
n i=1
+
αi xi +
n
λj0 (aj − A0 )
j∈input(0)
λji (aj + Di − ai )
i=1 j∈input(i)
+
n+s
λmi (Di − ai )
(14)
i=n+1
where λji corresponds to the input edge j and output edge i of gate i. m in λmi is equal to n + s + 1 (virtual input node). The flow diagram of the proposed sizing algorithm for reliability improvement is shown in Fig. 3. The algorithm first calculates the switching activities of all gates in a circuit for given signal switching probabilities at all primary inputs. It then estimates the threshold-voltage degradation of all pMOS transistors in the circuit. This information is used to obtain the delay of each gate in the circuit. Finally, Lλ is minimized to obtain minimum size of the circuit for a given delay constraint. Minimizing Lλ using LR consists of iterating the following two steps: 1) calculating the optimal size of the circuit for the current λ values and 2) updating λ to the direction of the optimal solution [11]. In this algorithm, we use Sakurai’s delay model to calculate the gate delay. The mathematical formulation for optimal size of a gate using Sakurai’s delay model is given in the Appendix. Minimizing Lλ provides the minimum size of a circuit while ensuring the performance for a desired period of time Tmax .
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Fig. 4. Percentage degradation in the performance of ISCAS C432 benchmark circuit: 1) with worst case (Si = 1) NBTI stress and 2) with activity-dependent effect.
Fig. 3.
Sizing algorithm for reliability improvement.
IV. S IMULATION R ESULTS We simulated several ISCAS benchmark circuits to estimate their temporal performance degradation due to the NBTI stress and sized them using the proposed algorithm. We considered the following two cases: 1) Vth degradation of all pMOS transistors is the same (worst case condition) and 2) Vth degradation of all individual pMOS transistors is different depending on their ON-time (Vgs = −Vdd ). The ON-time is calculated based on the switching activity of each individual gate. The circuit delay is calculated through a static timing analysis. The delay of each gate was calculated using Sakurai’s gate-delay model [17]. A. Estimation of Performance Degradation Fig. 4 shows the performance degradation of ISCAS C432 benchmark circuit with time. It can be seen that as expected, the slope of log(∆τckt ) versus log(t) plot, both cases 1) and 2) are the same as that of Vth degradation. Also note that the performance degradation considering the switching activity is less than the worst case NBTI stress. The activity factors of all the transistors were calculated by assuming 50% signal switching probability at the primary inputs. Fig. 5 shows the probability density function (pdf) of the threshold-voltage degradation (∆Vth ) considering transistor activities of the same C432 circuit. It can be observed that despite a wide variation in ∆Vth , the performance degradation is almost comparable to the worst case degradation (Fig. 4). We further calculated the per-
Fig. 5. PDF of transistor activities in ISCAS C432 benchmark circuit.
formance degradation of the same circuit (C432) with very low (10%) and high (100%) signal switching probabilities at the primary inputs. It was observed that the performance degradation is a weak function of signal probability. The threshold-voltage degradation of pMOS transistor depends on its ON-time, which changes with the signal probability at the input. However, due to the topology of CMOS circuits, when the ON-time of a particular transistor reduces, the ON-time of transistor in the following gate is likely to increase. This makes the overall performance degradation of a circuit insensitive to the signal probability. Hence, calculating the performance degradation with worst case assumption will not result in a significant over estimation. Note that the above discussion is true for traditional CMOS circuit topology, which occupies the major part of a design. The impact of switching activity may however be different for different circuit types. All other benchmark circuits also show the similar delay degradation characteristics
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TABLE I DELAY DEGRADATION OF ISCAS BENCHMARK CIRCUITS UNDER NBTI
Fig. 7. Area versus delay for ISCAS C432 benchmark circuit. The area was calculated as the sum of transistor width. TABLE II SIZING ISCAS BENCHMARK CIRCUITS CONSIDERING TEMPORAL PERFORMANCE DEGRADATION DUE TO NBTI
Fig. 6. Percentage degradation in the performance of ISCAS C432 benchmark circuit with time-dependent exponent (n).
with time. Table I shows the percentage delay degradation of several ISCAS benchmark circuits with time under both worst case (Si = 1) and activity-dependent (Si < 1) NBTI stress. Though the delay degradation depends on the circuit topology, the expected average delay degradation is about 9.2% (worst case) in ten years, which is approximately four times less than Vth degradation of individual transistors. It has been recently reported that the time exponent (n) of ∆Vth decreases over time [18]. It can be seen from (10) that though n is a function of time, the circuit delay degradation still follows the Vth degradation. This is further confirmed with the simulation of ISCAS C432 circuit shown in Fig. 6. In this analysis, we only considered the degradation of Vth under the NBTI stress. However, the conductivity (gm ) and the capacitance of the transistor are also affected (though not as strongly as Vth ) due to NBTI. The impact of the degradation in these parameters on circuit performance can also be modeled following the same method described in this paper.
B. Sizing Our proposed sizing algorithm was used to size several ISCAS benchmark circuits, taking their temporal performance degradation due to NBTI into account. Fig. 7 shows the areaversus-delay curve of ISCAS C432 benchmark circuit using the conventional LR sizing algorithm. The area (the sum of transistor width) in the plot represents the minimum circuit size for the corresponding delay. Since the area strongly depends on the delay, the area overhead in sizing considering the reliability into account will also depend on the delay constraint. We chose the delay constraint of a circuit from the above area-versusdelay plot where the percentage increase in area is equal to the percentage decrease in delay (e.g., 385 ps for C432). Table II shows the area overhead in sizing the above benchmark circuits using the proposed algorithm to ensure the reliability for ten years. We calculated the area overhead for
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that with an average of 8.7% area overhead, one can avoid the reliability degradation of nanoscale circuits due to NBTI for ten years. A PPENDIX C ALCULATION OF O PTIMUM G ATE S IZE U SING S AKURAI ’ S D ELAY M ODEL
Fig. 8.
Impact of NBTI on different technology generations.
both worst case and activity-dependent performance degradation. We chose 50% signal probability for all the benchmark circuits in our analysis. It can be observed from the table that with an average of 8.7% area overhead (worst case), the temporal performance degradation of digital circuits due to NBTI can be avoided. Note that the area overhead in large circuits (e.g., C3540) is even less (3.44%). Hence, although the threshold-voltage degradation due to NBTI is estimated to be approximately 35% in ten years (in 70-nm technology), a small area overhead is sufficient to ensure the reliable operation of digital circuits. Also note that the area overhead considering the activity of the circuit is not significantly different from the worst case design. Hence, sizing circuits considering the worst case performance degradation will not result in pessimistic design. This further simplifies the design of digital circuits considering the reliability as one of the design constraints. We further analyzed the impact of NBTI on different technology generations. Fig. 8 shows the percentage degradation (in ten years) in threshold voltage in 100-, 70-, and 45-nm technologies (BPTM), respectively. The increase in Vth degradation with technology scaling is expected due to the increase in oxide field. It can also be observed that the average delay degradation (in all ISCAS benchmark circuits) is approximately four times less than that of Vth . Recently, statistical sizing techniques have been proposed to size circuits considering process variations [19], [20]. Our proposed sizing technique can also be incorporated with those tools by properly modifying the threshold voltage of transistors due to NBTI.
Calculation of the optimal size (Fig. 3) involves the sizing of each gate in such a way that Lλ is locally minimized. Since Di in Lλ is a function of gate size xi , the optimal size of a gate can be obtained by solving (dLλ /dxi ) = 0. It was shown in [11] that Lλ can be simplified to Lµ using the optimality condition as follows: Lµ =
n+s i=1
µi =
n
αi xi − µ0 A0
i=1
λji
i = 1, . . . , n (15)
j∈input(i)
λmi
i = n + 1, . . . , n + s.
Note that Lµ is a function of µ, not λ. When the circuit is iteratively sized, the optimum size xi,opt which minimizes Lµ is calculated for gate i. Based on Sakurai’s delay model [17], delay associated with a gate i, Di can be represented as follows for fast inputs1 (slow input case can be solved similarly): Di =
2 4vD0 CI VDD 0.7ID0IN 4vD0 − 1
1 − vT (vV − vT )n+1 CO VDD × 0.5 − + + 0.5 n+1 (n + 1)(1 − vT )n ID0
(16)
where CI and CO represent the input and output capacitances of a gate, respectively. ID0 is the drain current for VGS = VDS = VDD , where VDD is the supply voltage. vD0 = VD0 /VDD , vT = VT 0 /VDD , and vV = VINV /VDD , where VD0 is the drain saturation voltage for VGS = VDD , VT 0 is the saturation voltage, and VINV is the logic threshold voltage. n denotes the constant that controls the drain current in saturation region. The complete derivation of the gate delay can be found in [17]. Note from the above equation that CI and ID0 can be represented as a linear function of the transistor size (or equivalently the gate size) xi as CI = β1 xi and ID0 = β2 xi . Then, the gate delay Di becomes
V. C ONCLUSION In this paper, we analyzed the performance degradation of digital circuits due to the NBTI stress. It is shown that the overall performance degradation of a circuit is significantly less than the threshold-voltage degradation of individual transistors and that it can be handled by employing a sizing technique with an additional reliability constraint. We also proposed a sizing algorithm considering the temporal performance degradation into account. This algorithm ensures the performance of circuits for a desired period of time under the NBTI-affected threshold-voltage degradation. Simulation results on several ISCAS benchmark circuits in BPTM 70-nm technology show
µi Di +
Di = γ1 xi +
γ2 xi
(17)
where 2 β1 VDD 4vD0 γ1 = 0.7ID0IN 4vD0 −1
γ2 =
1 The
(vV −vT )n+1 1−vT + 0.5− n+1 (n+1)(1−vT )n
CO VDD . β2
delay equation presented is also under zero-body bias assumption.
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By inserting Di into Lµ shown in (15), we get Lµ = (αi + µi γ1 )xi +
µi γ2 + terms independent of xi . xi
By setting dLµ /dxi = 0, the optimal size of gate i, xi,opt can be obtained as follows: µi γ2 xi,opt = min Ui , max Li , (18) αi + µi γ1 where Li and Ui are the lower and upper bounds of gate size xi , respectively. For n gates in a circuit, each gate is sized according to xi,opt shown previously, and the timing analysis is performed. R EFERENCES [1] N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi, “Impact of bias temperature instability for direct tunneling ultrathin gate oxide on MOSFET scaling,” in Proc. Symp. VLSI Technol. Tech. Dig. Papers, 1999, pp. 73–74. [2] G. Chen, M. F. Li, C. H. Ang, J. Z. Zheng, and D. L. Kwong, “Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling,” IEEE Electron Device Lett., vol. 23, no. 12, pp. 734–736, Dec. 2002. [3] Y. H. Lee, N. Mielke, B. Sabi, S. Stadler, R. Nachman, and S. Hu, “Effect of pMOST bias-temperature instability on circuit reliability performance,” in Proc. IEDM Tech. Dig., 2003, pp. 14.6.1–14.6.4. [4] D. Schroder and J. F. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl. Phys., vol. 94, no. 1, pp. 1–18, 2003. [5] M. A. Alam, “A critical examination of the mechanics of dynamic NBTI for PMOSFETs,” in Proc. IEDM, 2003, pp. 346–349. [6] S. Zafar, B. H. Lee, and J. Stathis, “Evaluation of NBTI in HfO/sub 2/gate dielectric stacks with tungsten gates,” IEEE Electron Device Lett., vol. 25, no. 3, pp. 153–155, Mar. 2004. [7] W. Abadeer and W. Ellis, “Behavior of NBTI under AC dynamic circuit conditions,” in Proc. IRPS, 2003, pp. 17–22. [8] V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, “Impact of negative bias temperature instability on digital circuit reliability,” in Proc. IRPS, 2002, pp. 248–253. [9] A. T. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, and S. Krishnan, “NBTI impact on transistor and circuit: Models, mechanisms and scaling effects,” in Proc. IEDM, 2003, pp. 14.5.1–14.5.4. [10] B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Impact of NBTI on the temporal performance degradation of digital circuits,” IEEE Electron Device Lett., vol. 26, no. 8, pp. 560–562, Aug. 2005. [11] C. P. Chen, C. C. N. Chu, and D. F. Wong, “Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation,” IEEE Trans. Comput.Aided Design Integr. Circuits Syst., vol. 18, no. 7, pp. 1014–1025, Jul. 1999. [12] Device Group, Dept. Elect. Eng. Comput. Sci., Univ. California, Berkeley. [Online]. Available: http://www-device.eecs.berkeley.edu/ptm [13] M. A. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation,” Microelectron. Reliab., vol. 45, no. 1, pp. 71–81, Jan. 2005. [14] M. S. Bazaraa, H. D. Sherali, and C. M. Shetty, Nonlinear Programming: Theory and Algorithms, 2nd ed. Hoboken, NJ: Wiley, 1993. [15] V. Reddy, J. Carulli, A. Krishnan, W. Bosch, and B. Burgess, “Impact of negative bias temperature instability on product parametric drift,” in Proc. ITC, 2004, pp. 148–155. [16] Z. Chen, K. Roy, and T. Chou, “Power sensitivity—A new method to estimate power dissipation considering uncertain specifications of primary inputs,” in Proc. ICCAD, 1997, pp. 40–44. [17] T. Sakurai and R. Newton, “Delay analysis of series-connected MOSFET circuits,” IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 122–131, Feb. 1991. [18] S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan, “A comprehensive framework for predictive modeling of negative bias temperature instability,” in Proc. IRPS, 2004, pp. 273–282. [19] E. T. A. F. Jacobs and M. R. C. M. Berkelaar, “Gate sizing using statistical delay model,” in Proc. DATE, 2000, pp. 283–290. [20] S. H. Choi, B. C. Paul, and K. Roy, “Novel sizing algorithm for yield improvement under process variation,” in Proc. DAC, 2004, pp. 454–459.
Bipul C. Paul (S’97–M’01–SM’05) received the B.Tech. and M.Tech. degrees in radiophysics and electronics from University of Calcutta, Kolkata, West Bengal, India, and the Ph.D. degree from Indian Institute of Science (IISc), Bangalore, India. After his graduation, he joined Alliance Semiconductor (India), where he worked on synchronous DRAM design. In 2000, he joined Purdue University, West Lafayette, IN, as a Post Doctoral Fellow, where he worked on low-power electronic design of nanoscale circuits (both bulk and SOI technologies), statistical design under process variation, VLSI testing, verification, and noise analysis. He has also developed device and circuit optimization techniques for ultralow power digital subthreshold operation. He is currently with the Toshiba America Research Inc., San Jose, CA, where he is working on post-silicon device modeling, 3-D circuit design, and nanoarchitecture. He is also a Visiting Scientist with Stanford University, Stanford, CA. Dr. Paul received the National scholarship, India, in 1984, the Senior Research Fellowship Award from CSIR, India, in 1995, the Best Thesis Award in 1999, and the 2006 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Best Paper Award.
Kunhyuk Kang (S’04) received the B.S. degree from Seoul National University, Seoul, Korea, in 2002, and the M.S. degree from Rensselaer Polytechnic Institute, Troy, NY, in 2003, both in electrical engineering. He is currently working toward the Ph.D. degree in electrical engineering at Purdue University, West Lafayette, IN. In the summer of 2005, he was an Intern with Texas Development Center, Intel Corporation, Austin, TX, where he performed research in static timing analysis. His research interests include statistical design, timing analysis, CAD, and design for reliability.
Haldun Kufluoglu (S’04) was born in Turkey, in 1979. He received the B.S. and M.S. degrees in electrical engineering from Purdue University, West Lafayette, IN, in 2001 and 2003, respectively, where he is currently working toward the Ph.D. degree. Particularly, his Ph.D. research involves measurements and theoretical modeling of MOSFET degradation mechanisms such as NBTI, HCI, and TDDB, and their implications on VLSI design. His research interests include MOSFET reliability, experimental characterization, and modeling of semiconductor devices. He also participates in OFF-state transistor reliability assessment. Previously, he obtained microfabrication skills in a MEMS-based sensor that was interfaced with live neurons for biological applications.
PAUL et al.: NBTI: ESTIMATION AND DESIGN FOR IMPROVED RELIABILITY OF NANOSCALE CIRCUITS
Muhammad A. Alam (F’05) received the B.S.E.E. degree from Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, in 1988, the M.S. degree from Clarkson University, Potsdam, NY, in 1991, and the Ph.D. degree from Purdue University, Lafayette, IN, in 1994, all in electrical engineering. From 1995 to 2001, he was with Bell Laboratories, Lucent Technologies, Murray Hill, NJ, as a member of technical staff with the Silicon ULSI Research Department. From 2001 to 2003, he was a distinguished member of technical staff and the Technical Manager with the IC Reliability Group at Agere Systems, Murray Hill. In 2004, he joined Purdue University, West Lafayette, IN, where he is currently a Professor of electrical and computer engineering, where his research and teaching focus on physics, simulation, characterization, and technology of classical and novel semiconductor devices. His current research includes theory of oxide reliability, transport in nanocomposite thin film transistors, and nanobio sensors. He has published over 75 papers in international journals and has presented many invited and contributed talks at international conferences. Dr. Alam received IRPS Best Paper Award in 2003 and an Outstanding Paper Award in 2001, both for his work on gate oxide reliability. Most recently, he was elected an IEEE Fellow for contribution to physics of CMOS reliability and simulation of optoelectronic devices and received IEEE Kiyo Tomiyasu Award for contributions to device technology for communication systems.
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Kaushik Roy (S’83–M’83–SM’95–F’02) received the B.Tech. degree in electronics and electrical communications engineering from Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois, Urbana-Champaign, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and lowpower circuit design. In 1993, he joined the Electrical and Computer Engineering Faculty at Purdue University, West Lafayette, IN, where he is currently a Professor and a Purdue University Faculty Scholar Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 200 papers in refereed journals and conferences, holds five patents, and has coauthored a book on Low Power CMOS VLSI Design (John Wiley). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM Faculty Partnership Award, ATT/Lucent Foundation Award, and Best Paper Awards at 1997 International Test Conference and 2000 International Symposium on Quality of IC Design. He is in the editorial board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was a Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).
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Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits Bipul C. Paul, Senior Member, IEEE, Kunhyuk Kang, Student Member, IEEE, Haldun Kufluoglu, Student Member, IEEE, Muhammad A. Alam, Fellow, IEEE, and Kaushik Roy, Fellow, IEEE
Abstract—Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold-voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm, taking the NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area, one can ensure a reliable performance of circuits for ten years. Index Terms—Design for reliability, negative bias temperature instability (NBTI), performance degradation, threshold-voltage degradation.
I. I NTRODUCTION
W
ITH THE continuous scaling of transistor dimensions, the reliability degradation of circuits has become an important issue in sub-100-nm technologies. Due to increasing electric field across the thin oxide, the generation of interface traps under a negative bias (Vgs = −Vdd ) at elevated temperature [also known as negative bias temperature instability (NBTI)] in pMOS transistors has become one of the most critical reliability issues that determine the lifetime of CMOS devices [1]–[3]. In conventional MOSFETs, due to crystal mismatch at the Si-SiO2 interface, traps are present in the form of Si dangling bonds after the growth of a gate oxide. Traditionally, these interface traps are passivated in ambient hydrogen to improve the device characteristics. However, due to aggressive oxide thickness scaling and process modifications such as the choice of p-poly gates for pMOS and oxide nitridation to prevent boron penetration from the gate, the Si–H bond breaking is accelerated at the interface (degrading the threshold voltage) over time during device operation. This results in temporal performance degradation in nanoscale circuits. Hence, an early Manuscript received June 9, 2005; revised November 16, 2005. This paper was recommended by Associate Editor S. Saxena. B. C. Paul is with Toshiba America Research Inc., San Jose, CA 95131 USA (e-mail: [email protected]). K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TCAD.2006.884870
estimation of reliability is necessary in the design phase, and it should be considered as one of the design parameters to ensure the reliable operation of circuits for a desired period of time. Due to NBTI, the threshold voltage (Vth ) of the transistor increases with time resulting in the reduction in drive current [4]. The reduction in drive current in turn results in temporal degradation in the performance of a circuit causing reliability degradation over time. Hence, an efficient design technique to minimize this temporal reliability degradation is very essential for digital circuit operation. Considerable efforts have been put in to estimate the threshold-voltage degradation [5], [6] as well as to analyze its impact on the drive current and circuit delay [7]–[9]. An analytical model is also recently proposed to estimate the temporal performance degradation of digital circuits due to NBTI [10]. However, a good design technique taking the temporal reliability degradation as one of the design constraints is rarely available. In this paper, we analyze the impact of the NBTI on the temporal performance degradation of combinatorial circuits and show that by taking this degradation into account during sizing, a desired performance can be ensured with a reasonable area overhead. We also propose a sizing algorithm to size the gates in a circuit, taking the temporal performance degradation into account. This algorithm estimates the threshold-voltage degradation of all individual pMOS transistors in a circuit based on their activities and accordingly sizes the circuit for a desired performance. The proposed sizing tool uses Lagrangian relaxation (LR) algorithm [11] for global optimization of gate sizes. We estimate the performance degradation of several ISCAS benchmark circuits implemented in 70-nm Berkeley Predictive Technology model (BPTM) [12] and show that the performance degradation of all the circuits has the same power-law dependence as the threshold voltage on time. We also size the circuits using the proposed algorithm taking the temporal performance degradation into account and compare the area overhead with that of nominal design. The rest of this paper is organized as follows. Section II briefly explains the analytical model for estimating the performance degradation of circuits due to NBTI. We describe the proposed sizing algorithm in Section III to size circuits considering the temporal performance degradation into account. Section IV discusses the experimental results on
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several ISCAS benchmark circuits followed by the conclusion in Section V. II. A NALYSIS OF T EMPORAL P ERFORMANCE D EGRADATION In this section, we will briefly describe the analytical model to estimate the performance degradation of circuits due to NBTI.
B. Circuit Delay Degradation The drain current of a transistor in the saturation region can be approximately represented as
A. Vth Degradation NBTI is the result of trap generation at the Si/SiO2 interface in negatively biased pMOS transistors at elevated temperatures. The interaction of inversion layer holes with hydrogenpassivated Si atoms can break the Si–H bonds, creating an interface trap and one H atom that can diffuse away from the interface (through the oxide) or can anneal an existing trap. The interface trap generation is modeled successfully in the reaction-diffusion framework [5]. In this model, the interface trap density (∆NIT ) is expressed as kf N0 ∆NIT (t) = (DH t)0.25 (1) kr where kf and kr are the bond-breaking and hydrogen annealing rates, respectively, N0 is the maximum available Si–H density, and DH is the diffusion coefficient. The bond-breaking rate depends on the accumulation of holes in the inversion layer and the tunneling of the holes into the oxide to dissociate the Si–H bonds [13]. Thus, kf depends on the hole density p, hole capture cross section σ0 , tunneling coefficient Tp , and the bond dissociation coefficient B, and can be expressed as kf ∝ Bσ0 pTp , where p(= Cox (Vg − Vth ) ∝ Eox ) and Tp ( e(Eox /E0 ) ) depend on the electric field (Eox ) across the oxide. E0 is the field acceleration factor. B, σ0 , and kr are assumed to have weak field dependence [13]. Substituting kf , (1) can be simplified to ∆NIT (Eox , t) ≡ χ Eox e
Eox E0
t
0.25
(2)
where χ represents the field independent terms. The change in the threshold voltage due to the increase in interface charge, hence, can be given by ∆Vth (Eox , t) =
Further, the frequency-dependent effect on Vth degradation [5] can be included by modifying the parameter “kf ” in (1) by a constant factor and, hence, will not change the time exponent. The factor can be obtained based on the switching activity of the transistor. However, due to the unavailability of a proper model to obtain this factor, we did not include quantitative results considering an ac recovery in this paper.
qNIT (Eox , t) Cox
(3)
where q is the electronic charge. Furthermore, the interface traps increase scattering resulting in mobility degradation. The mobility degradation can be expressed as an additional Vth shift [9]. The effective threshold-voltage degradation can be expressed as ∆Vth (Eox , t) = (1 + m)
qNIT (Eox , t) Cox
(4)
where m is a constant representing the equivalent Vth shift due to mobility degradation for a given technology.
Id = β(Vg − Vth )α ,
β=
µCox Weff Leff
(5)
where Vg and Vth are the gate voltage and the threshold voltage of the transistor, respectively. µ is the mobility, Cox is the oxide capacitance, and Leff and Weff are, respectively, the channel length and width of the transistor. α is a constant, whose value ranges from 1 to 2. The delay of a gate can be approximately expressed as [8], [9] τ= K1 =
K1 CL Vdd = Id (Vg − Vth )α CL Vdd β
(6)
where CL is the load capacitance and Vdd is the supply voltage. Differentiating (6) with respect to Vth , we get δτ αδVth = . τ (Vg − Vth )
(7)
Integrating (7), we get τ0+∆τ
τ0
dτ = τ
Vth0 +∆Vth0
Vth0
αdVth (Vg − Vth )
∆τ ∆Vth ln 1 + = −α · ln 1 − τ0 Vg − Vth0
(8)
where Vth0 is the threshold voltage at any time instant t and τ0 is the corresponding gate delay. Using Taylor series expansion on both sides of (8) and neglecting the higher order terms (assuming ln(1 + x) ∼ x), we get ∆τ ∆Vth =α . τ0 Vg − Vth0
(9)
Substituting ∆Vth from (4) in the form of Atn (n = 0.25), (9) can be rewritten as ∆τ αA log = n · log (t) + log τ0 Vg − Vth0 E ox qχ Eox e E0 A = (1 + m) . (10) Cox
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Fig. 2. Example circuit for sizing with reliability constraint.
Fig. 1. Percentage degradation in inverter and ring oscillator delays with time under NBTI stress. The delays of the inverter and the ring oscillator are obtained through HSPICE simulation using BPTM 70-nm technology.
The second term in the right-hand side of (10) is not constant because Vth is a function of time. However, due to the logarithmic dependence, this term can be treated as constant for a specific range of time (e.g., ten years [10]). In this period, log(∆τ /τ ) will linearly change with log(t) with the same slope n as the Vth degradation. Therefore, by monitoring the threshold-voltage degradation, the change in gate delay can be easily estimated with a high degree of accuracy. The degradation in the delay of a circuit, τckt ( N i=1 τg,i ) can further be estimated as [10] N n αAτg,i ∆τckt i=1 (Si · t) Vg −Vth,i log = log N τckt i=1 τg,i
N αA(Si )n τg,i = n log (t) + log , τ (V − Vth,i ) i=1 ckt g τg , τckt : (t = 0)
(11)
where N is the number of gates in the critical path and τg,i is the delay of ith gate. Si · t represents the ON-time of a pMOS transistor in a particular gate i based on its switching activity. Note that Si is typically calculated over a period of time and shows a negligible change. Hence, the slope (n) of log(∆τckt /τckt ) versus log(t) will not change. Fig. 1 shows the degradation of threshold voltage and the corresponding gate (inverter) delay with time. The thresholdvoltage degradation was obtained using (4). The inverter delay was measured through an HSPICE simulation using 70-nm BPTM technology (Vdd = 1 V). It can be observed that both the threshold voltage and the gate-delay degradation have the same slope (= 0.25) as expected from (10). This is also observed experimentally in ring oscillators [15]. It can also be observed from Fig. 1 that the degradation in delay is less than the degradation in threshold voltage. This can be understood from (9). Since Vg − Vth0 is greater than Vth0 (within the time range shown in Fig. 1) and α is close
to one for short-channel transistors, the percentage degradation in delay will be less than that of the threshold voltage and can be quantified as log[(α/(Vg − Vth0 )]. For example, with Vg = 1 V and Vt0 = 0.3 V, a 20% degradation in Vth will cause approximately 10% degradation in the gate delay (9). Fig. 1 also shows the performance degradation of a ninestage ring oscillator with time. The delay was also measured through the HSPICE simulation using the 70-nm BPTM technology with 1-V supply. As expected, the circuit performance degradation also has the same slope as Vth degradation. However, the percentage degradation is further less than that of a single gate. This is because in a circuit, a low-to-high switching is always followed by a high-to-low switching. While a lowto-high switching is affected due to the NBTI-induced Vth degradation, the high-to-low switching is not affected. Hence, the overall performance degradation is approximately half of that of a single gate. III. S IZING FOR R ELIABILITY I MPROVEMENT In this section, a gate-sizing algorithm is proposed, which considers the temporal performance degradation of the circuit into account. The algorithm proposed here is based on a technique called Lagrangian Relaxation (LR) [14] for solving nonlinear optimization problem. Chen et al. [11] proposed the use of LR for simultaneous sizing of gate and interconnects of a combinational circuit to optimize the total area while maintaining a delay constraint. The convergence of the algorithm was proven, and the optimality was verified. In our experiments, we ignored interconnects since interconnects do not play a role in NBTI. However, the algorithm can easily incorporate interconnects. A. Problem Formulation Fig. 2 shows an example circuit representation for sizing with reliability constraint. The circuit consists of n gates, which are to be sized, and s primary inputs. Logic gates and primary inputs are called components. In addition, we add two virtual components, one connecting all primary inputs (component 9 in Fig. 2) and the other connecting primary outputs (component 0). Therefore, for a circuit with n gates and s inputs, there are n + s + 2 components. Edge numbers follow their driver gates, i.e., the output of gate i is denoted as edge i. Note that the components and edges are numbered in reverse topological order. Our objectiveis to minimize the total area which can be represented by αi xi , i = 1, . . . , n where xi is the gate size and αi is an arbitrary constant multiplier for gate i, which can
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vary depending on the objective of optimization. Hence, the sizing problem can be formulated as follows: Minimize
n
αi xi
delay constraints on all the paths are transformed into the delay constraints on each gate in the circuit. Therefore, the sizing problem (which is called the primal problem; PP) is redefined as follows:
i=1
Subject to
Di ≤ A0 ,
∀p ∈ P
PP : Minimize
i∈p
Li ≤ xi ≤ Ui ,
n
αi xi
i=1
i = 1, . . . , n
(12)
Subject to aj ≤ A0 ,
where Li and Ui represent the lower bound and upper bound of the size of gate i, respectively. P is the set of possible paths in a circuit. Di represents the delay of gate i in a path p. Note that threshold voltages of the transistors in all individual gates will be different due to the NBTI depending on their switching activities. The proposed algorithm first calculates the thresholdvoltage degradation of all transistors in a circuit depending on their switching activities and then sizes the circuit to ensure the performance for a desired period of time (e.g., ten years).
aj +Di ≤ ai ,
B. Vth Estimation This algorithm calculates the switching activities of all gates in a circuit for given signal switching probabilities at all primary inputs [16]. Based on the switching activity, the ON-time (Vgs = −Vdd ) of all pMOS transistors is calculated for a desired period of time Tmax (e.g., ten years). Using the ON-time, the thresholdvoltage degradation (∆Vth ) of all pMOS transistors is then calculated from (4). We calculate the delay of each gate using Sakurai’s gatedelay model [17]. In [11], Elmore delay model was used for calculating the arrival-time information. However, we use the Sakurai’s delay model for better accuracy. This model uses precomputed device parameters that are obtained from the I–V characteristics of a particular transistor. However, in our analysis, since the threshold voltage of different transistors is different (hence, the I–V characteristics), we use a lookup table to obtain device parameters corresponding to a particular transistor (threshold voltage). We first obtain and store the device characteristics required for Sakurai’s delay model for different threshold voltages of the transistor. The detailed explanation on how to obtain these parameters for a particular threshold voltage can be found in [17]. In static timing analysis, the worst case delay of each gate is considered to obtain the circuit delay. Hence, based on the circuit topology and the type of the gate, we first find the transistor that is responsible for maximum gate delay. The device parameters corresponding to the threshold voltage of that transistor are then obtained from the lookup table and used in the delay calculation. C. Sizing Algorithm In this section, we explain how to size the circuit using the LR taking the temporal performance degradation into account. Note that the complexity of the problem defined in (12) is exponentially dependent on the number of components in the circuit (O(en )). To reduce the complexity to a linear one, the
j ∈ input(node : 0)/∗ outputs∗ / i = 1, . . . , n
Di ≤ ai ,
∀j ∈ input(i)
i = n+1, . . . , n+s
Li ≤ xi ≤ Ui ,
i = 1, . . . , n
/∗ inputs∗ / (13)
where ai represents the signal arrival time at edge i and Di is the delay associated with gate i considering the temporal performance degradation based on its switching activity. Hence, this algorithm globally optimizes the gate sizes and is not a pathbased algorithm. Also note that the delay constraint A0 is on the circuit delay and not on any specific path in the circuit. In the previous problem, PP is solved by introducing a Lagrangian multiplier λ for each constraint on arrival time as follows:
Minimize : Lλ (x, a) =
n i=1
+
αi xi +
n
λj0 (aj − A0 )
j∈input(0)
λji (aj + Di − ai )
i=1 j∈input(i)
+
n+s
λmi (Di − ai )
(14)
i=n+1
where λji corresponds to the input edge j and output edge i of gate i. m in λmi is equal to n + s + 1 (virtual input node). The flow diagram of the proposed sizing algorithm for reliability improvement is shown in Fig. 3. The algorithm first calculates the switching activities of all gates in a circuit for given signal switching probabilities at all primary inputs. It then estimates the threshold-voltage degradation of all pMOS transistors in the circuit. This information is used to obtain the delay of each gate in the circuit. Finally, Lλ is minimized to obtain minimum size of the circuit for a given delay constraint. Minimizing Lλ using LR consists of iterating the following two steps: 1) calculating the optimal size of the circuit for the current λ values and 2) updating λ to the direction of the optimal solution [11]. In this algorithm, we use Sakurai’s delay model to calculate the gate delay. The mathematical formulation for optimal size of a gate using Sakurai’s delay model is given in the Appendix. Minimizing Lλ provides the minimum size of a circuit while ensuring the performance for a desired period of time Tmax .
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Fig. 4. Percentage degradation in the performance of ISCAS C432 benchmark circuit: 1) with worst case (Si = 1) NBTI stress and 2) with activity-dependent effect.
Fig. 3.
Sizing algorithm for reliability improvement.
IV. S IMULATION R ESULTS We simulated several ISCAS benchmark circuits to estimate their temporal performance degradation due to the NBTI stress and sized them using the proposed algorithm. We considered the following two cases: 1) Vth degradation of all pMOS transistors is the same (worst case condition) and 2) Vth degradation of all individual pMOS transistors is different depending on their ON-time (Vgs = −Vdd ). The ON-time is calculated based on the switching activity of each individual gate. The circuit delay is calculated through a static timing analysis. The delay of each gate was calculated using Sakurai’s gate-delay model [17]. A. Estimation of Performance Degradation Fig. 4 shows the performance degradation of ISCAS C432 benchmark circuit with time. It can be seen that as expected, the slope of log(∆τckt ) versus log(t) plot, both cases 1) and 2) are the same as that of Vth degradation. Also note that the performance degradation considering the switching activity is less than the worst case NBTI stress. The activity factors of all the transistors were calculated by assuming 50% signal switching probability at the primary inputs. Fig. 5 shows the probability density function (pdf) of the threshold-voltage degradation (∆Vth ) considering transistor activities of the same C432 circuit. It can be observed that despite a wide variation in ∆Vth , the performance degradation is almost comparable to the worst case degradation (Fig. 4). We further calculated the per-
Fig. 5. PDF of transistor activities in ISCAS C432 benchmark circuit.
formance degradation of the same circuit (C432) with very low (10%) and high (100%) signal switching probabilities at the primary inputs. It was observed that the performance degradation is a weak function of signal probability. The threshold-voltage degradation of pMOS transistor depends on its ON-time, which changes with the signal probability at the input. However, due to the topology of CMOS circuits, when the ON-time of a particular transistor reduces, the ON-time of transistor in the following gate is likely to increase. This makes the overall performance degradation of a circuit insensitive to the signal probability. Hence, calculating the performance degradation with worst case assumption will not result in a significant over estimation. Note that the above discussion is true for traditional CMOS circuit topology, which occupies the major part of a design. The impact of switching activity may however be different for different circuit types. All other benchmark circuits also show the similar delay degradation characteristics
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TABLE I DELAY DEGRADATION OF ISCAS BENCHMARK CIRCUITS UNDER NBTI
Fig. 7. Area versus delay for ISCAS C432 benchmark circuit. The area was calculated as the sum of transistor width. TABLE II SIZING ISCAS BENCHMARK CIRCUITS CONSIDERING TEMPORAL PERFORMANCE DEGRADATION DUE TO NBTI
Fig. 6. Percentage degradation in the performance of ISCAS C432 benchmark circuit with time-dependent exponent (n).
with time. Table I shows the percentage delay degradation of several ISCAS benchmark circuits with time under both worst case (Si = 1) and activity-dependent (Si < 1) NBTI stress. Though the delay degradation depends on the circuit topology, the expected average delay degradation is about 9.2% (worst case) in ten years, which is approximately four times less than Vth degradation of individual transistors. It has been recently reported that the time exponent (n) of ∆Vth decreases over time [18]. It can be seen from (10) that though n is a function of time, the circuit delay degradation still follows the Vth degradation. This is further confirmed with the simulation of ISCAS C432 circuit shown in Fig. 6. In this analysis, we only considered the degradation of Vth under the NBTI stress. However, the conductivity (gm ) and the capacitance of the transistor are also affected (though not as strongly as Vth ) due to NBTI. The impact of the degradation in these parameters on circuit performance can also be modeled following the same method described in this paper.
B. Sizing Our proposed sizing algorithm was used to size several ISCAS benchmark circuits, taking their temporal performance degradation due to NBTI into account. Fig. 7 shows the areaversus-delay curve of ISCAS C432 benchmark circuit using the conventional LR sizing algorithm. The area (the sum of transistor width) in the plot represents the minimum circuit size for the corresponding delay. Since the area strongly depends on the delay, the area overhead in sizing considering the reliability into account will also depend on the delay constraint. We chose the delay constraint of a circuit from the above area-versusdelay plot where the percentage increase in area is equal to the percentage decrease in delay (e.g., 385 ps for C432). Table II shows the area overhead in sizing the above benchmark circuits using the proposed algorithm to ensure the reliability for ten years. We calculated the area overhead for
PAUL et al.: NBTI: ESTIMATION AND DESIGN FOR IMPROVED RELIABILITY OF NANOSCALE CIRCUITS
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that with an average of 8.7% area overhead, one can avoid the reliability degradation of nanoscale circuits due to NBTI for ten years. A PPENDIX C ALCULATION OF O PTIMUM G ATE S IZE U SING S AKURAI ’ S D ELAY M ODEL
Fig. 8.
Impact of NBTI on different technology generations.
both worst case and activity-dependent performance degradation. We chose 50% signal probability for all the benchmark circuits in our analysis. It can be observed from the table that with an average of 8.7% area overhead (worst case), the temporal performance degradation of digital circuits due to NBTI can be avoided. Note that the area overhead in large circuits (e.g., C3540) is even less (3.44%). Hence, although the threshold-voltage degradation due to NBTI is estimated to be approximately 35% in ten years (in 70-nm technology), a small area overhead is sufficient to ensure the reliable operation of digital circuits. Also note that the area overhead considering the activity of the circuit is not significantly different from the worst case design. Hence, sizing circuits considering the worst case performance degradation will not result in pessimistic design. This further simplifies the design of digital circuits considering the reliability as one of the design constraints. We further analyzed the impact of NBTI on different technology generations. Fig. 8 shows the percentage degradation (in ten years) in threshold voltage in 100-, 70-, and 45-nm technologies (BPTM), respectively. The increase in Vth degradation with technology scaling is expected due to the increase in oxide field. It can also be observed that the average delay degradation (in all ISCAS benchmark circuits) is approximately four times less than that of Vth . Recently, statistical sizing techniques have been proposed to size circuits considering process variations [19], [20]. Our proposed sizing technique can also be incorporated with those tools by properly modifying the threshold voltage of transistors due to NBTI.
Calculation of the optimal size (Fig. 3) involves the sizing of each gate in such a way that Lλ is locally minimized. Since Di in Lλ is a function of gate size xi , the optimal size of a gate can be obtained by solving (dLλ /dxi ) = 0. It was shown in [11] that Lλ can be simplified to Lµ using the optimality condition as follows: Lµ =
n+s i=1
µi =
n
αi xi − µ0 A0
i=1
λji
i = 1, . . . , n (15)
j∈input(i)
λmi
i = n + 1, . . . , n + s.
Note that Lµ is a function of µ, not λ. When the circuit is iteratively sized, the optimum size xi,opt which minimizes Lµ is calculated for gate i. Based on Sakurai’s delay model [17], delay associated with a gate i, Di can be represented as follows for fast inputs1 (slow input case can be solved similarly): Di =
2 4vD0 CI VDD 0.7ID0IN 4vD0 − 1
1 − vT (vV − vT )n+1 CO VDD × 0.5 − + + 0.5 n+1 (n + 1)(1 − vT )n ID0
(16)
where CI and CO represent the input and output capacitances of a gate, respectively. ID0 is the drain current for VGS = VDS = VDD , where VDD is the supply voltage. vD0 = VD0 /VDD , vT = VT 0 /VDD , and vV = VINV /VDD , where VD0 is the drain saturation voltage for VGS = VDD , VT 0 is the saturation voltage, and VINV is the logic threshold voltage. n denotes the constant that controls the drain current in saturation region. The complete derivation of the gate delay can be found in [17]. Note from the above equation that CI and ID0 can be represented as a linear function of the transistor size (or equivalently the gate size) xi as CI = β1 xi and ID0 = β2 xi . Then, the gate delay Di becomes
V. C ONCLUSION In this paper, we analyzed the performance degradation of digital circuits due to the NBTI stress. It is shown that the overall performance degradation of a circuit is significantly less than the threshold-voltage degradation of individual transistors and that it can be handled by employing a sizing technique with an additional reliability constraint. We also proposed a sizing algorithm considering the temporal performance degradation into account. This algorithm ensures the performance of circuits for a desired period of time under the NBTI-affected threshold-voltage degradation. Simulation results on several ISCAS benchmark circuits in BPTM 70-nm technology show
µi Di +
Di = γ1 xi +
γ2 xi
(17)
where 2 β1 VDD 4vD0 γ1 = 0.7ID0IN 4vD0 −1
γ2 =
1 The
(vV −vT )n+1 1−vT + 0.5− n+1 (n+1)(1−vT )n
CO VDD . β2
delay equation presented is also under zero-body bias assumption.
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By inserting Di into Lµ shown in (15), we get Lµ = (αi + µi γ1 )xi +
µi γ2 + terms independent of xi . xi
By setting dLµ /dxi = 0, the optimal size of gate i, xi,opt can be obtained as follows: µi γ2 xi,opt = min Ui , max Li , (18) αi + µi γ1 where Li and Ui are the lower and upper bounds of gate size xi , respectively. For n gates in a circuit, each gate is sized according to xi,opt shown previously, and the timing analysis is performed. R EFERENCES [1] N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi, “Impact of bias temperature instability for direct tunneling ultrathin gate oxide on MOSFET scaling,” in Proc. Symp. VLSI Technol. Tech. Dig. Papers, 1999, pp. 73–74. [2] G. Chen, M. F. Li, C. H. Ang, J. Z. Zheng, and D. L. Kwong, “Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling,” IEEE Electron Device Lett., vol. 23, no. 12, pp. 734–736, Dec. 2002. [3] Y. H. Lee, N. Mielke, B. Sabi, S. Stadler, R. Nachman, and S. Hu, “Effect of pMOST bias-temperature instability on circuit reliability performance,” in Proc. IEDM Tech. Dig., 2003, pp. 14.6.1–14.6.4. [4] D. Schroder and J. F. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl. Phys., vol. 94, no. 1, pp. 1–18, 2003. [5] M. A. Alam, “A critical examination of the mechanics of dynamic NBTI for PMOSFETs,” in Proc. IEDM, 2003, pp. 346–349. [6] S. Zafar, B. H. Lee, and J. Stathis, “Evaluation of NBTI in HfO/sub 2/gate dielectric stacks with tungsten gates,” IEEE Electron Device Lett., vol. 25, no. 3, pp. 153–155, Mar. 2004. [7] W. Abadeer and W. Ellis, “Behavior of NBTI under AC dynamic circuit conditions,” in Proc. IRPS, 2003, pp. 17–22. [8] V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, “Impact of negative bias temperature instability on digital circuit reliability,” in Proc. IRPS, 2002, pp. 248–253. [9] A. T. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, and S. Krishnan, “NBTI impact on transistor and circuit: Models, mechanisms and scaling effects,” in Proc. IEDM, 2003, pp. 14.5.1–14.5.4. [10] B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Impact of NBTI on the temporal performance degradation of digital circuits,” IEEE Electron Device Lett., vol. 26, no. 8, pp. 560–562, Aug. 2005. [11] C. P. Chen, C. C. N. Chu, and D. F. Wong, “Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation,” IEEE Trans. Comput.Aided Design Integr. Circuits Syst., vol. 18, no. 7, pp. 1014–1025, Jul. 1999. [12] Device Group, Dept. Elect. Eng. Comput. Sci., Univ. California, Berkeley. [Online]. Available: http://www-device.eecs.berkeley.edu/ptm [13] M. A. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation,” Microelectron. Reliab., vol. 45, no. 1, pp. 71–81, Jan. 2005. [14] M. S. Bazaraa, H. D. Sherali, and C. M. Shetty, Nonlinear Programming: Theory and Algorithms, 2nd ed. Hoboken, NJ: Wiley, 1993. [15] V. Reddy, J. Carulli, A. Krishnan, W. Bosch, and B. Burgess, “Impact of negative bias temperature instability on product parametric drift,” in Proc. ITC, 2004, pp. 148–155. [16] Z. Chen, K. Roy, and T. Chou, “Power sensitivity—A new method to estimate power dissipation considering uncertain specifications of primary inputs,” in Proc. ICCAD, 1997, pp. 40–44. [17] T. Sakurai and R. Newton, “Delay analysis of series-connected MOSFET circuits,” IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 122–131, Feb. 1991. [18] S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan, “A comprehensive framework for predictive modeling of negative bias temperature instability,” in Proc. IRPS, 2004, pp. 273–282. [19] E. T. A. F. Jacobs and M. R. C. M. Berkelaar, “Gate sizing using statistical delay model,” in Proc. DATE, 2000, pp. 283–290. [20] S. H. Choi, B. C. Paul, and K. Roy, “Novel sizing algorithm for yield improvement under process variation,” in Proc. DAC, 2004, pp. 454–459.
Bipul C. Paul (S’97–M’01–SM’05) received the B.Tech. and M.Tech. degrees in radiophysics and electronics from University of Calcutta, Kolkata, West Bengal, India, and the Ph.D. degree from Indian Institute of Science (IISc), Bangalore, India. After his graduation, he joined Alliance Semiconductor (India), where he worked on synchronous DRAM design. In 2000, he joined Purdue University, West Lafayette, IN, as a Post Doctoral Fellow, where he worked on low-power electronic design of nanoscale circuits (both bulk and SOI technologies), statistical design under process variation, VLSI testing, verification, and noise analysis. He has also developed device and circuit optimization techniques for ultralow power digital subthreshold operation. He is currently with the Toshiba America Research Inc., San Jose, CA, where he is working on post-silicon device modeling, 3-D circuit design, and nanoarchitecture. He is also a Visiting Scientist with Stanford University, Stanford, CA. Dr. Paul received the National scholarship, India, in 1984, the Senior Research Fellowship Award from CSIR, India, in 1995, the Best Thesis Award in 1999, and the 2006 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Best Paper Award.
Kunhyuk Kang (S’04) received the B.S. degree from Seoul National University, Seoul, Korea, in 2002, and the M.S. degree from Rensselaer Polytechnic Institute, Troy, NY, in 2003, both in electrical engineering. He is currently working toward the Ph.D. degree in electrical engineering at Purdue University, West Lafayette, IN. In the summer of 2005, he was an Intern with Texas Development Center, Intel Corporation, Austin, TX, where he performed research in static timing analysis. His research interests include statistical design, timing analysis, CAD, and design for reliability.
Haldun Kufluoglu (S’04) was born in Turkey, in 1979. He received the B.S. and M.S. degrees in electrical engineering from Purdue University, West Lafayette, IN, in 2001 and 2003, respectively, where he is currently working toward the Ph.D. degree. Particularly, his Ph.D. research involves measurements and theoretical modeling of MOSFET degradation mechanisms such as NBTI, HCI, and TDDB, and their implications on VLSI design. His research interests include MOSFET reliability, experimental characterization, and modeling of semiconductor devices. He also participates in OFF-state transistor reliability assessment. Previously, he obtained microfabrication skills in a MEMS-based sensor that was interfaced with live neurons for biological applications.
PAUL et al.: NBTI: ESTIMATION AND DESIGN FOR IMPROVED RELIABILITY OF NANOSCALE CIRCUITS
Muhammad A. Alam (F’05) received the B.S.E.E. degree from Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, in 1988, the M.S. degree from Clarkson University, Potsdam, NY, in 1991, and the Ph.D. degree from Purdue University, Lafayette, IN, in 1994, all in electrical engineering. From 1995 to 2001, he was with Bell Laboratories, Lucent Technologies, Murray Hill, NJ, as a member of technical staff with the Silicon ULSI Research Department. From 2001 to 2003, he was a distinguished member of technical staff and the Technical Manager with the IC Reliability Group at Agere Systems, Murray Hill. In 2004, he joined Purdue University, West Lafayette, IN, where he is currently a Professor of electrical and computer engineering, where his research and teaching focus on physics, simulation, characterization, and technology of classical and novel semiconductor devices. His current research includes theory of oxide reliability, transport in nanocomposite thin film transistors, and nanobio sensors. He has published over 75 papers in international journals and has presented many invited and contributed talks at international conferences. Dr. Alam received IRPS Best Paper Award in 2003 and an Outstanding Paper Award in 2001, both for his work on gate oxide reliability. Most recently, he was elected an IEEE Fellow for contribution to physics of CMOS reliability and simulation of optoelectronic devices and received IEEE Kiyo Tomiyasu Award for contributions to device technology for communication systems.
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Kaushik Roy (S’83–M’83–SM’95–F’02) received the B.Tech. degree in electronics and electrical communications engineering from Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois, Urbana-Champaign, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and lowpower circuit design. In 1993, he joined the Electrical and Computer Engineering Faculty at Purdue University, West Lafayette, IN, where he is currently a Professor and a Purdue University Faculty Scholar Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 200 papers in refereed journals and conferences, holds five patents, and has coauthored a book on Low Power CMOS VLSI Design (John Wiley). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM Faculty Partnership Award, ATT/Lucent Foundation Award, and Best Paper Awards at 1997 International Test Conference and 2000 International Symposium on Quality of IC Design. He is in the editorial board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was a Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).
