Noise Margin Analysis for Dynamic Logic Circuits - Semantic Scholar
Noise Margin Analysis for Dynamic Logic Circuits Suwen Yang and Mark Greenstreet University of British Columbia
{swyang, mrg}@cs.ubc.ca
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.1/30
Contribution Introduced a sensitivity matrix for robustness analysis of a circuit applied the sensitivity matrix for small signal analysis developed a non-linear constrained optimization model to calculate the dynamic noise margin.
Quantified the noise margin of dynamic logic circuits
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.2/30
Overview Robustness Small Signal Analysis
Large Signal Analysis
A circuit is a dynamic system
min ∆ in , s.t. ∆ out > ∆ in
Sensitivity Matrix
Eigenvalues identify propagating modes
Use numerical optimization to find propagating modes
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.3/30
Outline Overview of Noise Analysis Sensitivity Matrix Small Signal Stability Large Signal Stability Conclusion
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.4/30
Outline Noise Analysis Static Noise Margin Dynamic Noise Margin
Sensitivity Matrix Small Signal Stability Large Signal Stability Conclusion
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.5/30
Static Noise Analysis Vout VOH VOUH +1
+1 VOUL VOL VOL
VIL
NM L
VIH
VOH
Vin
NM H
Guarantees disturbances won’t propagate through a chain of gates. Neglects dynamic behaviour: noise often exhibits a narrow pulse width gates act as low pass filters dynamic gates have time varying response ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.6/30
Dynamic Noise Analysis Previous work: Latch transition failure criterion [Zolotov+ 02] Modeling noise with fixed-shape pulses [Larsson+ 94, Gemmeke+ 04, Shepard+ 00] Static gain failure criterion [Zolotov+ 02] Dynamic gain failure criterion [Shepard+ 00, Shepard+ 96]
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.7/30
Dynamic Noise Analysis Previous work: Latch transition failure criterion [Zolotov+ 02] : Noise creates a failure by changing the state of a memory element. Corresponds to system failure. How to get the worst case scenario? Modeling noise with fixed-shape pulses [Larsson+ 94, Gemmeke+ 04, Shepard+ 00] Static gain failure criterion [Zolotov+ 02] Dynamic gain failure criterion [Shepard+ 00, Shepard+ 96]
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.7/30
Dynamic Noise Analysis Previous work: Latch transition failure criterion [Zolotov+ 02] Modeling noise with fixed-shape pulses [Larsson+ 94, Gemmeke+ 04, Shepard+ 00] : Simplifies search space. Doesn’t correspond to real noise. Provides no guarantee of correct operation. Static gain failure criterion [Zolotov+ 02] Dynamic gain failure criterion [Shepard+ 00, Shepard+ 96]
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.7/30
Dynamic Noise Analysis Previous work: Latch transition failure criterion [Zolotov+ 02] Modeling noise with fixed-shape pulses [Larsson+ 94, Gemmeke+ 04, Shepard+ 00] Static gain failure criterion [Zolotov+ 02] : The output voltage of the victim net exceeds the static noise margin It is still conservative Dynamic gain failure criterion [Shepard+ 00, Shepard+ 96]
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.7/30
Dynamic Noise Analysis Previous work: Latch transition failure criterion [Zolotov+ 02] Modeling noise with fixed-shape pulses [Larsson+ 94, Gemmeke+ 04, Shepard+ 00] Static gain failure criterion [Zolotov+ 02] Dynamic gain failure criterion [Shepard+ 00, Shepard+ 96] : Measure sensitivity of output waveform to DC offset of input in presence of disturbance pulse. Provides no guarantees – it can under- or over-estimate the noise margin.
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.7/30
Noise Analysis The noise margins of dynamic logic circuits depend on the noise’s duration, magnitude, shape, and arrival time.
voltage(V)
Output Prediction Logic [McMurchie+ 00]:
in
out2
out1
1.8 1.6
out 1
in
1.4 1.2 1
out 2
0.8 0.6
clock1
clock2
clock1
0.4 0.2 0
clock2 2.6
2.7
2.8
2.9
time(s)
3
3.1 −9
x 10
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.8/30
Noise Analysis The noise margins of dynamic logic circuits depend on the noise’s duration, magnitude, shape, and arrival time.
voltage(V)
Output Prediction Logic [McMurchie+ 00]:
in
out2
out1
t1
1.8 1.6
t2
out 1
in
1.4 1.2 1
out 2
0.8 0.6
clock1
clock2
clock1
0.4 0.2 0
clock2 2.6
2.7
2.8
2.9
3
time(s)
3.1 −9
x 10
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.8/30
Outline Overview of Noise Analysis Sensitivity Matrix Definition How to Calculate the Sensitivity Matrix
Small Signal Stability Large Signal Stability Conclusion
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.9/30
The Sensitivity Matrix (part 1)
in
out t
i
t j+d
We use a discrete approximation of time. S(j, i) is the perturbation at the output of a gate at time tj + d when a unit perturbation is applied to the input of the gate at time ti and the input of this gate is then returned to its non-perturbed value at time ti+1 . ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.10/30
The Sensitivity Matrix (part 2)
∆Vout
S
∆Vin
∆Vin represents a perturbation applied to the input of a gate. ∆Vout represents the resulting change in the output waveform. Columns of S correspond to time points of the input sequence. Rows correspond to time points of the output.
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.11/30
Small Signal Stability 2
1.5
undisturbed input disturbed input input noise
1
undisturbed output disturbed output
0.5
output noise 0
λ=0.2391 −0.5 1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8 −9
x 10
Eigenvalues of S give the sensitivity of the circuit to small disturbances. If all eigenvalues have magnitudes less than one, then disturbances cannot propagate through a long chain of gates. The eigenvectors are the propagating modes for small disturbances. ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.12/30
Calculating the Sensitivity Matrix Numerical differencing unacceptable slow: requires a separate integration for each input time point. inaccurate: amplifies errors of the numerical integrator. Our approach: Let Γtj ,ti (y, x) be the response on node y at time tj to a perturbation of node x at time ti . Two handy properties of Γ: Γ˙
= Jac(f (v)),
Γtk ,ti
= Γtk ,tj Γtj ,ti
where v˙
= f (v) is the circuit model
S(j, i) = Γtj ,ti (in, out). We calculate Γ in a single integration pass. No numerical differencing. ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.13/30
Outline Robustness Small Signal Analysis
Large Signal Analysis
A circuit is a dynamic system
min ∆ in , s.t. ∆ out > ∆ in
Sensitivity Matrix
Eigenvalues identify propagating modes
Use numerical optimization to find propagating modes
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.14/30
Circuits 2.67/1.67
p
16
16
16
out
in 8
keeper
1.67
out
x
in
8
static buffer
8
26.67/12
self_resetting domino
8
8
8
in
out2
out1
8
8
clock1
8
8
clock2
8
OPL buffer ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.15/30
Analysis of Static Buffers 2
undisturbed input
1.5
voltage
1
0.5
λ=0.9934
0
λ=0.9972 −0.5
0
100
200
300 time(*2ps)
400
500
600
maximum eigenvalues: 0.9972, 0.9934, 0.0026, 0.0025, 1.25e-5, and 1.24e-5 eigenvectors shift the timing of transitions ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.16/30
voltage(V)
Analysis of Self-Resetting Domino 2
undisturbed input
1.5
1
0.5
λ=0.9907
λ=0.0404
0
−0.5 2.1
2.15
2.2
2.25
2.3
2.35
2.4
time(ns)
2.45
2.5
2.55
2.6 −9
x 10
maximum eigenvalues: 0.9907, 0.0404 eigenvectors shift the timing of the rising and falling events respectively ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.17/30
voltage(V)
Analysis of an OPL Buffer 2
undisturbed input
1.5
1
0.5
0
λ=0.2413 −0.5 1.8
2
2.2
2.4
2.6
2.8
time(s)
3 −9
x 10
input is 1, maximum eigenvalue: 0.2391 input is 0, maximum eigenvalue value: 0.2413 ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.18/30
voltage(V)
Analysis of an OPL Buffer 2
undisturbed input
1.5
1
0.5
0
λ=0.2391 −0.5 1.9
2
2.1
2.2
2.3
2.4
2.5
time(s)
2.6
2.7 −9
x 10
input is 1, maximum eigenvalue: 0.2391 input is 0, maximum eigenvalue value: 0.2413 ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.18/30
Eigenvalues and Noise Propagation Buffer with ideal maximum eigenvalue equal to 1: 1.8 1.6 1.4
voltage(V)
1.2 1 0.8 0.6 0.4 0.2 0 1.95
2
2.05
2.1
2.15 time(s)
2.2
2.25
2.3
2.35 −9
x 10
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.19/30
Eigenvalues and Noise Propagation OPL with maximum eigenvalue less than 1:
1.7
voltage(V)
1.6
1.5
1.4
1.3
1.2
2
2.2
2.4
2.6 time(s)
2.8
3
3.2 −9
x 10
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.19/30
Application to Circuit Design largest eigenvalue
Effects of varying stage delay 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 10
15
20
25
30
35
time(ps)
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.20/30
Outline Robustness Small Signal Analysis
Large Signal Analysis
A circuit is a dynamic system
min ∆ in , s.t. ∆ out > ∆ in
Sensitivity Matrix
Eigenvalues identify propagating modes
Use numerical optimization to find propagating modes
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.21/30
Problem Formulation Measure disturbances with respect to a circuit with undisturbed signals. What is the smallest disturbance at the input of a gate that will create a disturbance that is at least as large as the input? Dynamic noise margin: min
P
P
P
△in (i)2 , s.t. 2
△out (i) ≥
P
△in (i)2
△in (i)2 > 0
Matlab’s optimization function fmincon is used to solve this problem. The sensitivity matrix helps to guide the search direction at each iteration. ∇(
P
△out (i)2 ) = 2S T △out
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.22/30
noise margin(V 2*ps)
Noise Margin with Input = 0 180
buffer(delay=75.9ps)
160 140 120
self−resetting domino(delay=70.6ps)
100 80
OPL(delay=70ps)
60
OPL(delay=50ps)
40
OPL(delay=40ps) OPL(delay=26ps)
20 0
0
5
10
15
gates in the chain
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.23/30
voltage(V)
voltage(V)
Noise with Input = 0 1.8
static buffer
1.6 1.4
self−resetting domino
1.6 1.4 1.2
voltage(v)
1.2 voltage(v)
1.8
1 0.8
1 0.8
0.6
0.6
0.4
0.4
0.2
0.2
0 40
50
60
70 80 time(*5ps)
90
0
100
0
5
10
25
opl(delay=70ps)
1
0.9
0.7
0.8
0.6
0.7
voltage(v)
voltage(v)
20
time(*5ps)
opl(delay=40ps)
0.8
15 time(*5ps)
voltage(V)
voltage(V)
time(*5ps)
0.5 0.4
0.6 0.5 0.4
0.3
0.3 0.2 0.2 0.1
0.1
0 35
40
45
50
55
time(*5ps) time(*5ps)
60
65
70
75
0 50
60
70
80
90
100
110
time(*5ps) time(*5ps)
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.24/30
250
buffer(delay=75.9ps)
2
noise margin(V *ps)
Noise Margin with Input = 1
200
150
100
OPL(delay=70ps) OPL(delay=50ps)
50
OPL(delay=40ps) 0
OPL(delay=26ps) 0
2
4
6
8
10
12
14
gates in the chain
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.25/30
Noise Margin of OPL Buffer 70 noise margin with input = 0 y = 2.754x−31.32 noise margin with input = 1 y=2.149x − 23.12
60
noise margin
50
40
30
20
10
0 25
30
35
40
45 50 delay(ps)
55
60
65
70
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.26/30
voltage
Noise Margin of OPL Buffer 0.4
1.2
input is 0
input is 1
0.2
1 0
0.8 −0.2
0.6 −0.4
0.4 −0.6
0.2 −0.8
0 0
10
20
30
40
50
−1
0
10
20
30
40
50
60
70
sample point
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.27/30
computation time(minutes)
Computation Time 200
+ x * o
180
160
OPL with input = 0 OPL with input = 1 inverter with input = 1 inverter with input = 0 domino with input = 0
140
120
100
80
60
40
20
0
0
5
10
15
gates in the chain
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.28/30
Summary Contribution: introduced the sensitivity matrix for robustness analysis of a circuit small signal stability analysis large signal dynamic noise margin quantified the timing stability of dynamic circuits
Future Work: explore other metrics such as l1 and l∞ explore energy vs. delay vs. robustness apply to other classes of circuits can we show global optimality? use “industrial strength” models
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.29/30
The End Future Work: explore the other metric such as l1 and l∞ how to find a good initial condition? apply more sophisticate transistor models explore the optimization model to other circuits such as Differential Logic, Complex Domino Logic and so on.
Thanks! ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.30/30
The End Future Work: explore the other metric such as l1 and l∞ how to find a good initial condition? apply more sophisticate transistor models explore the optimization model to other circuits such as Differential Logic, Complex Domino Logic and so on.
Thanks! ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.30/30
˜ Noll. A physically ori[Gemmeke+ 04] T. Gemmeke and T.G. ented model to quantify the dynamic noise margin. In Proceeding of the 30th European Conference on Solid-State Circuits, pages 467–470, September 2004. [Larsson+ 94] P. Larsson and C. Svensson. Noise in digital dynamic cmos circuits. IEEE Journal of Solid-State Circuits, 29(6):655–662, June 1994. [McMurchie+ 00] Larry McMurchie, Su Kio, et al. Output prediction logic: A high-performance CMOS design technique. In Proceedings of the 2000 International Conference on Computer Design, pages 247–254, 2000. [Shepard+ 00] K.L. Shepard and K. Chou. Cell characterization for noise stability. IEEE 2000 Custom Integrated Circuits Conference, pages 91–94, 2000. [Shepard+ 96] K.L. Shepard and V. Narayanan. Noise in deep submicron digital design. In Proceedings of the 1996 International Conference on Computer Aided Design, pages 406–411, 1996. [Zolotov+ 02] V. Zolotov, D. Blaauw, et al. Noise propagation and failure criteria for vlsi designs. In
30-1
IEEE/ACM International Conference on Computer Aided Design, pages 587–594, November 2002.
30-1
{swyang, mrg}@cs.ubc.ca
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.1/30
Contribution Introduced a sensitivity matrix for robustness analysis of a circuit applied the sensitivity matrix for small signal analysis developed a non-linear constrained optimization model to calculate the dynamic noise margin.
Quantified the noise margin of dynamic logic circuits
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.2/30
Overview Robustness Small Signal Analysis
Large Signal Analysis
A circuit is a dynamic system
min ∆ in , s.t. ∆ out > ∆ in
Sensitivity Matrix
Eigenvalues identify propagating modes
Use numerical optimization to find propagating modes
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.3/30
Outline Overview of Noise Analysis Sensitivity Matrix Small Signal Stability Large Signal Stability Conclusion
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.4/30
Outline Noise Analysis Static Noise Margin Dynamic Noise Margin
Sensitivity Matrix Small Signal Stability Large Signal Stability Conclusion
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.5/30
Static Noise Analysis Vout VOH VOUH +1
+1 VOUL VOL VOL
VIL
NM L
VIH
VOH
Vin
NM H
Guarantees disturbances won’t propagate through a chain of gates. Neglects dynamic behaviour: noise often exhibits a narrow pulse width gates act as low pass filters dynamic gates have time varying response ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.6/30
Dynamic Noise Analysis Previous work: Latch transition failure criterion [Zolotov+ 02] Modeling noise with fixed-shape pulses [Larsson+ 94, Gemmeke+ 04, Shepard+ 00] Static gain failure criterion [Zolotov+ 02] Dynamic gain failure criterion [Shepard+ 00, Shepard+ 96]
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.7/30
Dynamic Noise Analysis Previous work: Latch transition failure criterion [Zolotov+ 02] : Noise creates a failure by changing the state of a memory element. Corresponds to system failure. How to get the worst case scenario? Modeling noise with fixed-shape pulses [Larsson+ 94, Gemmeke+ 04, Shepard+ 00] Static gain failure criterion [Zolotov+ 02] Dynamic gain failure criterion [Shepard+ 00, Shepard+ 96]
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.7/30
Dynamic Noise Analysis Previous work: Latch transition failure criterion [Zolotov+ 02] Modeling noise with fixed-shape pulses [Larsson+ 94, Gemmeke+ 04, Shepard+ 00] : Simplifies search space. Doesn’t correspond to real noise. Provides no guarantee of correct operation. Static gain failure criterion [Zolotov+ 02] Dynamic gain failure criterion [Shepard+ 00, Shepard+ 96]
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.7/30
Dynamic Noise Analysis Previous work: Latch transition failure criterion [Zolotov+ 02] Modeling noise with fixed-shape pulses [Larsson+ 94, Gemmeke+ 04, Shepard+ 00] Static gain failure criterion [Zolotov+ 02] : The output voltage of the victim net exceeds the static noise margin It is still conservative Dynamic gain failure criterion [Shepard+ 00, Shepard+ 96]
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.7/30
Dynamic Noise Analysis Previous work: Latch transition failure criterion [Zolotov+ 02] Modeling noise with fixed-shape pulses [Larsson+ 94, Gemmeke+ 04, Shepard+ 00] Static gain failure criterion [Zolotov+ 02] Dynamic gain failure criterion [Shepard+ 00, Shepard+ 96] : Measure sensitivity of output waveform to DC offset of input in presence of disturbance pulse. Provides no guarantees – it can under- or over-estimate the noise margin.
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.7/30
Noise Analysis The noise margins of dynamic logic circuits depend on the noise’s duration, magnitude, shape, and arrival time.
voltage(V)
Output Prediction Logic [McMurchie+ 00]:
in
out2
out1
1.8 1.6
out 1
in
1.4 1.2 1
out 2
0.8 0.6
clock1
clock2
clock1
0.4 0.2 0
clock2 2.6
2.7
2.8
2.9
time(s)
3
3.1 −9
x 10
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.8/30
Noise Analysis The noise margins of dynamic logic circuits depend on the noise’s duration, magnitude, shape, and arrival time.
voltage(V)
Output Prediction Logic [McMurchie+ 00]:
in
out2
out1
t1
1.8 1.6
t2
out 1
in
1.4 1.2 1
out 2
0.8 0.6
clock1
clock2
clock1
0.4 0.2 0
clock2 2.6
2.7
2.8
2.9
3
time(s)
3.1 −9
x 10
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.8/30
Outline Overview of Noise Analysis Sensitivity Matrix Definition How to Calculate the Sensitivity Matrix
Small Signal Stability Large Signal Stability Conclusion
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.9/30
The Sensitivity Matrix (part 1)
in
out t
i
t j+d
We use a discrete approximation of time. S(j, i) is the perturbation at the output of a gate at time tj + d when a unit perturbation is applied to the input of the gate at time ti and the input of this gate is then returned to its non-perturbed value at time ti+1 . ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.10/30
The Sensitivity Matrix (part 2)
∆Vout
S
∆Vin
∆Vin represents a perturbation applied to the input of a gate. ∆Vout represents the resulting change in the output waveform. Columns of S correspond to time points of the input sequence. Rows correspond to time points of the output.
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.11/30
Small Signal Stability 2
1.5
undisturbed input disturbed input input noise
1
undisturbed output disturbed output
0.5
output noise 0
λ=0.2391 −0.5 1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8 −9
x 10
Eigenvalues of S give the sensitivity of the circuit to small disturbances. If all eigenvalues have magnitudes less than one, then disturbances cannot propagate through a long chain of gates. The eigenvectors are the propagating modes for small disturbances. ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.12/30
Calculating the Sensitivity Matrix Numerical differencing unacceptable slow: requires a separate integration for each input time point. inaccurate: amplifies errors of the numerical integrator. Our approach: Let Γtj ,ti (y, x) be the response on node y at time tj to a perturbation of node x at time ti . Two handy properties of Γ: Γ˙
= Jac(f (v)),
Γtk ,ti
= Γtk ,tj Γtj ,ti
where v˙
= f (v) is the circuit model
S(j, i) = Γtj ,ti (in, out). We calculate Γ in a single integration pass. No numerical differencing. ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.13/30
Outline Robustness Small Signal Analysis
Large Signal Analysis
A circuit is a dynamic system
min ∆ in , s.t. ∆ out > ∆ in
Sensitivity Matrix
Eigenvalues identify propagating modes
Use numerical optimization to find propagating modes
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.14/30
Circuits 2.67/1.67
p
16
16
16
out
in 8
keeper
1.67
out
x
in
8
static buffer
8
26.67/12
self_resetting domino
8
8
8
in
out2
out1
8
8
clock1
8
8
clock2
8
OPL buffer ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.15/30
Analysis of Static Buffers 2
undisturbed input
1.5
voltage
1
0.5
λ=0.9934
0
λ=0.9972 −0.5
0
100
200
300 time(*2ps)
400
500
600
maximum eigenvalues: 0.9972, 0.9934, 0.0026, 0.0025, 1.25e-5, and 1.24e-5 eigenvectors shift the timing of transitions ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.16/30
voltage(V)
Analysis of Self-Resetting Domino 2
undisturbed input
1.5
1
0.5
λ=0.9907
λ=0.0404
0
−0.5 2.1
2.15
2.2
2.25
2.3
2.35
2.4
time(ns)
2.45
2.5
2.55
2.6 −9
x 10
maximum eigenvalues: 0.9907, 0.0404 eigenvectors shift the timing of the rising and falling events respectively ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.17/30
voltage(V)
Analysis of an OPL Buffer 2
undisturbed input
1.5
1
0.5
0
λ=0.2413 −0.5 1.8
2
2.2
2.4
2.6
2.8
time(s)
3 −9
x 10
input is 1, maximum eigenvalue: 0.2391 input is 0, maximum eigenvalue value: 0.2413 ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.18/30
voltage(V)
Analysis of an OPL Buffer 2
undisturbed input
1.5
1
0.5
0
λ=0.2391 −0.5 1.9
2
2.1
2.2
2.3
2.4
2.5
time(s)
2.6
2.7 −9
x 10
input is 1, maximum eigenvalue: 0.2391 input is 0, maximum eigenvalue value: 0.2413 ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.18/30
Eigenvalues and Noise Propagation Buffer with ideal maximum eigenvalue equal to 1: 1.8 1.6 1.4
voltage(V)
1.2 1 0.8 0.6 0.4 0.2 0 1.95
2
2.05
2.1
2.15 time(s)
2.2
2.25
2.3
2.35 −9
x 10
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.19/30
Eigenvalues and Noise Propagation OPL with maximum eigenvalue less than 1:
1.7
voltage(V)
1.6
1.5
1.4
1.3
1.2
2
2.2
2.4
2.6 time(s)
2.8
3
3.2 −9
x 10
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.19/30
Application to Circuit Design largest eigenvalue
Effects of varying stage delay 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 10
15
20
25
30
35
time(ps)
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.20/30
Outline Robustness Small Signal Analysis
Large Signal Analysis
A circuit is a dynamic system
min ∆ in , s.t. ∆ out > ∆ in
Sensitivity Matrix
Eigenvalues identify propagating modes
Use numerical optimization to find propagating modes
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.21/30
Problem Formulation Measure disturbances with respect to a circuit with undisturbed signals. What is the smallest disturbance at the input of a gate that will create a disturbance that is at least as large as the input? Dynamic noise margin: min
P
P
P
△in (i)2 , s.t. 2
△out (i) ≥
P
△in (i)2
△in (i)2 > 0
Matlab’s optimization function fmincon is used to solve this problem. The sensitivity matrix helps to guide the search direction at each iteration. ∇(
P
△out (i)2 ) = 2S T △out
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.22/30
noise margin(V 2*ps)
Noise Margin with Input = 0 180
buffer(delay=75.9ps)
160 140 120
self−resetting domino(delay=70.6ps)
100 80
OPL(delay=70ps)
60
OPL(delay=50ps)
40
OPL(delay=40ps) OPL(delay=26ps)
20 0
0
5
10
15
gates in the chain
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.23/30
voltage(V)
voltage(V)
Noise with Input = 0 1.8
static buffer
1.6 1.4
self−resetting domino
1.6 1.4 1.2
voltage(v)
1.2 voltage(v)
1.8
1 0.8
1 0.8
0.6
0.6
0.4
0.4
0.2
0.2
0 40
50
60
70 80 time(*5ps)
90
0
100
0
5
10
25
opl(delay=70ps)
1
0.9
0.7
0.8
0.6
0.7
voltage(v)
voltage(v)
20
time(*5ps)
opl(delay=40ps)
0.8
15 time(*5ps)
voltage(V)
voltage(V)
time(*5ps)
0.5 0.4
0.6 0.5 0.4
0.3
0.3 0.2 0.2 0.1
0.1
0 35
40
45
50
55
time(*5ps) time(*5ps)
60
65
70
75
0 50
60
70
80
90
100
110
time(*5ps) time(*5ps)
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.24/30
250
buffer(delay=75.9ps)
2
noise margin(V *ps)
Noise Margin with Input = 1
200
150
100
OPL(delay=70ps) OPL(delay=50ps)
50
OPL(delay=40ps) 0
OPL(delay=26ps) 0
2
4
6
8
10
12
14
gates in the chain
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.25/30
Noise Margin of OPL Buffer 70 noise margin with input = 0 y = 2.754x−31.32 noise margin with input = 1 y=2.149x − 23.12
60
noise margin
50
40
30
20
10
0 25
30
35
40
45 50 delay(ps)
55
60
65
70
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.26/30
voltage
Noise Margin of OPL Buffer 0.4
1.2
input is 0
input is 1
0.2
1 0
0.8 −0.2
0.6 −0.4
0.4 −0.6
0.2 −0.8
0 0
10
20
30
40
50
−1
0
10
20
30
40
50
60
70
sample point
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.27/30
computation time(minutes)
Computation Time 200
+ x * o
180
160
OPL with input = 0 OPL with input = 1 inverter with input = 1 inverter with input = 0 domino with input = 0
140
120
100
80
60
40
20
0
0
5
10
15
gates in the chain
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.28/30
Summary Contribution: introduced the sensitivity matrix for robustness analysis of a circuit small signal stability analysis large signal dynamic noise margin quantified the timing stability of dynamic circuits
Future Work: explore other metrics such as l1 and l∞ explore energy vs. delay vs. robustness apply to other classes of circuits can we show global optimality? use “industrial strength” models
ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.29/30
The End Future Work: explore the other metric such as l1 and l∞ how to find a good initial condition? apply more sophisticate transistor models explore the optimization model to other circuits such as Differential Logic, Complex Domino Logic and so on.
Thanks! ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.30/30
The End Future Work: explore the other metric such as l1 and l∞ how to find a good initial condition? apply more sophisticate transistor models explore the optimization model to other circuits such as Differential Logic, Complex Domino Logic and so on.
Thanks! ICCAD 2005 — 08 NOV 2005 — Noise Margin Analysis for Dynamic Logic Circuits – p.30/30
˜ Noll. A physically ori[Gemmeke+ 04] T. Gemmeke and T.G. ented model to quantify the dynamic noise margin. In Proceeding of the 30th European Conference on Solid-State Circuits, pages 467–470, September 2004. [Larsson+ 94] P. Larsson and C. Svensson. Noise in digital dynamic cmos circuits. IEEE Journal of Solid-State Circuits, 29(6):655–662, June 1994. [McMurchie+ 00] Larry McMurchie, Su Kio, et al. Output prediction logic: A high-performance CMOS design technique. In Proceedings of the 2000 International Conference on Computer Design, pages 247–254, 2000. [Shepard+ 00] K.L. Shepard and K. Chou. Cell characterization for noise stability. IEEE 2000 Custom Integrated Circuits Conference, pages 91–94, 2000. [Shepard+ 96] K.L. Shepard and V. Narayanan. Noise in deep submicron digital design. In Proceedings of the 1996 International Conference on Computer Aided Design, pages 406–411, 1996. [Zolotov+ 02] V. Zolotov, D. Blaauw, et al. Noise propagation and failure criteria for vlsi designs. In
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IEEE/ACM International Conference on Computer Aided Design, pages 587–594, November 2002.
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