Objectives: Equipments Required: Theory:
Electronics I lab
EE277
Objectives: -
To investigate the FET characteristics.
Equipments Required: 1. 2. 3. 4. 5. 6.
Junction Field Effect Transistor (JFET of type 3819). Resistors (100Ω , 1kΩ , 4.7kΩ , 100kΩ). DC-voltage source. Digital Multimeter (DMM). Project board. Coupling wires.
Theory: 1. What is a FET? FET is a voltage-controlled device, where the input voltage defines the operating conditions of the device. So we can use the FET as a voltage-controlled resistor. The FET building can be determined as in Figure 8-1 which shows an n-channel FET.
Figure 8-1 2. How does FET work? When the applied voltage between Gate and Source is zero (VGS = 0V), the FET is closed, so the current passes through it -between Source and Drain- (ID) will be at maximum value ( IDSS ), and as VGS increases, the n-channel will narrow as in Figure 8-2.
Figure 8-2 Page No (8-1)
Electronics I lab
EE277
So the current passes through D & S will decrease until it reaches zero when the n-channel be closed, then the value of VGS at which current ID equal to zero, is called pinch-off voltage (VP), see Figure 8-3.
Figure 8-3 So, we can define IDSS & VP as follows: - IDSS: it is the maximum drain current for a JFET, and can be defined by the conditions VGS = 0V, and VDS > V P . - VP: it is the minimum value of the voltage applied between Gate and Source that blocks drain current from passing through the JFET. 3. The characteristic curve of ID and VGS: As VGS becomes less negative than VP, the drain current increases until the current reaches maximum value IDSS as in the curve shown in Figure 8-4.
Figure 8-4 4. How to test the FET? We use the DMM to test the FET. When we connect the DMM as follows and read the DMM: Terminal connected Reading G–S Diode G–D Diode D–S Semiconductor Resistance Table 8-1 If the readings of DMM were as in the Table 8-1, the FET is valid, else; it is invalid. 5. How to find the FET parameters (VP & IDSS)? Connect the circuit shown in Figure 8-5.
Page No (8-2)
Electronics I lab
EE277
Figure 8-5 Then make VGS = 0V, and read the voltage drop across Ro to find the current passing through it (IDSS). Then, start to change VGS to get zero voltage drop across Ro, then the value of VGS is VP. 6. What are the relations between dc-values of JFET?
⎛ VDS ( sat ) ⎞ ⎟ I D = I DSS ⎜⎜ ⎟ V P ⎝ ⎠
2
V DS = V D − V S
= V D − V S + VG − VG = (VG − V S ) + (V D − VG ) = V P − VGS
∴ID
⎛ V − VGS = I DSS ⎜⎜ P VP ⎝
2
⎞ ⎟⎟ ⇒ ⎠
⎛ V I D = I DSS ⎜⎜ 1 − GS VP ⎝ 7. How to determine the JFET terminals? The JFET and its terminal are shown in Figure 8-6.
⎞ ⎟⎟ ⎠
Figure 8-6
Page No (8-3)
Electronics I lab
EE277
Experimental Procedure: •
•
• •
We connected the circuit shown in Figure 8-7.
Figure 8-7 The resistor used was measured and found that: R = 99.5Ω. We started to change the input voltage (VGS) while the oscilloscope is connected between the gate and the source until the DMM read zero voltage. The voltage across the 100Ωresistor was measured and found that: 0.359 VGS = 0 ⇒ V 100 Ω = 0.359V ⇒ I DSS = = 3.608 mA 99.5 We connected the DMM across the 100Ω-resistor terminals and started to change VGS until we get zero voltage drop across the resistor, then we measured the voltage difference between the gate and the source. It was VGS = VP = -2.873V. We took some readings for VGS between -2.873V and 0V and found the current passes through the 100Ω-resistor. The readings were as in Table 8-2. V VR VGS I D = R (mA) (V) (V) 99.5 VP = -2.873 0 0 -2.4 0.005 0.05 -2.1 0.005 0.05 -1.8 0.005 0.05 -1.5 0.006 0.06 -1.2 0.011 0.111 -0.9 0.033 0.332 -0.6 0.101 1.015 -0.3 0.215 2.161 0 0.359 IDSS = 3.608 Table 8-2 The curve of VGS and ID was drawn as in Figure 8-8.
Page No (8-4)
Electronics I lab
•
•
EE277
Figure 8-8 We connected the circuit shown in Figure 8-9.
Figure 8-9 The resistors connected in the circuit were measured and found that their values were as in Table 8-3. Resistor Labeled value Measured value RG 100 kΩ 99.25 kΩ RD 4.7 kΩ 4.735 kΩ RS 1 kΩ 1.003 kΩ Table 8-3 VS was measured and was: VS = 0.69V. V 3.28 = 0.693mA VR was 3.28V, so ID was: I D = R = R D 4.735 × 10 3 V D = 11.71V And: . V DS = 11.02V We replaced RS with a 10-kΩ potentiometer and measured ID & VGS at some valued of the potentiometer, the readings were as in Table 8-4.
Page No (8-5)
Electronics I lab
EE277 RS
VGS
0 1 kΩ 2 kΩ 3 kΩ 4 kΩ 5 kΩ 6 kΩ 7 kΩ 8 kΩ 9 kΩ 10 kΩ
0.14 V 0.71 V 0.87 V 0.91 V 0.95 V 0.99 V 1.01 V 1.04 V 1.06 V 1.07 V 1.09 V
VR
13.53 3.30 V 1.95 V 1.40 V 1.10 V 0.91 V 0.78 V 0.69 V 0.61 V 0.55 V 0.50 V Table 8-4 And, plot the curve of ID versus VGS as in Figure 8-10.
VR 4.735 k 2.857 mA 0.697 mA 0.412 mA 0.296 mA 0.232 mA 0.192 mA 0.165 mA 0.146 mA 0.129 mA 0.116 mA 0.106 mA
ID =
Figure 8-10
Conclusions: 1. The JFET can be use as a voltage controlled device, where we can get variable resistance by changing the input bias voltage. 2. JFET operates in the negative region of VGS. 3. As the biasing voltage becomes less negative, the resistance of the FET channel decreases, so the current passes through it increases, until it reaches the maximum value when the VGS value reaches 0V. 4. We can get low difference in current by increasing the Source resistance to some value, which shifts Q-point on the (ID versus VGS) curve to the left.
Page No (8-6)
Electronics I lab
EE277
Some errors occurred in the experiment which are related to: 1. Personal errors. 2. Measurements errors. 3. Thermal and time drift of the JFETs. 4. The tolerance in the measurements devices used in the experiment.
Page No (8-7)
EE277
Objectives: -
To investigate the FET characteristics.
Equipments Required: 1. 2. 3. 4. 5. 6.
Junction Field Effect Transistor (JFET of type 3819). Resistors (100Ω , 1kΩ , 4.7kΩ , 100kΩ). DC-voltage source. Digital Multimeter (DMM). Project board. Coupling wires.
Theory: 1. What is a FET? FET is a voltage-controlled device, where the input voltage defines the operating conditions of the device. So we can use the FET as a voltage-controlled resistor. The FET building can be determined as in Figure 8-1 which shows an n-channel FET.
Figure 8-1 2. How does FET work? When the applied voltage between Gate and Source is zero (VGS = 0V), the FET is closed, so the current passes through it -between Source and Drain- (ID) will be at maximum value ( IDSS ), and as VGS increases, the n-channel will narrow as in Figure 8-2.
Figure 8-2 Page No (8-1)
Electronics I lab
EE277
So the current passes through D & S will decrease until it reaches zero when the n-channel be closed, then the value of VGS at which current ID equal to zero, is called pinch-off voltage (VP), see Figure 8-3.
Figure 8-3 So, we can define IDSS & VP as follows: - IDSS: it is the maximum drain current for a JFET, and can be defined by the conditions VGS = 0V, and VDS > V P . - VP: it is the minimum value of the voltage applied between Gate and Source that blocks drain current from passing through the JFET. 3. The characteristic curve of ID and VGS: As VGS becomes less negative than VP, the drain current increases until the current reaches maximum value IDSS as in the curve shown in Figure 8-4.
Figure 8-4 4. How to test the FET? We use the DMM to test the FET. When we connect the DMM as follows and read the DMM: Terminal connected Reading G–S Diode G–D Diode D–S Semiconductor Resistance Table 8-1 If the readings of DMM were as in the Table 8-1, the FET is valid, else; it is invalid. 5. How to find the FET parameters (VP & IDSS)? Connect the circuit shown in Figure 8-5.
Page No (8-2)
Electronics I lab
EE277
Figure 8-5 Then make VGS = 0V, and read the voltage drop across Ro to find the current passing through it (IDSS). Then, start to change VGS to get zero voltage drop across Ro, then the value of VGS is VP. 6. What are the relations between dc-values of JFET?
⎛ VDS ( sat ) ⎞ ⎟ I D = I DSS ⎜⎜ ⎟ V P ⎝ ⎠
2
V DS = V D − V S
= V D − V S + VG − VG = (VG − V S ) + (V D − VG ) = V P − VGS
∴ID
⎛ V − VGS = I DSS ⎜⎜ P VP ⎝
2
⎞ ⎟⎟ ⇒ ⎠
⎛ V I D = I DSS ⎜⎜ 1 − GS VP ⎝ 7. How to determine the JFET terminals? The JFET and its terminal are shown in Figure 8-6.
⎞ ⎟⎟ ⎠
Figure 8-6
Page No (8-3)
Electronics I lab
EE277
Experimental Procedure: •
•
• •
We connected the circuit shown in Figure 8-7.
Figure 8-7 The resistor used was measured and found that: R = 99.5Ω. We started to change the input voltage (VGS) while the oscilloscope is connected between the gate and the source until the DMM read zero voltage. The voltage across the 100Ωresistor was measured and found that: 0.359 VGS = 0 ⇒ V 100 Ω = 0.359V ⇒ I DSS = = 3.608 mA 99.5 We connected the DMM across the 100Ω-resistor terminals and started to change VGS until we get zero voltage drop across the resistor, then we measured the voltage difference between the gate and the source. It was VGS = VP = -2.873V. We took some readings for VGS between -2.873V and 0V and found the current passes through the 100Ω-resistor. The readings were as in Table 8-2. V VR VGS I D = R (mA) (V) (V) 99.5 VP = -2.873 0 0 -2.4 0.005 0.05 -2.1 0.005 0.05 -1.8 0.005 0.05 -1.5 0.006 0.06 -1.2 0.011 0.111 -0.9 0.033 0.332 -0.6 0.101 1.015 -0.3 0.215 2.161 0 0.359 IDSS = 3.608 Table 8-2 The curve of VGS and ID was drawn as in Figure 8-8.
Page No (8-4)
Electronics I lab
•
•
EE277
Figure 8-8 We connected the circuit shown in Figure 8-9.
Figure 8-9 The resistors connected in the circuit were measured and found that their values were as in Table 8-3. Resistor Labeled value Measured value RG 100 kΩ 99.25 kΩ RD 4.7 kΩ 4.735 kΩ RS 1 kΩ 1.003 kΩ Table 8-3 VS was measured and was: VS = 0.69V. V 3.28 = 0.693mA VR was 3.28V, so ID was: I D = R = R D 4.735 × 10 3 V D = 11.71V And: . V DS = 11.02V We replaced RS with a 10-kΩ potentiometer and measured ID & VGS at some valued of the potentiometer, the readings were as in Table 8-4.
Page No (8-5)
Electronics I lab
EE277 RS
VGS
0 1 kΩ 2 kΩ 3 kΩ 4 kΩ 5 kΩ 6 kΩ 7 kΩ 8 kΩ 9 kΩ 10 kΩ
0.14 V 0.71 V 0.87 V 0.91 V 0.95 V 0.99 V 1.01 V 1.04 V 1.06 V 1.07 V 1.09 V
VR
13.53 3.30 V 1.95 V 1.40 V 1.10 V 0.91 V 0.78 V 0.69 V 0.61 V 0.55 V 0.50 V Table 8-4 And, plot the curve of ID versus VGS as in Figure 8-10.
VR 4.735 k 2.857 mA 0.697 mA 0.412 mA 0.296 mA 0.232 mA 0.192 mA 0.165 mA 0.146 mA 0.129 mA 0.116 mA 0.106 mA
ID =
Figure 8-10
Conclusions: 1. The JFET can be use as a voltage controlled device, where we can get variable resistance by changing the input bias voltage. 2. JFET operates in the negative region of VGS. 3. As the biasing voltage becomes less negative, the resistance of the FET channel decreases, so the current passes through it increases, until it reaches the maximum value when the VGS value reaches 0V. 4. We can get low difference in current by increasing the Source resistance to some value, which shifts Q-point on the (ID versus VGS) curve to the left.
Page No (8-6)
Electronics I lab
EE277
Some errors occurred in the experiment which are related to: 1. Personal errors. 2. Measurements errors. 3. Thermal and time drift of the JFETs. 4. The tolerance in the measurements devices used in the experiment.
Page No (8-7)
