On the Electrostatic Discharge Robustness of ... - Semantic Scholar
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
On the Electrostatic Discharge Robustness of Graphene Hong Li, Member, IEEE, Christian C. Russ, Wei Liu, Member, IEEE, David Johnsson, Harald Gossner, Senior Member, IEEE, and Kaustav Banerjee, Fellow, IEEE Abstract— A comprehensive study of electrostatic discharge (ESD) characterization of atomically thin graphene is reported. In a material comprising only a few atomic layers, the thermally destructive second breakdown transmission line pulsing (TLP) current (It2) reaches a remarkable 4 mA/µm for 100-ns TLP and ∼8 mA/µm for 10-ns TLP or an equivalent current density of ∼3 × 108 and 4.6 × 108 A/cm2 , respectively. For ∼5-nm thick (∼15 layers) graphene film, It2 reaches 7.4 mA/µm for 100-ns pulse. The fact that failure occurs within the graphene and not at the contacts indicates that intrinsic breakdown properties of this new material can be appropriately characterized using short-pulse stressing. Moreover, unique gate biasing effects are observed that can be exploited for novel applications including robust ESD protection designs for advanced semiconductor products. This demonstration of graphene’s outstanding robustness against high-current/ESD pulses also establishes its unique potential as transparent electrodes in a variety of applications.
TABLE I P ROPERTIES OF G RAPHENE R ELEVANT TO E LECTRONICS AND I TS
C OMPARISON W ITH O THER M ATERIALS
Index Terms— Current density, current saturation, electrostatic discharge (ESD), graphene, It2, transmission line pulsing (TLP).
I. I NTRODUCTION
G
RAPHENE, a single atomic layer of carbon atoms packed into a 2-D honeycomb lattice structure, has extraordinary physical properties that make it attractive for a variety of applications in nanoelectronics, optoelectronics, spintronics, as well as mechanical and biological fields [1]–[4]. Particularly, in the nanoelectronics area, due to excellent properties of graphene such as high intrinsic mobility and high electrical/thermal conductivities, a lot of interest has been aroused in the applications of nanoscale logic transistors, RF devices, interconnects and passives, energy storage, and conversion devices (such as supercapacitors, thermoelectrics, and photovoltaics [5]), and various type of sensors. In addition, graphene also shows promising applications in consumer Manuscript received May 29, 2013; revised March 25, 2014; accepted March 31, 2014. Date of current version May 16, 2014. This work was supported in part by Intel Corporation and in part by the ESD Association through a Research Award in 2011. The review of this paper was arranged by Editor J. Knoch. H. Li was with the Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106 USA. He is now with the Emerging Memory Group, Micron Technology, Boise, ID 83707 USA (e-mail: [email protected]). C. C. Russ, D. Johnsson, and H. Gossner are with Intel Mobile Communications, Neubiberg 85579, Germany (e-mail: [email protected]; [email protected]; [email protected]). W. Liu and K. Banerjee are with the Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA 93106 USA (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2014.2315235
electronics, such as transparent electrodes and touchscreens, as demonstrated in [6]. A summary of the key properties of graphene relevant to electronic applications is provided in Table I [3], [4]. As reliability has always been a big concern for electronics, there has been a number of studies on the dc breakdown characteristics of carbon-based nanomaterials, demonstrating that both carbon nanotubes (CNTs) [7], [8] and graphene nanoribbons (GNRs) [9], [10] exhibit current carrying capacity larger than 108 A/cm2 . However, no experimental evidence has ever been reported on the electrostatic discharge (ESD) breakdown characterization of these carbon nanomaterials. In this paper, we investigate the reliability characterization of atomically thin graphene under ESD conditions. The preliminary work has been presented in [11]. The results of this paper not only provide new insights into designing ESD protection devices and circuits using this nanotechnology, but also open up new possibilities of characterizing graphene material. II. ESD C HARACTERIZATION The graphene sheets used in this paper consist of a few (mostly 198 , we can estimate that in our work the contact resistance contribution to the total resistance would be mostly less than 20%. Therefore, even though our measurements did not particularly exclude contact resistance, what we have measured reflects the ESD characteristics of graphene itself, and not those of the contacts.1 Fig. 7 shows the time-domain waveform of TLP voltage and current of a bilayer graphene device. It can be observed that the device reacts essentially instantaneously with no delay in the current. Note that the initial spikes at the edge of pulses are not device characteristics, but rather a measurement setup artifact due to an inductive parasitic in the ground path. We also noted that in all the voltage waveforms, the voltage is slightly increasing at the beginning of the pulse (from 0 to approximately 10 ns, as indicated by green dotted lines in Fig. 7) before reaching a relatively constant value. Since this 1 The contact resistance extracted here is greatly simplified as one lumped value. As true for all contacts from 2-D to 3-D material, graphene-metal contact resistance can be fairly complicated. More details can be found in [16] and [17].
short time period (≈10 ns) agrees with the thermal time constant estimation, the phase of slight voltage increase at the beginning of the pulse can be interpreted as the time for the device to reach thermal equilibrium. To characterize the stability and the repeatability of the ESD properties, we also performed multiple TLP sweeps and multizapping on one bilayer device. We first estimate the It2 to be around 16 mA from Fig. 4, then apply the pulsing at about 90% of It2 so that the device will not be destroyed during the multizapping test. Fig. 8 shows the multizapping results. Two standard TLP measurements were run at first and yielded almost identical TLP I –V characteristics. Subsequently, for a given TLP voltage (7 V) multizapping TLP pulse was applied to further test the stability. It is shown that even after 1200 pulses, both TLP current and its corresponding dc spot [after each TLP pulse apply dc = 0.1 V and measure the current (one spot value) at this voltage to monitor any device degradation] did not exhibit significant changes, indicating an excellent stability. Just to complete the stress sequence, the pulse amplitude was increased thereafter to prove that the device indeed fails at the estimated value (see post-It2 point in Fig. 8). Besides 100-ns TLP pulses, different TLP pulse widths have also been employed for examining the robustness of graphene devices. Fig. 9 shows the 10 and 1000-ns TLP I –V characteristics of graphene devices. Due to lower energy associated with the 10-ns pulse, the TLP breakdown current is significantly higher than that of the 100-ns pulse case, reaching 7.9 mA/μm. For the 1000-ns pulse, the TLP breakdown currents are slightly lower than those of 100 ns cases. Table III summarizes the breakdown currents for different pulse widths. Moreover, to eliminate the device-to-device variations, we run TLP measurements by applying different pulse widths on the same device without destroying it, as shown in Fig. 10. A series of different pulses with increasing duration (100–200–500–1000-ns nondestructive first sweeps) are applied and is followed by a second destructive sweep at 1000 ns. Despite minor fluctuations between the individual TLP sweeps, the characteristics are almost identical for the different pulse widths indicating that there is little impact from self-heating at least up to the
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
Fig. 10. TLP I –V responses with different pulse widths. The device has two graphene layers with width = 2.1 μm and length = 2.9 μm.
Fig. 9. ESD TLP characteristics of graphene device with pulse widths of (a) 10 and (b) 1000 ns. For 10 ns, the It2 per width is measured to be 7.9 mA/μm. For 1000 ns, the It2 per width are 1.2, 1.4, and 3.7 mA/μm for two, three, and four graphene layers, respectively. TABLE III It2 FOR D IFFERENT TLP P ULSE W IDTHS (mA/μm)
Fig. 11. (a) Drain current of graphene device d (in Table II) as a function of back gate voltage with drain voltage of 0.1 V for three sweeps. (b) Conductance of the graphene device d as a function of back gate voltage. For a given gate voltage, the conductance is measured by averaging the current due to applied drain voltages from 0 to 0.5 V. The device shows clear ambipolar behavior and the neutral point is at Vnp = 6 V, indicating a slightly p-type characteristic.
TLP technique a very unique electrothermal characterization tool for graphene. III. I MPACT OF G ATE C ONTROL
currents at which the nondestructive testing was performed (≈1.3–1.6 mA). This is in line with the earlier observations that thermal behavior is dominated by the substrate for graphene samples with small number of layers. Furthermore, this confirms that the compilation of data in Table III with different pulse widths on individually and destructively tested samples is a valid methodology for quantifying the robustness of graphene under high-current/ESD pulses. It should be noted that short-pulse stress conditions would usually provide a unique approach for studying thermal damage if the pulsewidth is much smaller than the thermal time constant of the device structure [18], [19]. The above analysis therefore demonstrates that with the proper choice of the TLP pulsewidth and/or the topology of the structures (including the thickness and thermal properties of the underlying dielectric), one can study the entire range of thermal stress conditions, from steady-state (dc-like) behavior to nonsteadystate situations, as discussed in [18]. This renders the
In Section II, samples were characterized without tuning the back gate bias. In this section, a new type of test-device with gate biasing is characterized under same stress conditions. For this particular device type, the substrate consists of 100-nm SiO2 on top of highly doped silicon, and the contact pad consists of 70-nm gold on top of 50-nm titanium. The highly doped silicon substrate can be biased and acts as a back gate. Fig. 11 shows the dc characteristics of one device under small drain bias (low electric field condition). The graphene in this device consists of three layers as characterized by Raman spectroscopy and has width and length of 6 μm and 2.4 μm, respectively. The device shows clear ambipolar behavior. The field-effect mobility (for low field, Vds = 0.1 V) for this device is calculated to be about 1600 cm2 /V-s using μ=
L Ids · W · Cox · Vds Vgs
(2)
where Cox is the back gate oxide capacitance per unit area (ignoring quantum capacitance due to large width). This number is in agreement with reported values in the literature for bilayer graphene [20]. Although there is a slight hysteresis shown in Fig. 11(a), the neutral point voltage is
LI et al.: ON THE ESD ROBUSTNESS OF GRAPHENE
Fig. 12. (a) TLP current as a function of gate voltage for device d. (b) DC conductance at different gate voltages according to Fig. 11(b).
Fig. 13. (a) Performance degradation after repeated TLP measurements under the gate voltage Vg = 40 V for device d. (b) Illustration of current degradation by neutral point shifting. G denotes the DC conductance.
almost unchanged at Vnp = 6 V, which indicates a p-doped device on SiO2 substrate. At neutral point, the resistance is maximum, and as the gate voltage increases (or decreases) away from the neutral point, the resistance decreases because of the increment in charge carrier densities (either electrons or holes). In graphene, the charge densities under gate bias can be approximated by [21] (3) n = n 20 + [Cox (Vg − Vnp )/q]2 where n 0 is the minimum sheet carrier concentration of graphene as determined by thermal excitation, disorder, and substrate interface, q is the elementary charge, and Vg and Vnp are the applied gate bias and neutral point voltage, respectively. This equation explains the fact that the carrier density (or the conductance) is minimum when Vg = Vnp , and increases as Vg moves away from Vnp . In order to perform multiple TLP measurements to observe any impact of the gate voltage, the maximum TLP voltage is chosen without damaging the device. Fig. 12(a) shows the TLP I –V curves for different gate biases. It can be observed that with increasing gate bias, the TLP current slightly decreases at first (from Vg = 0 to 10 V) then increases (from 10 to 30 V). This is explained in Fig. 12(b), where the channel conductance varies the same way as gate bias changes, indicating that the TLP current has direct relationship with the conductance. By increasing the difference between applied gate voltage and the neutral point voltage, TLP current increases due to larger carrier density, as can be explained by (3). Repeated TLP measurements are then performed at Vg = 40 V, as shown in Fig. 13(a). Interestingly, the TLP
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Fig. 14. (a) TLP measurements for negative gate bias and breakdown test under 100-ns TLP for device d. Note that two lines with Vg = −40 V are overlapping. (b) Illustration of neutral point shifting, which causes the current at Vg = −10 V to be larger than that of Vg = 40 V.
current decreases as the measurement repeats, and the degradation is most significant during the second measurement. We attribute this degradation to the effect of interface and oxide traps. For Vg = 40 V, electrons are the majority carriers, and during the first measurement the traps are filled by electrons. These electron-filled traps act as a screening layer that weakens the effect of back gate control. Effectively, one can describe this in terms of the more positive shift in neutral point, as shown in Fig. 13(b). As the neutral point shifts toward more positive, for the same Vg , the effective carrier density is smaller and therefore, current becomes smaller. This neutral point shifting will be larger for larger gate bias, as the traps in the oxide have larger probability to be activated due to larger oxide electric field. This neutral point shifting has been observed in many graphene devices, particularly for large gate bias [22]. For negative gate bias, the effect of gate control is shown in Fig. 14(a). As the gate voltage moves away from Vnp , the current increases. From Fig. 12(b), one would expect that the current at Vg = −10 V would be lower than that of Vg = 40 V, however, Fig. 14(a) does not show such a trend. This is because under a positive gate bias, the traps were filled with electrons. When a negative gate bias is applied, the majority carriers in the channel now become holes. The previously electron-filled traps also introduce positive image charges in the channel to increase carrier density. Similar to Fig. 13(b), we can also explain this using the neutral point shifting, as shown in Fig. 14(b). Because the neutral point shifts toward more positive values after third measurement of Vg = 40 V, it is now possible to have higher current at Vg = −10 V than that at Vg = 40 V, which is not possible during the initial measurement. From the above discussion, we can conclude that due to ambipolar nature of graphene and the fact that the carrier density of graphene (and its Fermi level) can be easily modulated by the gate electrostatics and trap states, graphene shows a unique gate biasing control effect, which not only depends on the bias amplitude, but also depends on the sign and sequence of gate biasing, thereby exhibiting unique memory effects. IV. C URRENT S ATURATION One interesting behavior observed from both Figs. 13 and 14 is that the I –V characteristics exhibit a bending at high voltages. Particularly, for large negative gate bias, the I –V curves
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Fig. 15. TLP current as a function of gate voltage for a bilayer graphene device with width and length of 3.3 and 2.5 μm, respectively. The red solid curve at the upper right corner represents a constant power.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
Fig. 17. densities.
Fitted mobility and saturation velocity as a function of carrier
saturation in the high field regime, which can also be regarded as velocity saturation, because the energy of surface optical phonon (55 meV) is much lower than that of optical phonon energy of graphene (150 meV). Using the carrier density formula in (3), the carrier velocity can be extracted according to J = qnv. From the curves at Vg = 0 V and Vg = 10 V, the minimum carrier density n 0 is first determined to be 4.5 × 1012 cm−2 , which is close to the existing reported value for trilayer graphene [24]. The extracted velocity is shown in Fig. 16. It can be observed that the velocity decreases as carrier density (related to gate bias) increases. Velocity saturation behavior is particularly obvious in Fig. 16(b). We can now approximate the carrier velocity by a simple velocity saturation model v=
Fig. 16. Extracted carrier velocities of device d for (a) positive and (b) negative gate biases. The fitted velocity curves are also shown as solid lines in (b).
display an obvious current saturation behavior. This current saturation behavior could be due to several effects. One factor could be the temperature rise due to Joule heating effects. However, we notice that for the same amount of power, not all the curves show current saturation. Fig. 15 best describes the situation, where for the same given power (red solid line), only curves with negative gate bias conditions show obvious current saturation behavior, whereas those under positive gate bias conditions show almost linear relationship. This indicates that there must be another more important factor that causes current saturation. An alternate root cause for current saturation could be an enhanced electron-phonon scattering at high electrical fields [21], [23]. For the structure of graphene on oxide, electron scattering due to surface optical phonons dominates the current
μE 1 + μE/vsat
(4)
where E is the electrical field in the channel along the graphene layer, μ is carrier mobility, and vsat is the saturation velocity of the carrier. The fitted mobility and saturation velocity is shown in Fig. 17, where both parameters decrease with increasing carrier density, in agreement with [21] and [23]–[25]. This is because a higher carrier density is correlated with higher Fermi level of the graphene, so that the probability of electrons to reach the energy threshold for surface optical phonon emission will be increased (i.e., enhanced scattering), thereby a reduction in mobility and saturation velocity occurs. At the same time, the enhanced scattering with surface optical phonons also leads to enhanced Joule heating and raises the local temperature. It should be noted that, the current saturation in graphene under high electric field is still not completely understood, although so far velocity saturation mechanism seems to be able to provide reasonably good explanation. The fitted curves are shown in Fig. 16(b) to compare them with the extracted data. It can be observed that for higher electrical field, the fitted curves overestimate the velocity. This overestimation may be due to the fact that the Joule heating and temperature effects on velocity are not considered in the fitting model yet. In the future, a more accurate model needs to be developed by taking into account Joule heating and temperature rise in a self-consistent manner.
LI et al.: ON THE ESD ROBUSTNESS OF GRAPHENE
V. C ONCLUSION This paper, for the first time, characterized graphene under high-current pulse/ESD conditions. The high TLP current carrying capability demonstrates the excellent robustness of graphene under ESD stress, which is potentially important for very advanced semiconductor and packaging technologies, as well as for various transparent conductor applications. Moreover, the fact that failure occurs in the graphene and not at the contacts indicates that intrinsic properties of this new material can be appropriately characterized using short-pulse stressing. Novel physical behavior has been revealed when graphene is investigated under high TLP current and high back gate voltage conditions. The existences of interface and oxide traps give rise to a bidirectional shifting of the neutral point under different gate biases. A current saturation behavior is observed and explained via velocity saturation at high electric filed. The application of short duration and high current pulses to graphene is, thereby proven to deliver unexpected and unique insights into this material. These unique features combined with graphene’s inherent flexibility, strength, and impermeability to moisture can also be potentially exploited for developing novel applications including robust ESD protection strategies in advanced semiconductor products as well as for touchscreen applications in various domains including mobile communication, automotive and aerospace, photon and thermal management, and sensors. ACKNOWLEDGMENT K.B. would like to thank the Alexander von Humboldt Foundation, Germany, for the Friedrich Wilhelm Bessel Research Award, which immensely facilitated this collaboration. R EFERENCES [1] A. K. Geim and K. S. Novoselov, “The rise of graphene,” Nature Mater., vol. 6, no. 3, pp. 183–191, 2007. [2] F. Schwierz, “Graphene transistors,” Nature Nanotechnol., vol. 5, pp. 487–496, May 2010. [3] H. Li, C. Xu, N. Srivastava, and K. Banerjee, “Carbon nanomaterials for next-generation interconnects and passives: Physics, status and prospects,” IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 1799–1821, Sep. 2009. [4] K. Banerjee et al., “Prospects of carbon nanomaterials for nextgeneration green electronics,” in Proc. 10th IEEE NANO, Nanotechnol. Conf., Aug. 2010, pp. 56–61. [5] Y. Khatami, W. Liu, J. Kang, and K. Banerjee, “Prospects of graphene electrodes in photovoltaics,” Proc. SPIE, vol. 8824, pp. 88240T-1–88240T-6, Sep. 2013. [6] S. Bae et al., “Roll-to-roll production of 30-inch graphene films for transparent electrodes,” Nature Nanotechnol., vol. 5, no. 8, pp. 574–578, 2010. [7] Z. Yao, C. L. Kane, and C. Dekker, “High-field electrical transport in single-wall carbon nanotubes,” Phys. Rev. Lett., vol. 84, no. 13, pp. 2941–2944, 2000. [8] B. Q. Wei, R. Vajtai, and P. M. Ajayan, “Reliability and current carrying capacity of carbon nanotubes,” Appl. Phys. Lett., vol. 79, no. 8, pp. 1172–1174, 2001. [9] R. Murali, Y. Yang, K. Brenner, T. Beck, and J. D. Meindl, “Breakdown current density of graphene nanoribbons,” Appl. Phys. Lett., vol. 94, no. 24, pp. 3114–3117, 2009. [10] A. D. Liao et al., “Thermally limited current carrying ability of graphene nanoribbons,” Phys. Rev. Lett., vol. 106, no. 25, p. 256801, 2011. [11] H. Li, C. C. Russ, W. Liu, D. Johnsson, H. Gossner, and K. Banerjee, “ESD characterization of atomically-thin graphene,” in Proc. 34th EOS/ESD Symp., Sep. 2012, pp. 1–8.
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[12] W. Liu, H. Li, C. Xu, Y. Khatami, and K. Banerjee, “Synthesis of highquality monolayer and bilayer graphene on copper using chemical vapor deposition,” Carbon, vol. 49, no. 13, pp. 4122–4130, Nov. 2011. [13] W. Liu, S. Krämer, D. Sarkar, H. Li, P. M. Ajayan, and K. Banerjee, “Controllable and rapid synthesis of high-quality and large-area Bernal stacked bilayer graphene using chemical vapor deposition,” Chem. Mater., vol. 26, no. 2, pp. 907–915, 2014. [14] W. Liu, J. J. Liou, A. Chung, Y.-H. Jeong, W.-C. Chen, and H.-C. Lin, “Electrostatic discharge robustness of Si nanowire field-effect transistors,” IEEE Trans. Electron Devices, vol. 30, no. 9, pp. 969–971, Sep. 2009. [15] Z. Chen, W. Jang, W. Bao, C. N. Lau, and C. Dames, “Thermal contact resistance between graphene and silicon dioxide,” Appl. Phys. Lett., vol. 95, no. 16, pp. 161910-1–161910-3, 2009. [16] Y. Khatami, H. Li, C. Xu, and K. Banerjee, “Metal-to-multilayergraphene contact—Part I: Contact resistance modeling,” IEEE Trans. Electron Devices, vol. 59, no. 9, pp. 2444–2452, Sep. 2012. [17] Y. Khatami, H. Li, C. Xu, and K. Banerjee, “Metal-to-multilayergraphene contact—Part II: Analysis of contact resistance,” IEEE Trans. Electron Devices, vol. 59, no. 9, pp. 2453–2460, Sep. 2012. [18] K. Banerjee, A. Amerasekera, N. Cheung, and C. Hu, “High-current failure model for VLSI interconnects under short-pulse stress conditions,” IEEE Trans. Electron Devices, vol. 18, no. 9, pp. 405–407, Sep. 1997. [19] K. Banerjee, D. Y. Kim, A. Amerasekera, C. Hu, S. S. Wong, and K. E. Goodson, “Microanalysis of VLSI interconnect failure modes under short-pulse stress conditions,” in Proc. 38th IEEE IPRS, Apr. 2000, pp. 283–288. [20] K. Nagashio, T. Nishimura, K. Kita, and A. Toriumi, “Mobility variations in mono- and multi-layer graphene films,” Appl. Phys. Exp., vol. 2, pp. 025003-1–025003-4, Dec. 2009. [21] I. Meric, M. Y. Han, A. F. Young, B. Ozyilmaz, P. Kim, and K. L. Shepard, “Current saturation in zero-bandgap, top-gated graphene field-effect transistors,” Nanotechnol., vol. 3, no. 11, pp. 654–659, 2008. [22] H. Wang, Y. Wu, C. Cong, J. Shang, and T. Yu, “Hysteresis of electronic transport in graphene transistors,” ACS Nano, vol. 4, no. 12, pp. 7221–7228, 2010. [23] A. M. Dasilva, K. Zou, J. K. Jain, and J. Zhu, “Mechanism for current saturation and energy dissipation in graphene transistors,” Phys. Rev. Lett., vol. 104, no. 23, p. 236601, 2010. [24] W. Zhu, V. Perebeinos, M. Freitag, and P. Avouris, “Carrier scattering, mobilities, and electrostatic potential in monolayer, bilayer, and trilayer graphene,” Phys. Rev. B, vol. 80, no. 23, p. 235402, 2009. [25] V. E. Dorgan, M.-H. Bae, and E. Pop, “Mobility and saturation velocity in graphene on SiO2 ,” Appl. Phys. Lett., vol. 97, no. 8, pp. 082112-1–082112-3, 2010.
Hong Li (S’07–M’12) received the Ph.D. degree in electrical and computer engineering from the University of California, Santa Barbara, CA, USA, in 2012. He is currently an Emerging Memory Engineer at Micron Technology Inc., Boise, ID, USA. He has authored and co-authored more than 30 publications.
Christian C. Russ received the M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich, Munich, Germany, in 1991 and 1999, respectively. He is currently a Principal Engineer at Intel Mobile Communications, Munich, where he is involved in ESD issues in CMOS technologies (28 nm, 14 nm, and below).
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Wei Liu (M’10) received the Ph.D. degree in chemistry from the Institute of Chemistry, Chinese Academy of Sciences, Beijing, China, in 2008. He is currently a Post-Doctoral Scholar with the Electrical and Computer Engineering Department, University of California, Santa Barbara, CA, USA.
Harald Gossner (M’06–SM’11) received the B.S. (Dipl.Phys.) degree in physics from the LudwigMaximilians-Universität München, München, Germany, and the Ph.D. degree in electrical engineering from Universität der Bundeswehr, München, in 1990 and 1995, respectively. He is currently a Senior Principal Engineer at Intel Mobile Communications, München, where he is involved in the development of robust mobile systems.
David Johnsson received the M.Sc. degree in electrical engineering from the Royal Institute of Technology, Stockholm, Sweden, in 2006. He is currently a member of the ESD team at Intel Mobile Communications, Munich, Germany. He is also a Co-Founder of High Power Pulse Instruments, Munich, where he develops software and hardware for TLP systems.
Kaustav Banerjee (S’92–M’99–SM’03–F’12) received the Ph.D. degree in electrical engineering and computer science from the University of California, Berkeley, CA, USA, in 1999. He is currently a Professor of Electrical and Computer Engineering with the University of California, Santa Barbara, CA, USA.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
On the Electrostatic Discharge Robustness of Graphene Hong Li, Member, IEEE, Christian C. Russ, Wei Liu, Member, IEEE, David Johnsson, Harald Gossner, Senior Member, IEEE, and Kaustav Banerjee, Fellow, IEEE Abstract— A comprehensive study of electrostatic discharge (ESD) characterization of atomically thin graphene is reported. In a material comprising only a few atomic layers, the thermally destructive second breakdown transmission line pulsing (TLP) current (It2) reaches a remarkable 4 mA/µm for 100-ns TLP and ∼8 mA/µm for 10-ns TLP or an equivalent current density of ∼3 × 108 and 4.6 × 108 A/cm2 , respectively. For ∼5-nm thick (∼15 layers) graphene film, It2 reaches 7.4 mA/µm for 100-ns pulse. The fact that failure occurs within the graphene and not at the contacts indicates that intrinsic breakdown properties of this new material can be appropriately characterized using short-pulse stressing. Moreover, unique gate biasing effects are observed that can be exploited for novel applications including robust ESD protection designs for advanced semiconductor products. This demonstration of graphene’s outstanding robustness against high-current/ESD pulses also establishes its unique potential as transparent electrodes in a variety of applications.
TABLE I P ROPERTIES OF G RAPHENE R ELEVANT TO E LECTRONICS AND I TS
C OMPARISON W ITH O THER M ATERIALS
Index Terms— Current density, current saturation, electrostatic discharge (ESD), graphene, It2, transmission line pulsing (TLP).
I. I NTRODUCTION
G
RAPHENE, a single atomic layer of carbon atoms packed into a 2-D honeycomb lattice structure, has extraordinary physical properties that make it attractive for a variety of applications in nanoelectronics, optoelectronics, spintronics, as well as mechanical and biological fields [1]–[4]. Particularly, in the nanoelectronics area, due to excellent properties of graphene such as high intrinsic mobility and high electrical/thermal conductivities, a lot of interest has been aroused in the applications of nanoscale logic transistors, RF devices, interconnects and passives, energy storage, and conversion devices (such as supercapacitors, thermoelectrics, and photovoltaics [5]), and various type of sensors. In addition, graphene also shows promising applications in consumer Manuscript received May 29, 2013; revised March 25, 2014; accepted March 31, 2014. Date of current version May 16, 2014. This work was supported in part by Intel Corporation and in part by the ESD Association through a Research Award in 2011. The review of this paper was arranged by Editor J. Knoch. H. Li was with the Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106 USA. He is now with the Emerging Memory Group, Micron Technology, Boise, ID 83707 USA (e-mail: [email protected]). C. C. Russ, D. Johnsson, and H. Gossner are with Intel Mobile Communications, Neubiberg 85579, Germany (e-mail: [email protected]; [email protected]; [email protected]). W. Liu and K. Banerjee are with the Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA 93106 USA (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2014.2315235
electronics, such as transparent electrodes and touchscreens, as demonstrated in [6]. A summary of the key properties of graphene relevant to electronic applications is provided in Table I [3], [4]. As reliability has always been a big concern for electronics, there has been a number of studies on the dc breakdown characteristics of carbon-based nanomaterials, demonstrating that both carbon nanotubes (CNTs) [7], [8] and graphene nanoribbons (GNRs) [9], [10] exhibit current carrying capacity larger than 108 A/cm2 . However, no experimental evidence has ever been reported on the electrostatic discharge (ESD) breakdown characterization of these carbon nanomaterials. In this paper, we investigate the reliability characterization of atomically thin graphene under ESD conditions. The preliminary work has been presented in [11]. The results of this paper not only provide new insights into designing ESD protection devices and circuits using this nanotechnology, but also open up new possibilities of characterizing graphene material. II. ESD C HARACTERIZATION The graphene sheets used in this paper consist of a few (mostly 198 , we can estimate that in our work the contact resistance contribution to the total resistance would be mostly less than 20%. Therefore, even though our measurements did not particularly exclude contact resistance, what we have measured reflects the ESD characteristics of graphene itself, and not those of the contacts.1 Fig. 7 shows the time-domain waveform of TLP voltage and current of a bilayer graphene device. It can be observed that the device reacts essentially instantaneously with no delay in the current. Note that the initial spikes at the edge of pulses are not device characteristics, but rather a measurement setup artifact due to an inductive parasitic in the ground path. We also noted that in all the voltage waveforms, the voltage is slightly increasing at the beginning of the pulse (from 0 to approximately 10 ns, as indicated by green dotted lines in Fig. 7) before reaching a relatively constant value. Since this 1 The contact resistance extracted here is greatly simplified as one lumped value. As true for all contacts from 2-D to 3-D material, graphene-metal contact resistance can be fairly complicated. More details can be found in [16] and [17].
short time period (≈10 ns) agrees with the thermal time constant estimation, the phase of slight voltage increase at the beginning of the pulse can be interpreted as the time for the device to reach thermal equilibrium. To characterize the stability and the repeatability of the ESD properties, we also performed multiple TLP sweeps and multizapping on one bilayer device. We first estimate the It2 to be around 16 mA from Fig. 4, then apply the pulsing at about 90% of It2 so that the device will not be destroyed during the multizapping test. Fig. 8 shows the multizapping results. Two standard TLP measurements were run at first and yielded almost identical TLP I –V characteristics. Subsequently, for a given TLP voltage (7 V) multizapping TLP pulse was applied to further test the stability. It is shown that even after 1200 pulses, both TLP current and its corresponding dc spot [after each TLP pulse apply dc = 0.1 V and measure the current (one spot value) at this voltage to monitor any device degradation] did not exhibit significant changes, indicating an excellent stability. Just to complete the stress sequence, the pulse amplitude was increased thereafter to prove that the device indeed fails at the estimated value (see post-It2 point in Fig. 8). Besides 100-ns TLP pulses, different TLP pulse widths have also been employed for examining the robustness of graphene devices. Fig. 9 shows the 10 and 1000-ns TLP I –V characteristics of graphene devices. Due to lower energy associated with the 10-ns pulse, the TLP breakdown current is significantly higher than that of the 100-ns pulse case, reaching 7.9 mA/μm. For the 1000-ns pulse, the TLP breakdown currents are slightly lower than those of 100 ns cases. Table III summarizes the breakdown currents for different pulse widths. Moreover, to eliminate the device-to-device variations, we run TLP measurements by applying different pulse widths on the same device without destroying it, as shown in Fig. 10. A series of different pulses with increasing duration (100–200–500–1000-ns nondestructive first sweeps) are applied and is followed by a second destructive sweep at 1000 ns. Despite minor fluctuations between the individual TLP sweeps, the characteristics are almost identical for the different pulse widths indicating that there is little impact from self-heating at least up to the
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Fig. 10. TLP I –V responses with different pulse widths. The device has two graphene layers with width = 2.1 μm and length = 2.9 μm.
Fig. 9. ESD TLP characteristics of graphene device with pulse widths of (a) 10 and (b) 1000 ns. For 10 ns, the It2 per width is measured to be 7.9 mA/μm. For 1000 ns, the It2 per width are 1.2, 1.4, and 3.7 mA/μm for two, three, and four graphene layers, respectively. TABLE III It2 FOR D IFFERENT TLP P ULSE W IDTHS (mA/μm)
Fig. 11. (a) Drain current of graphene device d (in Table II) as a function of back gate voltage with drain voltage of 0.1 V for three sweeps. (b) Conductance of the graphene device d as a function of back gate voltage. For a given gate voltage, the conductance is measured by averaging the current due to applied drain voltages from 0 to 0.5 V. The device shows clear ambipolar behavior and the neutral point is at Vnp = 6 V, indicating a slightly p-type characteristic.
TLP technique a very unique electrothermal characterization tool for graphene. III. I MPACT OF G ATE C ONTROL
currents at which the nondestructive testing was performed (≈1.3–1.6 mA). This is in line with the earlier observations that thermal behavior is dominated by the substrate for graphene samples with small number of layers. Furthermore, this confirms that the compilation of data in Table III with different pulse widths on individually and destructively tested samples is a valid methodology for quantifying the robustness of graphene under high-current/ESD pulses. It should be noted that short-pulse stress conditions would usually provide a unique approach for studying thermal damage if the pulsewidth is much smaller than the thermal time constant of the device structure [18], [19]. The above analysis therefore demonstrates that with the proper choice of the TLP pulsewidth and/or the topology of the structures (including the thickness and thermal properties of the underlying dielectric), one can study the entire range of thermal stress conditions, from steady-state (dc-like) behavior to nonsteadystate situations, as discussed in [18]. This renders the
In Section II, samples were characterized without tuning the back gate bias. In this section, a new type of test-device with gate biasing is characterized under same stress conditions. For this particular device type, the substrate consists of 100-nm SiO2 on top of highly doped silicon, and the contact pad consists of 70-nm gold on top of 50-nm titanium. The highly doped silicon substrate can be biased and acts as a back gate. Fig. 11 shows the dc characteristics of one device under small drain bias (low electric field condition). The graphene in this device consists of three layers as characterized by Raman spectroscopy and has width and length of 6 μm and 2.4 μm, respectively. The device shows clear ambipolar behavior. The field-effect mobility (for low field, Vds = 0.1 V) for this device is calculated to be about 1600 cm2 /V-s using μ=
L Ids · W · Cox · Vds Vgs
(2)
where Cox is the back gate oxide capacitance per unit area (ignoring quantum capacitance due to large width). This number is in agreement with reported values in the literature for bilayer graphene [20]. Although there is a slight hysteresis shown in Fig. 11(a), the neutral point voltage is
LI et al.: ON THE ESD ROBUSTNESS OF GRAPHENE
Fig. 12. (a) TLP current as a function of gate voltage for device d. (b) DC conductance at different gate voltages according to Fig. 11(b).
Fig. 13. (a) Performance degradation after repeated TLP measurements under the gate voltage Vg = 40 V for device d. (b) Illustration of current degradation by neutral point shifting. G denotes the DC conductance.
almost unchanged at Vnp = 6 V, which indicates a p-doped device on SiO2 substrate. At neutral point, the resistance is maximum, and as the gate voltage increases (or decreases) away from the neutral point, the resistance decreases because of the increment in charge carrier densities (either electrons or holes). In graphene, the charge densities under gate bias can be approximated by [21] (3) n = n 20 + [Cox (Vg − Vnp )/q]2 where n 0 is the minimum sheet carrier concentration of graphene as determined by thermal excitation, disorder, and substrate interface, q is the elementary charge, and Vg and Vnp are the applied gate bias and neutral point voltage, respectively. This equation explains the fact that the carrier density (or the conductance) is minimum when Vg = Vnp , and increases as Vg moves away from Vnp . In order to perform multiple TLP measurements to observe any impact of the gate voltage, the maximum TLP voltage is chosen without damaging the device. Fig. 12(a) shows the TLP I –V curves for different gate biases. It can be observed that with increasing gate bias, the TLP current slightly decreases at first (from Vg = 0 to 10 V) then increases (from 10 to 30 V). This is explained in Fig. 12(b), where the channel conductance varies the same way as gate bias changes, indicating that the TLP current has direct relationship with the conductance. By increasing the difference between applied gate voltage and the neutral point voltage, TLP current increases due to larger carrier density, as can be explained by (3). Repeated TLP measurements are then performed at Vg = 40 V, as shown in Fig. 13(a). Interestingly, the TLP
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Fig. 14. (a) TLP measurements for negative gate bias and breakdown test under 100-ns TLP for device d. Note that two lines with Vg = −40 V are overlapping. (b) Illustration of neutral point shifting, which causes the current at Vg = −10 V to be larger than that of Vg = 40 V.
current decreases as the measurement repeats, and the degradation is most significant during the second measurement. We attribute this degradation to the effect of interface and oxide traps. For Vg = 40 V, electrons are the majority carriers, and during the first measurement the traps are filled by electrons. These electron-filled traps act as a screening layer that weakens the effect of back gate control. Effectively, one can describe this in terms of the more positive shift in neutral point, as shown in Fig. 13(b). As the neutral point shifts toward more positive, for the same Vg , the effective carrier density is smaller and therefore, current becomes smaller. This neutral point shifting will be larger for larger gate bias, as the traps in the oxide have larger probability to be activated due to larger oxide electric field. This neutral point shifting has been observed in many graphene devices, particularly for large gate bias [22]. For negative gate bias, the effect of gate control is shown in Fig. 14(a). As the gate voltage moves away from Vnp , the current increases. From Fig. 12(b), one would expect that the current at Vg = −10 V would be lower than that of Vg = 40 V, however, Fig. 14(a) does not show such a trend. This is because under a positive gate bias, the traps were filled with electrons. When a negative gate bias is applied, the majority carriers in the channel now become holes. The previously electron-filled traps also introduce positive image charges in the channel to increase carrier density. Similar to Fig. 13(b), we can also explain this using the neutral point shifting, as shown in Fig. 14(b). Because the neutral point shifts toward more positive values after third measurement of Vg = 40 V, it is now possible to have higher current at Vg = −10 V than that at Vg = 40 V, which is not possible during the initial measurement. From the above discussion, we can conclude that due to ambipolar nature of graphene and the fact that the carrier density of graphene (and its Fermi level) can be easily modulated by the gate electrostatics and trap states, graphene shows a unique gate biasing control effect, which not only depends on the bias amplitude, but also depends on the sign and sequence of gate biasing, thereby exhibiting unique memory effects. IV. C URRENT S ATURATION One interesting behavior observed from both Figs. 13 and 14 is that the I –V characteristics exhibit a bending at high voltages. Particularly, for large negative gate bias, the I –V curves
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Fig. 15. TLP current as a function of gate voltage for a bilayer graphene device with width and length of 3.3 and 2.5 μm, respectively. The red solid curve at the upper right corner represents a constant power.
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Fig. 17. densities.
Fitted mobility and saturation velocity as a function of carrier
saturation in the high field regime, which can also be regarded as velocity saturation, because the energy of surface optical phonon (55 meV) is much lower than that of optical phonon energy of graphene (150 meV). Using the carrier density formula in (3), the carrier velocity can be extracted according to J = qnv. From the curves at Vg = 0 V and Vg = 10 V, the minimum carrier density n 0 is first determined to be 4.5 × 1012 cm−2 , which is close to the existing reported value for trilayer graphene [24]. The extracted velocity is shown in Fig. 16. It can be observed that the velocity decreases as carrier density (related to gate bias) increases. Velocity saturation behavior is particularly obvious in Fig. 16(b). We can now approximate the carrier velocity by a simple velocity saturation model v=
Fig. 16. Extracted carrier velocities of device d for (a) positive and (b) negative gate biases. The fitted velocity curves are also shown as solid lines in (b).
display an obvious current saturation behavior. This current saturation behavior could be due to several effects. One factor could be the temperature rise due to Joule heating effects. However, we notice that for the same amount of power, not all the curves show current saturation. Fig. 15 best describes the situation, where for the same given power (red solid line), only curves with negative gate bias conditions show obvious current saturation behavior, whereas those under positive gate bias conditions show almost linear relationship. This indicates that there must be another more important factor that causes current saturation. An alternate root cause for current saturation could be an enhanced electron-phonon scattering at high electrical fields [21], [23]. For the structure of graphene on oxide, electron scattering due to surface optical phonons dominates the current
μE 1 + μE/vsat
(4)
where E is the electrical field in the channel along the graphene layer, μ is carrier mobility, and vsat is the saturation velocity of the carrier. The fitted mobility and saturation velocity is shown in Fig. 17, where both parameters decrease with increasing carrier density, in agreement with [21] and [23]–[25]. This is because a higher carrier density is correlated with higher Fermi level of the graphene, so that the probability of electrons to reach the energy threshold for surface optical phonon emission will be increased (i.e., enhanced scattering), thereby a reduction in mobility and saturation velocity occurs. At the same time, the enhanced scattering with surface optical phonons also leads to enhanced Joule heating and raises the local temperature. It should be noted that, the current saturation in graphene under high electric field is still not completely understood, although so far velocity saturation mechanism seems to be able to provide reasonably good explanation. The fitted curves are shown in Fig. 16(b) to compare them with the extracted data. It can be observed that for higher electrical field, the fitted curves overestimate the velocity. This overestimation may be due to the fact that the Joule heating and temperature effects on velocity are not considered in the fitting model yet. In the future, a more accurate model needs to be developed by taking into account Joule heating and temperature rise in a self-consistent manner.
LI et al.: ON THE ESD ROBUSTNESS OF GRAPHENE
V. C ONCLUSION This paper, for the first time, characterized graphene under high-current pulse/ESD conditions. The high TLP current carrying capability demonstrates the excellent robustness of graphene under ESD stress, which is potentially important for very advanced semiconductor and packaging technologies, as well as for various transparent conductor applications. Moreover, the fact that failure occurs in the graphene and not at the contacts indicates that intrinsic properties of this new material can be appropriately characterized using short-pulse stressing. Novel physical behavior has been revealed when graphene is investigated under high TLP current and high back gate voltage conditions. The existences of interface and oxide traps give rise to a bidirectional shifting of the neutral point under different gate biases. A current saturation behavior is observed and explained via velocity saturation at high electric filed. The application of short duration and high current pulses to graphene is, thereby proven to deliver unexpected and unique insights into this material. These unique features combined with graphene’s inherent flexibility, strength, and impermeability to moisture can also be potentially exploited for developing novel applications including robust ESD protection strategies in advanced semiconductor products as well as for touchscreen applications in various domains including mobile communication, automotive and aerospace, photon and thermal management, and sensors. ACKNOWLEDGMENT K.B. would like to thank the Alexander von Humboldt Foundation, Germany, for the Friedrich Wilhelm Bessel Research Award, which immensely facilitated this collaboration. R EFERENCES [1] A. K. Geim and K. S. Novoselov, “The rise of graphene,” Nature Mater., vol. 6, no. 3, pp. 183–191, 2007. [2] F. Schwierz, “Graphene transistors,” Nature Nanotechnol., vol. 5, pp. 487–496, May 2010. [3] H. Li, C. Xu, N. Srivastava, and K. Banerjee, “Carbon nanomaterials for next-generation interconnects and passives: Physics, status and prospects,” IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 1799–1821, Sep. 2009. [4] K. Banerjee et al., “Prospects of carbon nanomaterials for nextgeneration green electronics,” in Proc. 10th IEEE NANO, Nanotechnol. Conf., Aug. 2010, pp. 56–61. [5] Y. Khatami, W. Liu, J. Kang, and K. Banerjee, “Prospects of graphene electrodes in photovoltaics,” Proc. SPIE, vol. 8824, pp. 88240T-1–88240T-6, Sep. 2013. [6] S. Bae et al., “Roll-to-roll production of 30-inch graphene films for transparent electrodes,” Nature Nanotechnol., vol. 5, no. 8, pp. 574–578, 2010. [7] Z. Yao, C. L. Kane, and C. Dekker, “High-field electrical transport in single-wall carbon nanotubes,” Phys. Rev. Lett., vol. 84, no. 13, pp. 2941–2944, 2000. [8] B. Q. Wei, R. Vajtai, and P. M. Ajayan, “Reliability and current carrying capacity of carbon nanotubes,” Appl. Phys. Lett., vol. 79, no. 8, pp. 1172–1174, 2001. [9] R. Murali, Y. Yang, K. Brenner, T. Beck, and J. D. Meindl, “Breakdown current density of graphene nanoribbons,” Appl. Phys. Lett., vol. 94, no. 24, pp. 3114–3117, 2009. [10] A. D. Liao et al., “Thermally limited current carrying ability of graphene nanoribbons,” Phys. Rev. Lett., vol. 106, no. 25, p. 256801, 2011. [11] H. Li, C. C. Russ, W. Liu, D. Johnsson, H. Gossner, and K. Banerjee, “ESD characterization of atomically-thin graphene,” in Proc. 34th EOS/ESD Symp., Sep. 2012, pp. 1–8.
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[12] W. Liu, H. Li, C. Xu, Y. Khatami, and K. Banerjee, “Synthesis of highquality monolayer and bilayer graphene on copper using chemical vapor deposition,” Carbon, vol. 49, no. 13, pp. 4122–4130, Nov. 2011. [13] W. Liu, S. Krämer, D. Sarkar, H. Li, P. M. Ajayan, and K. Banerjee, “Controllable and rapid synthesis of high-quality and large-area Bernal stacked bilayer graphene using chemical vapor deposition,” Chem. Mater., vol. 26, no. 2, pp. 907–915, 2014. [14] W. Liu, J. J. Liou, A. Chung, Y.-H. Jeong, W.-C. Chen, and H.-C. Lin, “Electrostatic discharge robustness of Si nanowire field-effect transistors,” IEEE Trans. Electron Devices, vol. 30, no. 9, pp. 969–971, Sep. 2009. [15] Z. Chen, W. Jang, W. Bao, C. N. Lau, and C. Dames, “Thermal contact resistance between graphene and silicon dioxide,” Appl. Phys. Lett., vol. 95, no. 16, pp. 161910-1–161910-3, 2009. [16] Y. Khatami, H. Li, C. Xu, and K. Banerjee, “Metal-to-multilayergraphene contact—Part I: Contact resistance modeling,” IEEE Trans. Electron Devices, vol. 59, no. 9, pp. 2444–2452, Sep. 2012. [17] Y. Khatami, H. Li, C. Xu, and K. Banerjee, “Metal-to-multilayergraphene contact—Part II: Analysis of contact resistance,” IEEE Trans. Electron Devices, vol. 59, no. 9, pp. 2453–2460, Sep. 2012. [18] K. Banerjee, A. Amerasekera, N. Cheung, and C. Hu, “High-current failure model for VLSI interconnects under short-pulse stress conditions,” IEEE Trans. Electron Devices, vol. 18, no. 9, pp. 405–407, Sep. 1997. [19] K. Banerjee, D. Y. Kim, A. Amerasekera, C. Hu, S. S. Wong, and K. E. Goodson, “Microanalysis of VLSI interconnect failure modes under short-pulse stress conditions,” in Proc. 38th IEEE IPRS, Apr. 2000, pp. 283–288. [20] K. Nagashio, T. Nishimura, K. Kita, and A. Toriumi, “Mobility variations in mono- and multi-layer graphene films,” Appl. Phys. Exp., vol. 2, pp. 025003-1–025003-4, Dec. 2009. [21] I. Meric, M. Y. Han, A. F. Young, B. Ozyilmaz, P. Kim, and K. L. Shepard, “Current saturation in zero-bandgap, top-gated graphene field-effect transistors,” Nanotechnol., vol. 3, no. 11, pp. 654–659, 2008. [22] H. Wang, Y. Wu, C. Cong, J. Shang, and T. Yu, “Hysteresis of electronic transport in graphene transistors,” ACS Nano, vol. 4, no. 12, pp. 7221–7228, 2010. [23] A. M. Dasilva, K. Zou, J. K. Jain, and J. Zhu, “Mechanism for current saturation and energy dissipation in graphene transistors,” Phys. Rev. Lett., vol. 104, no. 23, p. 236601, 2010. [24] W. Zhu, V. Perebeinos, M. Freitag, and P. Avouris, “Carrier scattering, mobilities, and electrostatic potential in monolayer, bilayer, and trilayer graphene,” Phys. Rev. B, vol. 80, no. 23, p. 235402, 2009. [25] V. E. Dorgan, M.-H. Bae, and E. Pop, “Mobility and saturation velocity in graphene on SiO2 ,” Appl. Phys. Lett., vol. 97, no. 8, pp. 082112-1–082112-3, 2010.
Hong Li (S’07–M’12) received the Ph.D. degree in electrical and computer engineering from the University of California, Santa Barbara, CA, USA, in 2012. He is currently an Emerging Memory Engineer at Micron Technology Inc., Boise, ID, USA. He has authored and co-authored more than 30 publications.
Christian C. Russ received the M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich, Munich, Germany, in 1991 and 1999, respectively. He is currently a Principal Engineer at Intel Mobile Communications, Munich, where he is involved in ESD issues in CMOS technologies (28 nm, 14 nm, and below).
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Wei Liu (M’10) received the Ph.D. degree in chemistry from the Institute of Chemistry, Chinese Academy of Sciences, Beijing, China, in 2008. He is currently a Post-Doctoral Scholar with the Electrical and Computer Engineering Department, University of California, Santa Barbara, CA, USA.
Harald Gossner (M’06–SM’11) received the B.S. (Dipl.Phys.) degree in physics from the LudwigMaximilians-Universität München, München, Germany, and the Ph.D. degree in electrical engineering from Universität der Bundeswehr, München, in 1990 and 1995, respectively. He is currently a Senior Principal Engineer at Intel Mobile Communications, München, where he is involved in the development of robust mobile systems.
David Johnsson received the M.Sc. degree in electrical engineering from the Royal Institute of Technology, Stockholm, Sweden, in 2006. He is currently a member of the ESD team at Intel Mobile Communications, Munich, Germany. He is also a Co-Founder of High Power Pulse Instruments, Munich, where he develops software and hardware for TLP systems.
Kaustav Banerjee (S’92–M’99–SM’03–F’12) received the Ph.D. degree in electrical engineering and computer science from the University of California, Berkeley, CA, USA, in 1999. He is currently a Professor of Electrical and Computer Engineering with the University of California, Santa Barbara, CA, USA.
