Oscillation and Sequential Behavior Caused by ... - Semantic Scholar
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits Haluk Konuk haluk [email protected] California Design Center Hewlett-Packard Company
F. Joel Ferguson [email protected] Computer Engineering Dept. University of California at Santa Cruz
Abstract Shorts and opens are the most common types of defects in today’s CMOS ICs. In this paper we show for the first time that an open in the interconnect wiring of a digital CMOS circuit can cause oscillation or sequential behavior. We also analyze and compare the factors affecting the probabilities for an interconnect open and a feedback bridging fault to oscillate or display sequential behavior.
1
Introduction
Opens are one of the most common types of defects that occur during an IC manufacturing process [1]. Opens fall into different categories depending on their location in a digital CMOS circuit: An open can occur inside a CMOS cell affecting transistor drain and source connections [2, 3, 4, 5], at the gate input of a single transistor [6, 7], or on the interconnect separating a set of logic-gate inputs from their drivers, which allows the input voltage to float. In today’s CMOS ICs with five or more metal layers, interconnect wiring seems to be the most likely place for an open occur. Vias are especially susceptible to opens, and the number of vias is exceeding the number of transistors in some microprocessor designs [8]. We call the fault created by an open in the interconnect wiring an interconnect open. In this paper we show that an interconnect open can create capacitive feedback paths in a CMOS circuit, thus causing oscillation and sequential behavior. We also show under what conditions this previously unreported phenomenon will occur. Capacitive coupling as low as 1 femto-farad between signal lines can activate the feedback path as we demonstrate in Section 2.1. Since this is the first time this phenomenon is reported for opens, there is no previous published work for direct comparison. Knowing the cause and
necessary conditions for oscillation and added state (1) provides the limits to simpler models of interconnect opens, (2) may lead to more accurate fault grading of interconnect opens, (3) helps in the development of a more effective testing strategy, and (4) may allow this phenomenon to eventually be considered in test pattern generation. In this paper we also discuss, for comparison purposes, the conditions for an interconnect open and a bridging fault to display oscillatory or sequential behavior. Even though the examples in this paper use gates from a standard cell library, an interconnect open can also cause oscillation and sequential behavior in custom designs that use fully complementary static CMOS.
2
Oscillations due to Interconnect Opens
Wire-to-wire and Miller capacitances to the floating wire created by an interconnect open are the two types of feedback capacitances that can cause an interconnect open to oscillate. We discuss them in the following.
2.1
Feedback via Wire-to-Wire Capacitance
Consider the circuit in Figure 1. Node f loat is floating due to an interconnect open defect. CVDD represents the total capacitance between f loat and all neighboring nodes that are at VDD (excluding the Miller capacitances). These neighboring nodes include other signal wires at VDD , power wires carrying VDD , and n-wells that are tied to VDD . Similarly, CGND represents the total capacitance between f loat and all neighboring nodes that are at GND (excluding the Miller capacitances). These nodes include signal and power wires at GND, and the p-substrate.
sum of cap.’s to logic-1 wires and VDD interconnect open X
CVDD
Cwire-to-wire
float CGND
q Cw
S 1 -> 0
out Cw
Cw
sum of cap.’s to logic-0 wires and GND Figure 1: Circuit to demonstrate oscillation due to a wire-to-wire capacitance VDD
3.2 q float 2.8
float
VOLTAGE (V)
2.4
2
1.6
GND 1.2
Figure 3: Miller capacitances in an inverter. 800m
400m
0 0
2
4
6
8
10
12
14 16 18 (nanoseconds)
Figure 2: HSPICE result for the circuit in Figure 1 Cwire to wire represents the capacitance between the wires q and f loat, and finally CW represents the total wiring capacitance for each wire labeled with CW . Note that Cwire to wire is the only feedback capacitance in the example of Figure 1. Let’s now assign some values to these capacitances. In order to come up with realistic values, we used the MAGIC technology file available from MOSIS [9] for the HP 0.6µ fabrication process. We used 20fF for each CW , which corresponds to a 153µ long minimum width metal-1 wire over substrate. For comparison, the cell height in the MCNC cell library is 17.4µ in this process. We used 12fF for CGN D , 8fF for CVDD , and 1fF for Cwire to wire . A 1fF capacitance between two parallel metal-1 wires separated by 0.9µ corresponds to 24µ of metal-1 length. This
length decreases to 21µ for metal-2 and 15µ for the metal-3 layer. With a quick glance at the layout of any ISCAS85 circuit, it is easy to find many wires running in parallel for more than 75µ. We simulated the circuit in Figure 1 using the MCNC cell library with HSPICE with VDD = 3.3V, and using the BSIM parameters for the HP 0.6µ process from MOSIS [9]. The HSPICE results are shown in Figure 2. We started with all the nodes at 0V, and powered up the circuit during the first 1ns, that is, VDD went from 0V to 3.3V. At 3ns, signal S in Figure 1 went from 3.3V to 0V in 1ns. This formed an inverting path from f loat to q, and node q started oscillating as shown with the solid line in Figure 2 due to the electrical feedback created by Cwire to wire . Note that this circuit would never oscillate if it did not have the interconnect open or any other defect. The voltage around which f loat will oscillate is determined by the values of CVDD , CGN D , and the Miller capacitances [2] in the inverter driven by f loat, as shown in Figure 3. Given these capacitances, the size of Cwire to wire determines the ∆Vf loat /∆Vq ratio. If Cwire to wire is not large enough, oscilla-
OAI22 tion will not occur. Since the gate/source and the gate/drain capacitances for the inverter in Figure 3, b1 = 1 a1 = 0 also referred to as the Miller capacitances by Konuk et al. [2], are non-linear, and the voltage at the output of the inverter has a non-linear relationship to its input, we used HSPICE simulation to see the effects q float b2 of these Miller capacitances. Simulating the circuit in Figure 3 shows that f loat acquires 1.65V with VDD = b1 = 1 3.3V for the i1s inverter in the MCNC library, which is the inverter type used in Figure 1. In general, the a1 = 0 floating input of any gate will be forced to a value S2 a2 around VDD /2 by the Miller capacitances of the pand the n-channel transistors driven by the floating input1 , when the gate output is sensitized to this input. Figure 5: Miller capacitances to node f loat in FigIn Figure 2, the f loat oscillates between 1.50V and ure 4 1.57V. This 0.07V swing in f loat is sufficient for q to oscillate as the total gain of the path from f loat to q is high enough within the voltage range f loat 2.2 Feedback via Miller Capacitance is moving. If the voltage on f loat was centered at We will now show another mechanism that can 1.00V, then the total gain of the inverting path might make an interconnect open oscillate. Consider the cirnot have been sufficient for an oscillation with f loat cuit in Figure 4, which is obtained by removing the changing only 0.07V. Given the transistor sizes in the Cwire to wire in Figure 1 and replacing the inverter i1s inverter, CVDD and CGN D determine where the that drives node q with an OAI22 (Or-And-Invert) voltage of f loat will be centered. gate from the MCNC library. Cwire to wire was reCVDD CGND Cwire
to wire,min
10fF 10fF 6.5fF
Table 1: Minimum Cwire in Figure 1
9fF 11fF 4.0fF to wire
8fF 12fF 1.0fF
7fF 13fF 3.0fF
6fF 14fF 5.5fF
values for oscillation
Assuming that CVDD + CGN D = 20fF, we constructed Table 1 with HSPICE simulations, where Cwire to wire,min is the minimum capacitance between q and f loat in increments of 0.5fF such that the circuit will still oscillate. Note that as Cwire to wire increases, the ∆Vf loat /∆Vq ratio will also increase. We define oscillation as the case where the swing at out’s voltage exceeds the swing at f loat’s voltage. Among the five data points in Table 1, CVDD = 8fF and CGN D = 12fF is the case where the gain in the inverting path is the maximum; thus, even 1fF for Cwire to wire is sufficient for an oscillation as we showed earlier. Note that Cwire to wire,min needs to be larger as we move away from the 8fF-12fF point in either direction, as the inverting path gain gets smaller. 1 Assuming fully complimentary CMOS gates with each input driving one p- and one n-channel transistor.
sponsible for the feedback loop in Figure 1 between q and f loat. In Figure 4, however, the feedback from q to f loat is created by the Miller capacitances of the transistors inside the OAI22 gate. These Miller capacitances are shown in Figure 5, where they are connected with dotted lines to emphasize that they are not additionally inserted into the circuit, but they are part of every CMOS transistor. The total Miller capacitance for a transistor can be as large as the total gate-oxide capacitance depending on the region the transistor is operating. The interested reader can refer to the “Introduction to Transcapacitance” and the BSIM “Charge-Based Capacitance Model” sections in the HSPICE User’s Manual [10], and Sheu et al. [11]. The HSPICE simulation result for the circuit in Figure 4 is shown by Figure 6, where we used 8fF, 12fF, and 20fF for CVDD , CGN D , and CW ,respectively, as we did for Figure 2. VDD goes from 0V to 3.3V in the first 1ns, where all nodes in the circuit start from 0V. At 3ns, S1 goes from 3.3V to 0V in 1ns sensitizing the inverting path from f loat to q resulting in an oscillation. Note that this circuit would be a purely combinational circuit, and would never oscillate, if it did not have the interconnect open or any other defect. In order to find the sensitivity of this oscillation to the sizes of the wiring capacitances connected to
OAI22
CVDD interconnect open
X
1 q
C GND
out
0
float Cw
S1 1 -> 0
S2 Cw Cw
Figure 4: Circuit to demonstrate oscillation due to Miller capacitances q float
general. CVDD has two major components; the total capaci2.8 tance from f loat to other signal wires at logic-1 value, and the total capacitance from f loat to the n-wells 2.4 (assuming an n-well technology, such as the HP 0.6µ) and to the power wires. On average, the capacitance 2 to signal wires at logic-1 value will be the same as the capacitance to wires at logic-0, and the capacitance to 1.6 the power wires will be the same as the capacitance 1.2 to the ground wires. However, n-wells will usually occupy less area than the p-substrate. Therefore, in 800m general it is reasonable to expect that CVDD will be smaller than CGN D on average, but close to it, which 400m is exactly the oscillation requirement we discussed in the preceding paragraph as illustrated by Table 2. 0 2 4 6 8 10 12 14 16 18 0 The last row in Table 2 requires a very narrow (nanoseconds) range for CVDD , but 400fF corresponds to a very Figure 6: HSPICE result for the circuit in Figure 4 long wire in the HP 0.6µ technology, which would be a more than 3mm long metal-1 wire over substrate. In general, oscillation due to Miller feedback capacitances is more likely when (CVDD + CGN D ) is small f loat, we performed HSPICE simulations to conas also shown by Table 2, because the Miller feedback struct Table 2. CVDD ,min and CVDD ,max are the minicapacitance sizes are fixed by the transistor sizes. mum and maximum capacitance values for CVDD such that the circuit in Figure 4 still oscillates. We define oscillation as the case where the swing at out’s 3 Sequential Behavior due to voltage exceeds the swing at f loat’s voltage. The Interconnect Opens last two columns in Table 2 show that CVDD needs to be smaller than CGN D for an oscillation, but not too small. The last row shows that CVDD to In this section we show how an interconnect open can CVDD +CGN D ratio needs to be 0.46 as CVDD +CGN D cause sequential behavior. As in the case of oscillagets very large. This implies that the voltage around tion, the two types of feedback capacitances responsiwhich f loat needs to oscillate is 0.46 · VDD . This ble for sequential behavior are wire-to-wire and Miller is probably mostly true independent of which MCNC capacitances to the floating node created by the open. gates are used, because 1.05V and 1.90V are the maximum logic-0 and the minimum logic-1 voltages, re- 3.1 Feedback via Wire-to-Wire Caspectively, for the MCNC cell library using the HP pacitance 0.6µ BSIM parameters. Note that the mid-point between 1.05V and 1.90V is 1.47V, which is equal to Consider the circuit in Figure 7. We will now describe 0.45 · VDD . Also, gates from other cell libraries are why this circuit acts like a latch because of the interlikely to have this property, because n-channel tran- connect open. Let Qs denote the electrical charge on sistors conduct better than the p-channel ones, in the f loat side plate of Cwire to wire plus the electri-
VOLTAGE (V)
3.2
CVDD + CGN D 20fF 30fF 40fF 50fF 60fF 400fF
CVDD ,min 2.0fF 6.5fF 11.5fF 16.0fF 20.5fF 180.0fF
CVDD ,max 10.0fF 14.5fF 19.0fF 23.5fF 28.0fF 184.5fF
CVDD ,min CVDD +CGN D
CVDD ,max CVDD +CGN D
0.10 0.22 0.29 0.32 0.33 0.45
0.50 0.48 0.47 0.47 0.47 0.46
Table 2: The capacitance ranges for oscillation in Figure 4
interconnect open
X
Vq (V)
Qs (F)
Cwire-to-wire
3.2
CVDD
20f
float
10f
Q s = 54.6fC - 30fF * Vfloat
3
q
2.8
2 1
2.4
0
CGND
a
0
-10f
b
2
c 1.6
-20f
Figure 7: Circuit to demonstrate sequential behavior due to a wire-to-wire capacitance
-30f
1.2
Q s = 31.8fC - 30fF * Vfloat -40f
800m
Vq cal charge on the transistor gates of the NOR gate -50f connected to f loat. In order to find the relationship non-floating Qs 400m between Qs and the voltage on the input, we varied Vf loat from 0V to VDD by driving node f loat in -60f 0 500m 1 1.5 2 2.5 3 V HSPICE, and obtained the non-floating Qs curve 0 float shown in Figure 8 using Cwire to wire = 10fF. Note the sudden fall in the non-floating Qs around Vf loat = Figure 8: Illustration of one metastable and two sta1.7V due to the capacitive feedback from q to f loat. ble states When we add the assumption that node f loat is actually floating, then the following equation needs to the metastability in a latch [14]. Therefore, point b be satisfied, also: is not a real solution. Points a and c are stable states. Figure 8 illusQinit = Qs + CGN D · Vf loat + CVDD · (Vf loat − VDD ) trates Vq (the voltage on node q) with a dashed line, where Qinit is the trapped charge on f loat during which shows that the Vf loat values corresponding to the fabrication process [12] [13]. The above equation points a and c are interpreted as logic-0 (Vq = 0V ) and logic-1 (Vq = 3.3V ), respectively. The straight can be rewritten as follows: line for Equation 1 moves up as CVDD increases, and moves down as it decreases, with (CVDD +CGN D ) and Qs = Qinit +CVDD ·VDD −(CVDD +CGN D )·Vf loat (1) Qinit being constants for a given open. Recall that CVDD represents the total capacitance between f loat In Figure 8, there are three straight dotted lines and all neighboring nodes that are at VDD , which is corresponding to Equation 1 with three different determined by the vector applied to the circuit for (CVDD · VDD ) values using CVDD + CGN D = 30fF and a given open, and that is why we will refer to this Qinit = 0. Note that line 2 intersects the non-floating straight line as the vector line. Also, the value of Qs at three points, which represent three different so- Qinit , which is determined by the fabrication process lutions. Point b corresponds to a metastable state, for a given open, biases the vector line. because even the slightest disturbance on Vf loat will If the vector line moves down past line 1 or up past kick the solution point to either a or c, very much like line 3 in Figure 8, then it intersects the non-floating
Qs at a single point. Between lines 1 and 3, the real solution is determined by the previous value of Vf loat . Vf loat will remain at logic-0 if the vector line moves below line 1 at least once, and stays below line 3. Similarly, it will remain at logic-1 if the vector line moves above line 3 at least once, and stays above line 1. Therefore, the latch behavior is observed only in the region between lines 1 and 3. CVDD is 9.6fF and 16.5fF for lines 1 and 3, respectively. Recall that we used CVDD +CGN D = 30fF, and CVDD will be smaller than CGN D but close to it on average as we discussed in Section 2.2. Therefore, it is reasonable to expect that the vector line will be within lines 1 and 3 in a significant number of vectors applied to the circuit. In general, for any interconnect open as shown in Figure 7 with an even number of inverting gates from f loat to q, the corresponding curves will look like the ones in Figure 8. If we assume a gain of 10 for a single inverting gate, then the cascaded gain for even number of inverting gates will be 100, 10000, etc. Therefore, Vq will make a jump from 0V to VDD with ∆Vf loat = VDD /(cascaded gain) at a critical Vf loat value determined by the type of gate driven by the f loat. This quick jump in Vq is responsible for the sudden drop in the non-floating Qs , which also marks the transition from logic-0 to logic-1. The size of Cwire to wire together with the transistor sizes connected to the f loat determines the amount of drop in the non-floating Qs . Equation 1 shows that the slope of the vector line is -(CVDD +CGN D ), which is a constant for a given interconnect open. In order for the vector line to intersect the non-floating Qs always at a single point, it must be steeper than the rate of fall in the non-floating Qs . In our example in Figure 8, this would require (CVDD +CGN D ) to be larger than 600fF, which corresponds to a metal-1 wire over substrate with a length of over 4.5mm, which is a very long wire. Therefore, as long as (CVDD + CGN D ) is not extremely large and Cwire to wire is not extremely small, the vector line will intersect the non-floating Qs at three points for a range of CVDD , where one point is a metastable state and the other two are for logic-0 and logic-1.
3.2
Feedback via Miller Capacitance
The feedback we described in the preceding subsection was due to a wire-to-wire capacitance from output to input. We will now show that the same capacitive feedback can occur via the transistor gate-oxide capacitances, more specifically, the Miller feedback capacitances. These two mechanisms were also shown to be responsible for the oscillatory behavior in Sec-
XOR
interC connect VDD open float X
q
C GND 0
Figure 9: Circuit to demonstrate sequential behavior due to Miller capacitances tions 2.1 and 2.2. Consider an XOR gate with one input floating due to an interconnect open, and the other input at logic-0, as shown in Figure 9. The noninverting path from f loat to q through the NOR gate inside the XOR gate is analogous to the non-inverting path in Figure 7. The Miller capacitances connecting q to f loat inside the XOR gate form a feedback loop, the same way Cwire to wire does in Figure 7. In this case Qs is simply the total electrical charge on the floating input of the XOR gate. Figure 10 shows the non-floating Qs together with Vq as computed by HSPICE. Note that these curves are very much like the ones in Figure 8. Therefore, this XOR gate with a floating input displays a sequential behavior just as the circuit in Figure 7 does. In Table 3 we computed the range of CVDD for different (CVDD + CGN D ) values such that this XOR gate displays sequential behavior, that is, the vector line intersects the non-floating Qs at three points, one being metastable and the other two being logic-0 and logic-1. Interestingly, the numbers in Table 3 are very close to the ones in Table 2. Standard cell layouts usually have vias over them to connect signal wires to their inputs and outputs, and vias are particularly susceptible to opens. We removed one of the input vias for the XOR gate, and extracted all its capacitances using a 0.8µ MAGIC technology file, which had the most detailed extraction information we could find. The floating input had some wire-to-wire capacitance to the output of the XOR gate and to the output of the NOR gate inside the XOR. We included these capacitances in our Qs computation using HSPICE. (CVDD + CGN D ) was 9.1fF with a 5.1fF capacitance to the substrate and the GND line and a 1.9fF capacitance to the n-well and the VDD line. So, the minimum and max-
CVDD + CGN D 10fF 20fF 30fF 40fF
CVDD ,min 0.0fF 2.2fF 6.6fF 11.0fF
CVDD ,max 6.0fF 10.2fF 14.4fF 18.6fF
CVDD ,min CVDD +CGN D
CVDD ,max CVDD +CGN D
0.00 0.11 0.22 0.27
0.60 0.51 0.48 0.46
Table 3: Capacitance ranges for sequential behavior in Figure 9
Symbol
Vq (V)
Qs (F)
3.2
30f
Vq 2.8 20f
2.4
10f 2
0 1.6
1.2
-10f
non-floating Qs (charge on the XOR gate input)
800m
-20f
400m
-30f
0
500m
1
1.5
2
2.5
3
Vfloat
Figure 10: Illustration of similarity to the curves in Figure 8 imum possible CVDD values were 1.9fF and 9.1 - 5.1 = 4.0fF, which correspond to vector lines that intersect the non-floating Qs curve at three points. Therefore, this floating input XOR gate will display sequential behavior with any vector applied that makes its faultfree input logic-0 as shown in Figure 9. We repeated the same for the other input of the XOR gate, and found the same result. To give an idea of how often XOR or XNOR gates might be used; 0% to 57% of all the gates in the ISCAS85 layouts are XOR or XNOR gates depending on the circuit.
4
Feedback Activation
In this section we discuss the factors affecting the probabilities for a feedback bridging fault and an interconnect open to display feedback behavior, where we define feedback behavior to mean either oscillation or sequential behavior. Additional information on the oscillation frequency and amplitude, and
IDDQ testability of feedback bridging faults is given by [15, 16, 17, 18]. For a feedback bridging fault, we need to use the concepts of back gate, back wire, front gate, and front wire [19], which are depicted in the example of Figure 12. In order for a feedback bridging fault to display feedback behavior, at least the combinational path from the back wire to an input of the front gate needs to be sensitized. We call this condition partial sensitization. If the path from the back wire to the front wire is sensitized in the fault-free circuit, we call this condition full sensitization. Similarly, for an interconnect open to display feedback behavior, the combinational path from its floating wire A to at least one other wire B needs to be sensitized, where there is a wire-to-wire or a Miller feedback capacitance between A and B.
4.1
Feedback Activation for Shorts
Since it is not as easy to see how feedback behavior can occur with partial sensitization as it is with full sensitization, we will now describe an example oscillation with partial sensitization. Assume that the side input C of the NAND gate in Figure 11 is 0, and the path through the combinational logic block is sensitized; thus partial sensitization. Also, assume that there are even number of inversions from the back wire to the input of the front gate, and A = 1, B = 0 for the back gate. When the on-path input of the front gate is 1, let’s assume that the back gate wins the fight, thus the back wire becomes logic-0. When this logic-0 arrives at the on-path input of the front gate, it turns one more p-channel transistor on, which, we assume, will make the front gate win the fight this time. So, back wire becomes logic-1, which propagates to the on-path input of the front gate; thus oscillation.
More Current Paths in the Back Gate Here we assume that the applied vector has created a full sensitization condition. If the back gate wins the drive fight against the front gate, then no feedback behavior will be observed. That is, the front gate
feedback bridging fault A
C
B
X X
A
B
combinational logic C
Figure 11: Circuit to demonstrate more current paths in the back gate. must win for feedback behavior to occur when full sensitization is achieved. Since the path from the back wire to the front wire is sensitized, the output of the front gate must be also sensitized to its input on this path. Assuming that this input goes to one nchannel and one p-channel transistor inside the front gate, then there is only one current path from VDD to the front wire or from the front wire to GND inside the front gate2 . On the other hand, there might be more than one current path from VDD to the back wire or from the back wire to the GND inside the back gate. For example, in Figure 11 when A = B = 1, two current paths exist through the n-channel transistors, in which case the back gate is most likely to win. The side input C of the front gate in Figure 11 must be 1 because of the full sensitization condition. In order to compute the probability of a front gate winning, let’s make the following assumptions: 1. 75% of the gates used in a chip can have multiple current paths depending on the gate inputs; unlike an inverter, which can have only one current path. 2. The back gate wins when it has more than one current path. 3. Given a gate that can have multiple current paths, the probability for an input combination that will activate multiple current paths is 25%. For instance, the back gate in Figure 11 will have multiple current paths only when A = B = 1;
It follows from these assumptions that the probability of a front gate winning is 13/32 = 41%. This probability is actually smaller due to the reasons we describe in the following, which affect assumption 4 above.
Degraded Voltage on the Back Wire Here we assume either a partial or full sensitization condition. Due to the drive fight between the back and the front gates, the back wire cannot have a rail voltage but an intermediate value between VDD and GND. If the logic gate(s) from the back wire to the input of the front gate cannot pull this intermediate voltage to a rail value, then the drive strength of the front gate will be diminished, which decreases its chances to win the drive fight against the back gate; thus, diminishing the chances for feedback behavior. As an example consider the feedback bridging fault in Figure 12. The HSPICE simulation result with Rshort = 0 is shown in Figure 13, where VDD and S went from 0V to 3.3V during the first 1ns, and S went to 0V at 4ns. The degraded voltage at qback causes the voltage on q2 to be 3.1V instead of 3.3V. This decreases the drive strength of the front gate, and the back gate wins the fight, resulting in no oscillation. When we insert two inverters between the NOR gate and the front gate in Figure 12, only then the circuit starts oscillating. In order to verify that sequential behavior is also affected by degraded voltage on qback , we removed the inverter acting as the front gate in Figure 12, and made the output of the NOR gate qf ront . The HSPICE simulation with Rshort = 0 showed that qf ront goes logic-0 to logic-1 after S switches from 1 to 0, which means that the NOR gate cannot win the drive fight against the back gate due to the inability of one inverter to pull the degraded back wire voltage to a rail; thus, no sequential behavior is observed. When we insert an inverter between the NOR gate and the front gate in Figure 12, only then qf ront stays at logic-0 after S switches from 1 to 0, which means that the circuit is now acting like a latch.
Bridging Resistance
Here again we assume either a partial or full sensitiza4. The probability of the front gate winning is 50% tion condition. So far we assumed the bridging resiswhen there is a single current path both in the tance to be zero, but Rodriguez-Montanes et al. [20] front and back gates. Thus, we implicitly assume showed that most of the metal bridging resistances that the bridging fault resistance is zero. fall into the range from 0Ω to 1000Ω in an exper2 Unless multiple paths are sensitized from the back wire to imental study. As the bridging resistance increases the front wire, which is unlikely. the voltage on the back wire gets closer to what the
R short
VOLTAGE (V)
nodes that are at logic-0 gives CGN D . Capacitances from dependent nodes to the floating wire form the back gate feedback capacitances. front gate q1 q2 X Dependent nodes become most sensitive to the 0 X q_back S floating wire voltage when the floating wire voltage q_front 1 -> 0 is around VDD /2. For the examples corresponding to Tables 2 and 3, 0.45*VDD on the floating wire creFigure 12: Circuit to show the effects of degraded ates the most sensitivity. A signal wire may cross voltage and resistive short several other signal wires that run perpendicularly on the metal layer below or above, creating a lot of Symbol D0:A0:q_back 3.2 D0:A0:q1 D0:A0:v(q2 very small capacitances to it. If we assume N such crossings between the floating wire and other signal 2.8 wires that are independent of the floating wire voltq2 q1 age, a 0.5 probability for each such signal wire to be 2.4 q_back logic-1, and a normal distribution for the number of 2 wires at logic-1 among the N signal wires, then the probability P (x) that x wires are at logic-1 is given 1.6 by the following [21]: r 1.2 2 2 · e−2·(x−N/2) /N P (x) = N · π 800m 400m
0 0
2n
4n
6n
8n
10n 12n 14n 16n 18n (nanoseconds)
Figure 13: HSPICE results for the circuit in Figure 12 back gate is driving; thus reducing the chances for the front gate to win the drive fight for the back wire. As we explained above, the circuit in Figure 12 with Rshort = 0 starts oscillating only when we insert two more inverters. However, it stops oscillating when Rshort ≥ 450Ω. Similarly, we showed that the same circuit with Rshort = 0 displays sequential behavior only when we insert an additional inverter. However, the sequential behavior disappears when Rshort ≥ 427Ω. According to Rodriguez-Montanes et al. [20], 31% of the bridges have a resistance greater than 500Ω.
4.2
Feedback Activation for Opens
Given a vector applied to the combinational circuit inputs, all the nodes that have a wire-to-wire or a Miller capacitance to the floating wire that is created by an interconnect open fall into two classes: nodes whose voltages depend on, and nodes whose voltages are independent of the floating wire voltage. Adding up the wire-to-wire capacitances to the independent nodes that are at logic-1 gives CVDD , and adding up the wire-to-wire capacitances to the independent
When N = 10, the probability that 4, 5, or 6 wires are at logic-1 is 0.67. When N = 20, the probability that the number of logic-1 wires is in the range from 8 to 12 is 0.74. When N = 30, the same probability is 0.80 for the range from 12 to 18. Therefore, neighboring signal wires tend to bias the floating wire around VDD /2 when there are many of them with small capacitances. In contrast to bridging faults, note that there is no requirement for a gate to outdrive another gate in case of opens to display feedback behavior, because an interconnect open does not cause any drive fight, at all. Once the floating wire voltage is biased around VDD /2, then the feedback capacitance(s) need(s) to be large enough to cause feedback behavior. The size of a feedback capacitance is very much layout dependent, but wire-to-wire capacitances are growing in importance compared to other capacitances in a layout, because the number of metal layers is increasing, and metal lines on the same layer are getting closer to each other as the smallest feature size decreases. With this trend, the probability of feedback behavior from an interconnect open will increase. The fact that a feedback bridging fault between wire A and wire B corresponds to a feedback capacitance from B to A when wire A is floating due to an open can be exploited to perform more rigorous analysis comparing the probabilities of shorts and opens causing feedback behavior. We leave this analysis as a future work item. As a related reference, Maxwell et al. [22] used total wiring capacitance values esti-
mating the likelihoods of bridging faults to come up with a weighted stuck-at fault coverage measure.
[7] M. Renovell and G. Cambon. Electrical analysis and modeling of floating-gate fault. IEEE Transactions on Computer-Aided Design, pages 1450–1458, November 1992.
5
[8] K.M. Thompson. Intel and the myths of test. In The Keynote Address of International Test Conference, October 1995.
Summary
This paper describes how interconnect opens, due to feedback capacitive coupling, may cause oscillation or sequential behavior, and provides a basis for developing an accurate fault simulator or any other test tool regarding interconnect opens. The capacitive feedback can come from either wireto-wire capacitance of as little as 1 femtofarad or from Miller feedback capacitances from within a logic-gate. The range of initial voltages on the floating node to allow oscillation or additional state to occur is in the vicinity of VDD /2, which is likely to be the voltage the node is charged to due to Miller capacitances during circuit power up. The analysis we presented for the necessary conditions for a feedback bridging fault and an interconnect open to display feedback behavior does not clearly point out which one is more likely. A more rigorous analysis or experiments are necessary to determine the relative likelihoods.
Acknowledgments The first author acknowledges Doug Sojourner of HP for his support and valuable technical input. We also acknowledge the support from SRC contract 96-DJ315 and NSF grant MIP-9158491.
References [1] C.F. Hawkins, J.M. Soden, A.W. Righter, and F.J. Ferguson. Defect classes - an overdue paradigm for CMOS IC testing. In Proceedings of International Test Conference, pages 413–425, October 1994. [2] H. Konuk, F.J. Ferguson, and T. Larrabee. Charge-based fault simulation for CMOS network breaks. IEEE Transactions on Computer-Aided Design, pages 1555–1567, December 1996. [3] C. Di and J.A.G. Jess. On accurate modeling and efficient simulation of CMOS opens. In Proceedings of International Test Conference, pages 875–882, October 1993. [4] M. Favalli, M. Dalpasso, P. Olivo, and B. Ricco. Modeling of broken connections faults in CMOS ICs. In Proceedings of European Design and Test Conference, 1994. [5] W.M. Maly, P.K. Nag, and P. Nigh. Testing oriented analysis of CMOS ICs with opens. In Proceedings of International Conference on Computer-Aided Design, pages 344–347, November 1988. [6] V.H. Champac, A. Rubio, and J. Figueras. Electrical model of the floating gate defect in CMOS IC’s: Implications on IDDQ testing. IEEE Transactions on ComputerAided Design, pages 359–369, March 1994.
[9] MOSIS ftp site: ftp.mosis.edu. Directory /pub/mosis. [10] Meta-Software. HSPICE User’s Manual: Elements and Models. 1992. [11] B.J. Sheu, W.-J. Hsu, and P.K. Ko. An MOS transistor charge model for VLSI design. IEEE Transactions on Computer-Aided Design, pages 520–527, April 1988. [12] S. Johnson. Residual charge on the faulty floating gate MOS transistors. In Proceedings of International Test Conference, October 1994. [13] Haluk Konuk and F. Joel Ferguson. An unexpected factor in testing for CMOS opens: The die surface. In Proceedings of the IEEE VLSI Test Symposium, 1996. [14] E.J. McCluskey. Logic Design Principles with Emphasis on Testable Semicustom Circuits. Prentice Hall, 1986. [15] M. Roca and A. Rubio. Current testability analysis of feedback bridging faults in CMOS circuits. IEEE Transactions on Computer-Aided Design, pages 1299–1305, October 1995. [16] D. Lu and C.Q. Tong. Feedback bridging fault detection using current monitoring. In Proceedings of the 35th Midwest Symposium on Circuits and Systems. [17] B.K. Koch and K.D. Muller-Glaser. An examination of feedback bridging faults in digital CMOS circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems, 1993. [18] R. Rajsuman. An analysis of feedback bridging faults in MOS VLSI. In Proceedings of the IEEE VLSI Test Symposium, 1991. [19] B. Chess and T. Larrabee. Bridge fault simulation strategies for CMOS integrated circuits. In Proceedings of Design Automation Conference, 1993. [20] R. Rodriguez-Montanes, E.M.J.G. Bruls, and J. Figueras. Bridging defects resistance measurements in a CMOS process. In Proceedings of International Test Conference, pages 892–899, October 1992. [21] H.L. Alder and E.B. Roessler. Introduction to Probability and Statistics. W.H. Freeman and Company, 1964. [22] Peter C. Maxwell, Robert C. Aitken, and Leendert M. Huisman. The effect on quality of non-uniform fault coverage and fault probability. In Proceedings of International Test Conference, pages 739–746, October 1994.
F. Joel Ferguson [email protected] Computer Engineering Dept. University of California at Santa Cruz
Abstract Shorts and opens are the most common types of defects in today’s CMOS ICs. In this paper we show for the first time that an open in the interconnect wiring of a digital CMOS circuit can cause oscillation or sequential behavior. We also analyze and compare the factors affecting the probabilities for an interconnect open and a feedback bridging fault to oscillate or display sequential behavior.
1
Introduction
Opens are one of the most common types of defects that occur during an IC manufacturing process [1]. Opens fall into different categories depending on their location in a digital CMOS circuit: An open can occur inside a CMOS cell affecting transistor drain and source connections [2, 3, 4, 5], at the gate input of a single transistor [6, 7], or on the interconnect separating a set of logic-gate inputs from their drivers, which allows the input voltage to float. In today’s CMOS ICs with five or more metal layers, interconnect wiring seems to be the most likely place for an open occur. Vias are especially susceptible to opens, and the number of vias is exceeding the number of transistors in some microprocessor designs [8]. We call the fault created by an open in the interconnect wiring an interconnect open. In this paper we show that an interconnect open can create capacitive feedback paths in a CMOS circuit, thus causing oscillation and sequential behavior. We also show under what conditions this previously unreported phenomenon will occur. Capacitive coupling as low as 1 femto-farad between signal lines can activate the feedback path as we demonstrate in Section 2.1. Since this is the first time this phenomenon is reported for opens, there is no previous published work for direct comparison. Knowing the cause and
necessary conditions for oscillation and added state (1) provides the limits to simpler models of interconnect opens, (2) may lead to more accurate fault grading of interconnect opens, (3) helps in the development of a more effective testing strategy, and (4) may allow this phenomenon to eventually be considered in test pattern generation. In this paper we also discuss, for comparison purposes, the conditions for an interconnect open and a bridging fault to display oscillatory or sequential behavior. Even though the examples in this paper use gates from a standard cell library, an interconnect open can also cause oscillation and sequential behavior in custom designs that use fully complementary static CMOS.
2
Oscillations due to Interconnect Opens
Wire-to-wire and Miller capacitances to the floating wire created by an interconnect open are the two types of feedback capacitances that can cause an interconnect open to oscillate. We discuss them in the following.
2.1
Feedback via Wire-to-Wire Capacitance
Consider the circuit in Figure 1. Node f loat is floating due to an interconnect open defect. CVDD represents the total capacitance between f loat and all neighboring nodes that are at VDD (excluding the Miller capacitances). These neighboring nodes include other signal wires at VDD , power wires carrying VDD , and n-wells that are tied to VDD . Similarly, CGND represents the total capacitance between f loat and all neighboring nodes that are at GND (excluding the Miller capacitances). These nodes include signal and power wires at GND, and the p-substrate.
sum of cap.’s to logic-1 wires and VDD interconnect open X
CVDD
Cwire-to-wire
float CGND
q Cw
S 1 -> 0
out Cw
Cw
sum of cap.’s to logic-0 wires and GND Figure 1: Circuit to demonstrate oscillation due to a wire-to-wire capacitance VDD
3.2 q float 2.8
float
VOLTAGE (V)
2.4
2
1.6
GND 1.2
Figure 3: Miller capacitances in an inverter. 800m
400m
0 0
2
4
6
8
10
12
14 16 18 (nanoseconds)
Figure 2: HSPICE result for the circuit in Figure 1 Cwire to wire represents the capacitance between the wires q and f loat, and finally CW represents the total wiring capacitance for each wire labeled with CW . Note that Cwire to wire is the only feedback capacitance in the example of Figure 1. Let’s now assign some values to these capacitances. In order to come up with realistic values, we used the MAGIC technology file available from MOSIS [9] for the HP 0.6µ fabrication process. We used 20fF for each CW , which corresponds to a 153µ long minimum width metal-1 wire over substrate. For comparison, the cell height in the MCNC cell library is 17.4µ in this process. We used 12fF for CGN D , 8fF for CVDD , and 1fF for Cwire to wire . A 1fF capacitance between two parallel metal-1 wires separated by 0.9µ corresponds to 24µ of metal-1 length. This
length decreases to 21µ for metal-2 and 15µ for the metal-3 layer. With a quick glance at the layout of any ISCAS85 circuit, it is easy to find many wires running in parallel for more than 75µ. We simulated the circuit in Figure 1 using the MCNC cell library with HSPICE with VDD = 3.3V, and using the BSIM parameters for the HP 0.6µ process from MOSIS [9]. The HSPICE results are shown in Figure 2. We started with all the nodes at 0V, and powered up the circuit during the first 1ns, that is, VDD went from 0V to 3.3V. At 3ns, signal S in Figure 1 went from 3.3V to 0V in 1ns. This formed an inverting path from f loat to q, and node q started oscillating as shown with the solid line in Figure 2 due to the electrical feedback created by Cwire to wire . Note that this circuit would never oscillate if it did not have the interconnect open or any other defect. The voltage around which f loat will oscillate is determined by the values of CVDD , CGN D , and the Miller capacitances [2] in the inverter driven by f loat, as shown in Figure 3. Given these capacitances, the size of Cwire to wire determines the ∆Vf loat /∆Vq ratio. If Cwire to wire is not large enough, oscilla-
OAI22 tion will not occur. Since the gate/source and the gate/drain capacitances for the inverter in Figure 3, b1 = 1 a1 = 0 also referred to as the Miller capacitances by Konuk et al. [2], are non-linear, and the voltage at the output of the inverter has a non-linear relationship to its input, we used HSPICE simulation to see the effects q float b2 of these Miller capacitances. Simulating the circuit in Figure 3 shows that f loat acquires 1.65V with VDD = b1 = 1 3.3V for the i1s inverter in the MCNC library, which is the inverter type used in Figure 1. In general, the a1 = 0 floating input of any gate will be forced to a value S2 a2 around VDD /2 by the Miller capacitances of the pand the n-channel transistors driven by the floating input1 , when the gate output is sensitized to this input. Figure 5: Miller capacitances to node f loat in FigIn Figure 2, the f loat oscillates between 1.50V and ure 4 1.57V. This 0.07V swing in f loat is sufficient for q to oscillate as the total gain of the path from f loat to q is high enough within the voltage range f loat 2.2 Feedback via Miller Capacitance is moving. If the voltage on f loat was centered at We will now show another mechanism that can 1.00V, then the total gain of the inverting path might make an interconnect open oscillate. Consider the cirnot have been sufficient for an oscillation with f loat cuit in Figure 4, which is obtained by removing the changing only 0.07V. Given the transistor sizes in the Cwire to wire in Figure 1 and replacing the inverter i1s inverter, CVDD and CGN D determine where the that drives node q with an OAI22 (Or-And-Invert) voltage of f loat will be centered. gate from the MCNC library. Cwire to wire was reCVDD CGND Cwire
to wire,min
10fF 10fF 6.5fF
Table 1: Minimum Cwire in Figure 1
9fF 11fF 4.0fF to wire
8fF 12fF 1.0fF
7fF 13fF 3.0fF
6fF 14fF 5.5fF
values for oscillation
Assuming that CVDD + CGN D = 20fF, we constructed Table 1 with HSPICE simulations, where Cwire to wire,min is the minimum capacitance between q and f loat in increments of 0.5fF such that the circuit will still oscillate. Note that as Cwire to wire increases, the ∆Vf loat /∆Vq ratio will also increase. We define oscillation as the case where the swing at out’s voltage exceeds the swing at f loat’s voltage. Among the five data points in Table 1, CVDD = 8fF and CGN D = 12fF is the case where the gain in the inverting path is the maximum; thus, even 1fF for Cwire to wire is sufficient for an oscillation as we showed earlier. Note that Cwire to wire,min needs to be larger as we move away from the 8fF-12fF point in either direction, as the inverting path gain gets smaller. 1 Assuming fully complimentary CMOS gates with each input driving one p- and one n-channel transistor.
sponsible for the feedback loop in Figure 1 between q and f loat. In Figure 4, however, the feedback from q to f loat is created by the Miller capacitances of the transistors inside the OAI22 gate. These Miller capacitances are shown in Figure 5, where they are connected with dotted lines to emphasize that they are not additionally inserted into the circuit, but they are part of every CMOS transistor. The total Miller capacitance for a transistor can be as large as the total gate-oxide capacitance depending on the region the transistor is operating. The interested reader can refer to the “Introduction to Transcapacitance” and the BSIM “Charge-Based Capacitance Model” sections in the HSPICE User’s Manual [10], and Sheu et al. [11]. The HSPICE simulation result for the circuit in Figure 4 is shown by Figure 6, where we used 8fF, 12fF, and 20fF for CVDD , CGN D , and CW ,respectively, as we did for Figure 2. VDD goes from 0V to 3.3V in the first 1ns, where all nodes in the circuit start from 0V. At 3ns, S1 goes from 3.3V to 0V in 1ns sensitizing the inverting path from f loat to q resulting in an oscillation. Note that this circuit would be a purely combinational circuit, and would never oscillate, if it did not have the interconnect open or any other defect. In order to find the sensitivity of this oscillation to the sizes of the wiring capacitances connected to
OAI22
CVDD interconnect open
X
1 q
C GND
out
0
float Cw
S1 1 -> 0
S2 Cw Cw
Figure 4: Circuit to demonstrate oscillation due to Miller capacitances q float
general. CVDD has two major components; the total capaci2.8 tance from f loat to other signal wires at logic-1 value, and the total capacitance from f loat to the n-wells 2.4 (assuming an n-well technology, such as the HP 0.6µ) and to the power wires. On average, the capacitance 2 to signal wires at logic-1 value will be the same as the capacitance to wires at logic-0, and the capacitance to 1.6 the power wires will be the same as the capacitance 1.2 to the ground wires. However, n-wells will usually occupy less area than the p-substrate. Therefore, in 800m general it is reasonable to expect that CVDD will be smaller than CGN D on average, but close to it, which 400m is exactly the oscillation requirement we discussed in the preceding paragraph as illustrated by Table 2. 0 2 4 6 8 10 12 14 16 18 0 The last row in Table 2 requires a very narrow (nanoseconds) range for CVDD , but 400fF corresponds to a very Figure 6: HSPICE result for the circuit in Figure 4 long wire in the HP 0.6µ technology, which would be a more than 3mm long metal-1 wire over substrate. In general, oscillation due to Miller feedback capacitances is more likely when (CVDD + CGN D ) is small f loat, we performed HSPICE simulations to conas also shown by Table 2, because the Miller feedback struct Table 2. CVDD ,min and CVDD ,max are the minicapacitance sizes are fixed by the transistor sizes. mum and maximum capacitance values for CVDD such that the circuit in Figure 4 still oscillates. We define oscillation as the case where the swing at out’s 3 Sequential Behavior due to voltage exceeds the swing at f loat’s voltage. The Interconnect Opens last two columns in Table 2 show that CVDD needs to be smaller than CGN D for an oscillation, but not too small. The last row shows that CVDD to In this section we show how an interconnect open can CVDD +CGN D ratio needs to be 0.46 as CVDD +CGN D cause sequential behavior. As in the case of oscillagets very large. This implies that the voltage around tion, the two types of feedback capacitances responsiwhich f loat needs to oscillate is 0.46 · VDD . This ble for sequential behavior are wire-to-wire and Miller is probably mostly true independent of which MCNC capacitances to the floating node created by the open. gates are used, because 1.05V and 1.90V are the maximum logic-0 and the minimum logic-1 voltages, re- 3.1 Feedback via Wire-to-Wire Caspectively, for the MCNC cell library using the HP pacitance 0.6µ BSIM parameters. Note that the mid-point between 1.05V and 1.90V is 1.47V, which is equal to Consider the circuit in Figure 7. We will now describe 0.45 · VDD . Also, gates from other cell libraries are why this circuit acts like a latch because of the interlikely to have this property, because n-channel tran- connect open. Let Qs denote the electrical charge on sistors conduct better than the p-channel ones, in the f loat side plate of Cwire to wire plus the electri-
VOLTAGE (V)
3.2
CVDD + CGN D 20fF 30fF 40fF 50fF 60fF 400fF
CVDD ,min 2.0fF 6.5fF 11.5fF 16.0fF 20.5fF 180.0fF
CVDD ,max 10.0fF 14.5fF 19.0fF 23.5fF 28.0fF 184.5fF
CVDD ,min CVDD +CGN D
CVDD ,max CVDD +CGN D
0.10 0.22 0.29 0.32 0.33 0.45
0.50 0.48 0.47 0.47 0.47 0.46
Table 2: The capacitance ranges for oscillation in Figure 4
interconnect open
X
Vq (V)
Qs (F)
Cwire-to-wire
3.2
CVDD
20f
float
10f
Q s = 54.6fC - 30fF * Vfloat
3
q
2.8
2 1
2.4
0
CGND
a
0
-10f
b
2
c 1.6
-20f
Figure 7: Circuit to demonstrate sequential behavior due to a wire-to-wire capacitance
-30f
1.2
Q s = 31.8fC - 30fF * Vfloat -40f
800m
Vq cal charge on the transistor gates of the NOR gate -50f connected to f loat. In order to find the relationship non-floating Qs 400m between Qs and the voltage on the input, we varied Vf loat from 0V to VDD by driving node f loat in -60f 0 500m 1 1.5 2 2.5 3 V HSPICE, and obtained the non-floating Qs curve 0 float shown in Figure 8 using Cwire to wire = 10fF. Note the sudden fall in the non-floating Qs around Vf loat = Figure 8: Illustration of one metastable and two sta1.7V due to the capacitive feedback from q to f loat. ble states When we add the assumption that node f loat is actually floating, then the following equation needs to the metastability in a latch [14]. Therefore, point b be satisfied, also: is not a real solution. Points a and c are stable states. Figure 8 illusQinit = Qs + CGN D · Vf loat + CVDD · (Vf loat − VDD ) trates Vq (the voltage on node q) with a dashed line, where Qinit is the trapped charge on f loat during which shows that the Vf loat values corresponding to the fabrication process [12] [13]. The above equation points a and c are interpreted as logic-0 (Vq = 0V ) and logic-1 (Vq = 3.3V ), respectively. The straight can be rewritten as follows: line for Equation 1 moves up as CVDD increases, and moves down as it decreases, with (CVDD +CGN D ) and Qs = Qinit +CVDD ·VDD −(CVDD +CGN D )·Vf loat (1) Qinit being constants for a given open. Recall that CVDD represents the total capacitance between f loat In Figure 8, there are three straight dotted lines and all neighboring nodes that are at VDD , which is corresponding to Equation 1 with three different determined by the vector applied to the circuit for (CVDD · VDD ) values using CVDD + CGN D = 30fF and a given open, and that is why we will refer to this Qinit = 0. Note that line 2 intersects the non-floating straight line as the vector line. Also, the value of Qs at three points, which represent three different so- Qinit , which is determined by the fabrication process lutions. Point b corresponds to a metastable state, for a given open, biases the vector line. because even the slightest disturbance on Vf loat will If the vector line moves down past line 1 or up past kick the solution point to either a or c, very much like line 3 in Figure 8, then it intersects the non-floating
Qs at a single point. Between lines 1 and 3, the real solution is determined by the previous value of Vf loat . Vf loat will remain at logic-0 if the vector line moves below line 1 at least once, and stays below line 3. Similarly, it will remain at logic-1 if the vector line moves above line 3 at least once, and stays above line 1. Therefore, the latch behavior is observed only in the region between lines 1 and 3. CVDD is 9.6fF and 16.5fF for lines 1 and 3, respectively. Recall that we used CVDD +CGN D = 30fF, and CVDD will be smaller than CGN D but close to it on average as we discussed in Section 2.2. Therefore, it is reasonable to expect that the vector line will be within lines 1 and 3 in a significant number of vectors applied to the circuit. In general, for any interconnect open as shown in Figure 7 with an even number of inverting gates from f loat to q, the corresponding curves will look like the ones in Figure 8. If we assume a gain of 10 for a single inverting gate, then the cascaded gain for even number of inverting gates will be 100, 10000, etc. Therefore, Vq will make a jump from 0V to VDD with ∆Vf loat = VDD /(cascaded gain) at a critical Vf loat value determined by the type of gate driven by the f loat. This quick jump in Vq is responsible for the sudden drop in the non-floating Qs , which also marks the transition from logic-0 to logic-1. The size of Cwire to wire together with the transistor sizes connected to the f loat determines the amount of drop in the non-floating Qs . Equation 1 shows that the slope of the vector line is -(CVDD +CGN D ), which is a constant for a given interconnect open. In order for the vector line to intersect the non-floating Qs always at a single point, it must be steeper than the rate of fall in the non-floating Qs . In our example in Figure 8, this would require (CVDD +CGN D ) to be larger than 600fF, which corresponds to a metal-1 wire over substrate with a length of over 4.5mm, which is a very long wire. Therefore, as long as (CVDD + CGN D ) is not extremely large and Cwire to wire is not extremely small, the vector line will intersect the non-floating Qs at three points for a range of CVDD , where one point is a metastable state and the other two are for logic-0 and logic-1.
3.2
Feedback via Miller Capacitance
The feedback we described in the preceding subsection was due to a wire-to-wire capacitance from output to input. We will now show that the same capacitive feedback can occur via the transistor gate-oxide capacitances, more specifically, the Miller feedback capacitances. These two mechanisms were also shown to be responsible for the oscillatory behavior in Sec-
XOR
interC connect VDD open float X
q
C GND 0
Figure 9: Circuit to demonstrate sequential behavior due to Miller capacitances tions 2.1 and 2.2. Consider an XOR gate with one input floating due to an interconnect open, and the other input at logic-0, as shown in Figure 9. The noninverting path from f loat to q through the NOR gate inside the XOR gate is analogous to the non-inverting path in Figure 7. The Miller capacitances connecting q to f loat inside the XOR gate form a feedback loop, the same way Cwire to wire does in Figure 7. In this case Qs is simply the total electrical charge on the floating input of the XOR gate. Figure 10 shows the non-floating Qs together with Vq as computed by HSPICE. Note that these curves are very much like the ones in Figure 8. Therefore, this XOR gate with a floating input displays a sequential behavior just as the circuit in Figure 7 does. In Table 3 we computed the range of CVDD for different (CVDD + CGN D ) values such that this XOR gate displays sequential behavior, that is, the vector line intersects the non-floating Qs at three points, one being metastable and the other two being logic-0 and logic-1. Interestingly, the numbers in Table 3 are very close to the ones in Table 2. Standard cell layouts usually have vias over them to connect signal wires to their inputs and outputs, and vias are particularly susceptible to opens. We removed one of the input vias for the XOR gate, and extracted all its capacitances using a 0.8µ MAGIC technology file, which had the most detailed extraction information we could find. The floating input had some wire-to-wire capacitance to the output of the XOR gate and to the output of the NOR gate inside the XOR. We included these capacitances in our Qs computation using HSPICE. (CVDD + CGN D ) was 9.1fF with a 5.1fF capacitance to the substrate and the GND line and a 1.9fF capacitance to the n-well and the VDD line. So, the minimum and max-
CVDD + CGN D 10fF 20fF 30fF 40fF
CVDD ,min 0.0fF 2.2fF 6.6fF 11.0fF
CVDD ,max 6.0fF 10.2fF 14.4fF 18.6fF
CVDD ,min CVDD +CGN D
CVDD ,max CVDD +CGN D
0.00 0.11 0.22 0.27
0.60 0.51 0.48 0.46
Table 3: Capacitance ranges for sequential behavior in Figure 9
Symbol
Vq (V)
Qs (F)
3.2
30f
Vq 2.8 20f
2.4
10f 2
0 1.6
1.2
-10f
non-floating Qs (charge on the XOR gate input)
800m
-20f
400m
-30f
0
500m
1
1.5
2
2.5
3
Vfloat
Figure 10: Illustration of similarity to the curves in Figure 8 imum possible CVDD values were 1.9fF and 9.1 - 5.1 = 4.0fF, which correspond to vector lines that intersect the non-floating Qs curve at three points. Therefore, this floating input XOR gate will display sequential behavior with any vector applied that makes its faultfree input logic-0 as shown in Figure 9. We repeated the same for the other input of the XOR gate, and found the same result. To give an idea of how often XOR or XNOR gates might be used; 0% to 57% of all the gates in the ISCAS85 layouts are XOR or XNOR gates depending on the circuit.
4
Feedback Activation
In this section we discuss the factors affecting the probabilities for a feedback bridging fault and an interconnect open to display feedback behavior, where we define feedback behavior to mean either oscillation or sequential behavior. Additional information on the oscillation frequency and amplitude, and
IDDQ testability of feedback bridging faults is given by [15, 16, 17, 18]. For a feedback bridging fault, we need to use the concepts of back gate, back wire, front gate, and front wire [19], which are depicted in the example of Figure 12. In order for a feedback bridging fault to display feedback behavior, at least the combinational path from the back wire to an input of the front gate needs to be sensitized. We call this condition partial sensitization. If the path from the back wire to the front wire is sensitized in the fault-free circuit, we call this condition full sensitization. Similarly, for an interconnect open to display feedback behavior, the combinational path from its floating wire A to at least one other wire B needs to be sensitized, where there is a wire-to-wire or a Miller feedback capacitance between A and B.
4.1
Feedback Activation for Shorts
Since it is not as easy to see how feedback behavior can occur with partial sensitization as it is with full sensitization, we will now describe an example oscillation with partial sensitization. Assume that the side input C of the NAND gate in Figure 11 is 0, and the path through the combinational logic block is sensitized; thus partial sensitization. Also, assume that there are even number of inversions from the back wire to the input of the front gate, and A = 1, B = 0 for the back gate. When the on-path input of the front gate is 1, let’s assume that the back gate wins the fight, thus the back wire becomes logic-0. When this logic-0 arrives at the on-path input of the front gate, it turns one more p-channel transistor on, which, we assume, will make the front gate win the fight this time. So, back wire becomes logic-1, which propagates to the on-path input of the front gate; thus oscillation.
More Current Paths in the Back Gate Here we assume that the applied vector has created a full sensitization condition. If the back gate wins the drive fight against the front gate, then no feedback behavior will be observed. That is, the front gate
feedback bridging fault A
C
B
X X
A
B
combinational logic C
Figure 11: Circuit to demonstrate more current paths in the back gate. must win for feedback behavior to occur when full sensitization is achieved. Since the path from the back wire to the front wire is sensitized, the output of the front gate must be also sensitized to its input on this path. Assuming that this input goes to one nchannel and one p-channel transistor inside the front gate, then there is only one current path from VDD to the front wire or from the front wire to GND inside the front gate2 . On the other hand, there might be more than one current path from VDD to the back wire or from the back wire to the GND inside the back gate. For example, in Figure 11 when A = B = 1, two current paths exist through the n-channel transistors, in which case the back gate is most likely to win. The side input C of the front gate in Figure 11 must be 1 because of the full sensitization condition. In order to compute the probability of a front gate winning, let’s make the following assumptions: 1. 75% of the gates used in a chip can have multiple current paths depending on the gate inputs; unlike an inverter, which can have only one current path. 2. The back gate wins when it has more than one current path. 3. Given a gate that can have multiple current paths, the probability for an input combination that will activate multiple current paths is 25%. For instance, the back gate in Figure 11 will have multiple current paths only when A = B = 1;
It follows from these assumptions that the probability of a front gate winning is 13/32 = 41%. This probability is actually smaller due to the reasons we describe in the following, which affect assumption 4 above.
Degraded Voltage on the Back Wire Here we assume either a partial or full sensitization condition. Due to the drive fight between the back and the front gates, the back wire cannot have a rail voltage but an intermediate value between VDD and GND. If the logic gate(s) from the back wire to the input of the front gate cannot pull this intermediate voltage to a rail value, then the drive strength of the front gate will be diminished, which decreases its chances to win the drive fight against the back gate; thus, diminishing the chances for feedback behavior. As an example consider the feedback bridging fault in Figure 12. The HSPICE simulation result with Rshort = 0 is shown in Figure 13, where VDD and S went from 0V to 3.3V during the first 1ns, and S went to 0V at 4ns. The degraded voltage at qback causes the voltage on q2 to be 3.1V instead of 3.3V. This decreases the drive strength of the front gate, and the back gate wins the fight, resulting in no oscillation. When we insert two inverters between the NOR gate and the front gate in Figure 12, only then the circuit starts oscillating. In order to verify that sequential behavior is also affected by degraded voltage on qback , we removed the inverter acting as the front gate in Figure 12, and made the output of the NOR gate qf ront . The HSPICE simulation with Rshort = 0 showed that qf ront goes logic-0 to logic-1 after S switches from 1 to 0, which means that the NOR gate cannot win the drive fight against the back gate due to the inability of one inverter to pull the degraded back wire voltage to a rail; thus, no sequential behavior is observed. When we insert an inverter between the NOR gate and the front gate in Figure 12, only then qf ront stays at logic-0 after S switches from 1 to 0, which means that the circuit is now acting like a latch.
Bridging Resistance
Here again we assume either a partial or full sensitiza4. The probability of the front gate winning is 50% tion condition. So far we assumed the bridging resiswhen there is a single current path both in the tance to be zero, but Rodriguez-Montanes et al. [20] front and back gates. Thus, we implicitly assume showed that most of the metal bridging resistances that the bridging fault resistance is zero. fall into the range from 0Ω to 1000Ω in an exper2 Unless multiple paths are sensitized from the back wire to imental study. As the bridging resistance increases the front wire, which is unlikely. the voltage on the back wire gets closer to what the
R short
VOLTAGE (V)
nodes that are at logic-0 gives CGN D . Capacitances from dependent nodes to the floating wire form the back gate feedback capacitances. front gate q1 q2 X Dependent nodes become most sensitive to the 0 X q_back S floating wire voltage when the floating wire voltage q_front 1 -> 0 is around VDD /2. For the examples corresponding to Tables 2 and 3, 0.45*VDD on the floating wire creFigure 12: Circuit to show the effects of degraded ates the most sensitivity. A signal wire may cross voltage and resistive short several other signal wires that run perpendicularly on the metal layer below or above, creating a lot of Symbol D0:A0:q_back 3.2 D0:A0:q1 D0:A0:v(q2 very small capacitances to it. If we assume N such crossings between the floating wire and other signal 2.8 wires that are independent of the floating wire voltq2 q1 age, a 0.5 probability for each such signal wire to be 2.4 q_back logic-1, and a normal distribution for the number of 2 wires at logic-1 among the N signal wires, then the probability P (x) that x wires are at logic-1 is given 1.6 by the following [21]: r 1.2 2 2 · e−2·(x−N/2) /N P (x) = N · π 800m 400m
0 0
2n
4n
6n
8n
10n 12n 14n 16n 18n (nanoseconds)
Figure 13: HSPICE results for the circuit in Figure 12 back gate is driving; thus reducing the chances for the front gate to win the drive fight for the back wire. As we explained above, the circuit in Figure 12 with Rshort = 0 starts oscillating only when we insert two more inverters. However, it stops oscillating when Rshort ≥ 450Ω. Similarly, we showed that the same circuit with Rshort = 0 displays sequential behavior only when we insert an additional inverter. However, the sequential behavior disappears when Rshort ≥ 427Ω. According to Rodriguez-Montanes et al. [20], 31% of the bridges have a resistance greater than 500Ω.
4.2
Feedback Activation for Opens
Given a vector applied to the combinational circuit inputs, all the nodes that have a wire-to-wire or a Miller capacitance to the floating wire that is created by an interconnect open fall into two classes: nodes whose voltages depend on, and nodes whose voltages are independent of the floating wire voltage. Adding up the wire-to-wire capacitances to the independent nodes that are at logic-1 gives CVDD , and adding up the wire-to-wire capacitances to the independent
When N = 10, the probability that 4, 5, or 6 wires are at logic-1 is 0.67. When N = 20, the probability that the number of logic-1 wires is in the range from 8 to 12 is 0.74. When N = 30, the same probability is 0.80 for the range from 12 to 18. Therefore, neighboring signal wires tend to bias the floating wire around VDD /2 when there are many of them with small capacitances. In contrast to bridging faults, note that there is no requirement for a gate to outdrive another gate in case of opens to display feedback behavior, because an interconnect open does not cause any drive fight, at all. Once the floating wire voltage is biased around VDD /2, then the feedback capacitance(s) need(s) to be large enough to cause feedback behavior. The size of a feedback capacitance is very much layout dependent, but wire-to-wire capacitances are growing in importance compared to other capacitances in a layout, because the number of metal layers is increasing, and metal lines on the same layer are getting closer to each other as the smallest feature size decreases. With this trend, the probability of feedback behavior from an interconnect open will increase. The fact that a feedback bridging fault between wire A and wire B corresponds to a feedback capacitance from B to A when wire A is floating due to an open can be exploited to perform more rigorous analysis comparing the probabilities of shorts and opens causing feedback behavior. We leave this analysis as a future work item. As a related reference, Maxwell et al. [22] used total wiring capacitance values esti-
mating the likelihoods of bridging faults to come up with a weighted stuck-at fault coverage measure.
[7] M. Renovell and G. Cambon. Electrical analysis and modeling of floating-gate fault. IEEE Transactions on Computer-Aided Design, pages 1450–1458, November 1992.
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[8] K.M. Thompson. Intel and the myths of test. In The Keynote Address of International Test Conference, October 1995.
Summary
This paper describes how interconnect opens, due to feedback capacitive coupling, may cause oscillation or sequential behavior, and provides a basis for developing an accurate fault simulator or any other test tool regarding interconnect opens. The capacitive feedback can come from either wireto-wire capacitance of as little as 1 femtofarad or from Miller feedback capacitances from within a logic-gate. The range of initial voltages on the floating node to allow oscillation or additional state to occur is in the vicinity of VDD /2, which is likely to be the voltage the node is charged to due to Miller capacitances during circuit power up. The analysis we presented for the necessary conditions for a feedback bridging fault and an interconnect open to display feedback behavior does not clearly point out which one is more likely. A more rigorous analysis or experiments are necessary to determine the relative likelihoods.
Acknowledgments The first author acknowledges Doug Sojourner of HP for his support and valuable technical input. We also acknowledge the support from SRC contract 96-DJ315 and NSF grant MIP-9158491.
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