Output Probability Density Functions of Logic Circuits - IEEE Xplore
Output Probability Density Functions of Logic Circuits: Modeling and Fault-Tolerance Evaluation Milos Stanisavljevic, Alexandre Schmid and Yusuf Leblebici Microelectronic Systems Laboratory, EPFL, CH-1015 Lausanne, Switzerland {milos.stanisavljevic, alexandre.schmid, yusuf.leblebici}@epfl.ch Abstract—The precise evaluation of the reliability of logic circuits has a significant importance in highly-defective and future nanotechnologies. It allows efficient comparison of faulttolerance techniques, and enables designs improvement with respect to their reliability figure. This paper presents a novel, accurate and scalable method for modeling the output probability density functions (PDFs) of logic circuits. Our method combines probability theory with concepts from logic synthesis and testing. The PDFs are modeled using the acquired circuit output probability of failure and PDFs of gates in the last two layers of the output cone. Unlike the existing output PDF modeling techniques, the proposed method is directly applicable to standard CMOS design. Simulation results of benchmark circuits demonstrate the accuracy of the method. Several potential applications of the proposed technique include the analysis of averaging (analog) fault-tolerant techniques, fine-grained redundancy insertion, and reliability-driven design optimization.
I. I NTRODUCTION CMOS scaling has been a principle which has provided the semiconductor industry with historically unprecedented gains in productivity and performance. Scaling has been the trend for decades and even though it has faced many hurdles, clever engineering solutions, new materials and new device architectures have thus far broken through such barriers enabling scaling to continue with constant or slightly slower pace in the next ten years. Due to the foreseeable limitations of CMOS technology and the promising results of various new devices operating at nanometer level, there is a worldwide attention to the research and development of new electronic devices that could be the base of this future technology. Future systems based on non-CMOS nanodevices are expected to suffer from low reliability due to both permanent and transient errors [1], [2]. Permanent error rate will increase due to constraints imposed by fabrication technologies [3]. Transient error rate will increase due to nondeterministic parasitic effects such as background charge, which may disrupt correct operation of devices both in the time and space domain in a random way. An accurate calculation (estimation) of the reliability of nano-architectures through simulations is essential for future designs. It would allow not only verifying the theoretical results but could also help in designing or selecting the most suitable (nano)architecture that satisfies all delay, power, area, and reliability requirements. As a common denominator, most of statistical methods enabling the reliability evaluation use a single probability value to describe the fault-tolerance of each gate in a circuit.
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This value is the probability of failure of a device (or a logic gate). However, when analyzing fault-tolerant techniques like averaging, which inherently use analog signals, a wide range of output probability values is required. In this case, each output of a logic circuit can be described in a statistical manner using probability density functions (PDFs). PDFs can be constructed by analyzing the distribution of different faults in the given circuit, as well as the impact of every single fault on the circuit output. PDFs can also be obtained using a Monte Carlo (MC) simulator, to acquire output values on a large sample of different fault patterns. PDFs of future nano-devices can be modeled using Gibbs distribution and the approach described in [4]. This work presents a novel method for modeling output PDFs of an arbitrary logic circuit. A fast and accurate reliability evaluation tool is necessary in order to acquire output PDFs of a logic unit of an arbitrary size. Analytical and experimental methods (discreteevent simulation) are directly applicable to circuit output PDFs generation. An example of discrete-event simulation is a Monte Carlo framework which uses fault injection and simulation. Although parallelizable, MC tools are still not efficient to be used for large circuits. Analytical methods enabling the reliability analysis are applicable to very simple structures such as 2-input and 3input gates, and regular fabrics [5]. Despite the fact that they can be applied to large multi-level circuits, a significant loss in accuracy is observed due to simplified assumptions and compositional rules. Numerical methods enabling reliability evaluation use a single probability value to describe the fault-tolerance of each gate in the circuit. Moreover, the output result of the evaluation is a set of probability values for some input vector sets. Recent advances in reliability analysis presented such as probabilistic transfer matrices (PTMs) [6] and Bayesian networks [7] require significant runtimes for small benchmarks. Other works like [8] do not satisfy accuracy requirements. Two most recent approaches, single-pass reliability analysis [9] and signal probability analysis [10] satisfy accuracy and scalability requirements. The single-pass reliability analysis tool offers better performance in terms of speed and scalability, with lower memory requirement. It implements a fast, accurate and scalable algorithm for reliability analysis. The original algorithm is intended for transient errors which can be modeled as a symmetrical flip of a gate output, with the same probability of error. The tool provides the probability of error for a 0 → 1
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(logic-0 error) or 1 → 0 flip (logic-1 error) at the given output of the circuit and accounts for reconvergent fanout. The method enabling modeling output PDFs uses these probability of error values and PDFs of gates in the last two layers of the output cone to model the output PDFs by propagation of intermediate PDFs. The method can be equally applied to transient and permanent errors. Results are verified using the MC tool that performs SPICE-level simulations using fault injection and transistor fault models for permanent errors as presented in [11]. Therefore, we modified the single-pass reliability analysis tool to include permanent errors, as well. This paper is organized as follows. Section II presents, in brief, the existing single-pass reliability analysis tool and its modifications to account for permanent errors. The circuit output PDFs modeling method is presented in Section III. The results and the accuracy of the method are demonstrated in Section IV. Finally, the conclusion is given in Section V. II. S INGLE -PASS R ELIABILITY A NALYSIS T OOL In the original algorithm [9], gates are topologically sorted and processed in a single pass from the inputs to the outputs. Topological sorting ensures that before a gate is processed, the effects of multiple gate failures in the fanin cone of the gate are computed and stored at the inputs of the gate. At the core of this algorithm is the observation that an error at the output of any gate results from the cumulative effect of a local error component attributed to the probability of failure of the observed gate, and a propagated error component attributed to the failure of gates in its fanin cone. The following two events are important: • 0 → 1, which marks an event where the output of the gate is at logic-1, whereas its fault-free value is logic-0 (referred also as worst-case logic-0 error); • accordingly, 1 → 0, which marks an event where the output of the gate is at logic-0, whereas its fault-free value is logic-1 (referred also as worst-case logic-1 error). In this paper the following symbol convention is used: • the arbitrary gate output is marked as g; • the total error probability at g for 0 → 1 and 1 → 0 events is marked as Pr(g0→1 ) and Pr(g1→0 ), respectively; • the propagation error probability at g (which is defined further in the text) for 0 → 1 and 1 → 0 events is marked as Pp (g0→1 ) and Pp (g1→0 ), respectively; • the single gate error probability for a 0 → 1 and 1 → 0 events are marked as P0 and P1 , respectively; • the joint single gate error probability for a 0 → 1 and 1 → 0 events is marked as P01 . In general, Pr(g0→1 ) = Pr(g1→0 ) for an internal gate, located inside a circuit. Initially, Pr(xi,0→1 ) and Pr(xi,1→0 ) are known for the primary inputs xi of the circuit. In the core computational step of the algorithm, the 0 → 1 and 1 → 0 error components of input vectors at the inputs of a gate are combined to obtain propagation error probability Pp (g0→1 ) and Pp (g1→0 ). These probabilities are then combined with the local gate failure probability to obtain Pr(g0→1 ) and Pr(g1→0 ) at the output of the gate.
The single-pass reliability analysis is performed by recursively applying the core computational step of the algorithm to the gates in a topological order. At the end of the single-pass, Pr(y0→1 ) and Pr(y1→0 ) are obtained for the output y of the circuit. The time complexity of the algorithm is O(n), where n is the number of gates in the circuit. Note that the singlepass reliability analysis gives the exact values of probability of error at the output in the absence of reconvergent fanout. The modification of the original algorithm in order to account for the permanent errors is reflected in the way the propagation error probabilities, Pr(g0→1 ) and Pr(g1→0 ) are calculated. Transient errors (whose effects are observable not longer than one clock period) can affect the output value that corresponds to only one input vector active at that time. Permanent errors on the other hand, are present all the time and affect the output value that corresponds to each input vector. Expression of propagation error probabilities: The 0 → 1 and 1 → 0 input error probability at g are given as Pp (g0→1 ) = Pr(g0→1 | g is fault free) . Pp (g1→0 ) = Pr(g1→0 | g is fault free)
(1)
These are probabilities that the output g would be erroneous (whereas the gate does not fail) for at least one input vector, i.e. probabilities for combined input error vectors. Expressions for the propagation error probabilities and its components, for a 2-input NAND gate with inputs i and j (gate labeled with 3 in Figure 1), are given in Table I. P00 , P01 , P10 and P11 represent the propagation error probability components for input vectors 00, 01, 10 and 11 respectively. P00/01 , P00/10 , P01/10 and P00/01/10 represent the joint propagation error probability components for 00/01, 00/10, 01/10 and 00/01/11 input vectors respectively. Expressions of Pr(g0→1 ) and Pr(g1→0 ): If P0 and P1 are the 0 → 1 and 1 → 0 probabilities of failure of the local gate output g, respectively, the following expressions are obtained: Pr(g0→1 ) = (1 − Pp (g0→1 )) · P0 + Pp (g0→1 ) · (1 − P1 ) . Pr(g1→0 ) = (1 − Pp (g1→0 )) · P1 + Pp (g1→0 ) · (1 − P0 )
(2)
Note that events at inputs i and j are assumed independent which is valid if the gate is not a site of reconvergence of fanout. Since reconvergence causes the two events to be correlated, it is handled separately, in the following Subsection. The single-pass reliability analysis is illustrated for the circuit shown in Figure 1. The gate failure probabilities (P0 and P1 ), and probabilities of the 0 → 1 and 1 → 0 error are
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0.252 0.2376
0.1 0.1
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j
0.1 0.1
0ĺ1 1ĺ0 probability of error
Figure 1. Small circuit example realized with 2-input NAND gates used as a logic unit.
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Table I E XPRESSIONS OF INPUT ERROR COMPONENTS FOR A 2- INPUT NAND Input vector 00 01 10 00/01 00/10 01/10 00/01/10 Total
1 → 0 input error component P00 = Pr(i0→1 ) Pr(j0→1 ) P01 = Pr(i0→1 )(1 − Pr(j1→0 )) P10 = Pr(j0→1 )(1 − Pr(i1→0 )) P00/01 = Pr(i0→1 ) Pr(j0→1 )(1 − Pr(j1→0 )) P00/10 = Pr(i0→1 ) Pr(j0→1 )(1 − Pr(i1→0 )) P00/10 = Pr(i0→1 ) Pr(j0→1 )(1 − Pr(i1→0 ))(1 − Pr(j1→0 )) P00/10/10 = Pr(i0→1 ) Pr(j0→1 )(1 − Pr(i1→0 ))(1 − Pr(j1→0 )) Pp (g1→0 ) = P00 + P01 + P10 − P00/01 − P00/10
Input vector 11 Total
0 → 1 input error component P11 = Pr(i1→0 ) + Pr(j1→0 ) − Pr(i1→0 ) Pr(j1→0 ) Pp (g0→1 ) = P11
indicated for each gate. The gates are numbered in the order in which they are processed. Although the computation has been illustrated for an NAND gate, the computation for NORs, inverters, ANDs, ORs, and XORs are all handled in a similar manner and the corresponding tables have been excluded for brevity. Only 2 and 3-input gates are supported. However, the tool can easily be enhanced to support more input gates by extending propagation probability tables. A. Handling Reconvergent Fanout The single-pass reliability algorithm computes the exact value of the probability of failure of circuits with no reconvergent fanouts. The presence of reconvergent fanout renders the single-pass reliability analysis approximate because the events of a 0 → 1 or 1 → 0 error of the inputs of a gate may not be independent at the point of reconvergence. The theory of correlation coefficients used in signal probability computation [12] is extended to make single-pass reliability analysis more accurate in the presence of reconvergent fanout. The original approach from [9] is followed, but the new way the correlation coefficient are calculated is adopted. Let v and w represent two wires, then four correlation coefficients for this pair are denoted by Cvw , Cvw , Cvw˜ , and Cv˜w˜ , where v, w, v˜, and w ˜ refer to the event of a 0 → 1, 0 → 1, 1 → 0, and 1 → 0 error at v and w respectively. The correlation coefficients must be considered at the gates whose inputs are the site of reconvergence of fanout. At such gates, the events of a 0 → 1 or 1 → 0 error at the inputs are not independent. Thus, the entries in the second column of Table I are weighted by the appropriate correlation coefficient, e.g., Pr(i0→1 )(1 − Pr(j1→0 )) becomes Pr(i0→1 )(1 − Pr(j1→0 )Ci˜j ). Correlation coefficient computation: The correlation coefficient of a pair of wires can be calculated by computing the correlation coefficients of the wires in the fanout source that cause the correlation in the first step, and then propagating these correlation coefficients along the appropriate paths leading to the pair of wires. Note that all four correlation coefficients for two independent wires are equal to 1. The computation of correlation coefficients for the fanout source and the propagation of correlation coefficients at a 2-input
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GATE .
NAND gate are described in the following. Computation at fanout source node: Following the definition of the correlation coefficient, the correlation coefficient for the pair of wires {l, m} with fanout source node i (Figure 2a) is computed as follows: Pr(l0→1 ) = Pr(l0→1 , m0→1 ) = Pr(l0→1 ) Pr(m0→1 )Clm . 1 Clm = Pr(m0→1 )
(3)
C˜lm ˜ ˜ can be computed in a similar manner. C˜ lm and Clm are equal to zero since it is not possible to have a 0 → 1 error on m and a 1 → 0 error on l, or vice-versa.
l i
m
i j k
(a) Figure 2.
l
(b)
Computation/propagation of correlation coefficient.
Propagation at a NAND gate: The propagation of correlation coefficients is illustrated for the NAND gate in Figure 2b. Let i, j, k be three wires whose pairwise correlation coefficients are known. The computation of the correlation coefficients for the pair {l, k} involves the propagation of the correlation coefficients through the NAND gate, using the correlation coefficients for pairs (i, k) and (j, k). Following the definition of the correlation coefficient and the definition of the conditional probability [13]: Clk =
Pr(l1→0 , k0→1 ) Pr(l1→0 |k0→1 ) = . Pr(l1→0 ) Pr(k1→0 ) Pr(l1→0 )
(4)
The expression of Pr(l1→0 |k0→1 ) in terms of the correlation coefficients for pairs of inputs (i, k) and (j, k) is given as: Pr(l1→0 |k0→1 ) = (1 − Pp (l1→0 |k0→1 )) · P0 + Pp (l1→0 |k0→1 ) · P1 and Pp (l1→0 |k0→1 ) = Pr(i0→1 )Cik Pr(j0→1 )Cjk Cij + Pr(i0→1 )Cik (1 − Pr(j1→0 ))C˜jk Ci˜j + Pr(j0→1 )Cjk (1 − Pr(i1→0 ))C˜ik C˜ij + Pr(i0→1 )Cik Pr(j0→1 )Cjk (1 − Pr(j1→0 ))C˜jk Cij + Pr(i0→1 )Cik Pr(j0→1 )Cjk (1 − Pr(i1→0 ))C˜ik Cij
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(5)
The terms in the expression of Pp (l1→0 |k0→1 ) are similar to the terms in the second column of Table I. The difference is that the probability of the 0 → 1 and 1 → 0 errors are multiplied by the appropriate correlation coefficients. The expression for Clk is derived in a similar manner using the lower part of Table I. Expressions for Clk˜ and C˜lk˜ are derived by replacing k with k˜ in expressions for Clk and C˜lk respectively. In comparison with the original algorithm presented in [9], this modified version has the same level of accuracy and slightly improved computational speed. The speed improvement is due to the omission of the weight vector calculation.
The procedure for modeling PDFs for the worst case logic-0 and logic-1 at the output of an arbitrary circuit gate g is presented in the following. The example circuit from Figure 1 is used. If we mark the desired PDFs as hg,max 0 and hg,min 1 , the probability of failure acquired using the single-pass reliability tool is given as
1
hg,max 0 (x)dx and , 0.5 0.5 hg,min 1 (x)dx Pr(g1→0 ) =
(6)
0
since all output values for logic-0 (logic-1) that are higher (lower) than a threshold of 0.5 are assumed as erroneous. Output PDFs are modeled using the two values for the probability of the gate failure from (6) acquired with the single-pass reliability tool and PDFs of individual gates that are close to output in a topological sense. 0 → a marks an event where the output of the gate is at any level that is different from logic-0 and logic-1 (0 < a < 1) when its faultfree value is logic-0. Accordingly, 1 → a marks an event that output of the gate is at any level different from logic-0 and logic-1 (0 < a < 1) when its fault-free value is logic-1. We differentiate four distinctive cases of the propagation error probability at g Pp (g0→1 ) = Pr(g0→1 | Pp (g0→a ) = Pr(g0→a | Pp (g1→0 ) = Pr(g1→0 | Pp (g1→a ) = Pr(g1→a |
is is is is
fault fault fault fault
free) free) . free) free)
(2)
(1)
,
(9)
(1)
where hp,0→a (hp,1→a ) is the PDF at the output of g for the (2) (2) 0 → a (1 → a) event when g is fault-free and hp,0→a (hp,1→a ) is the PDF at the output of g for the 0 → a (1 → a) event when g is faulty. After inserting (9) into (8) hg,max 0 = (1 − Pp (g0→1 ) − Pp (g0→a )) · h,max 0 (1)
+ Pp (g0→1 ) · h,min 1 + Pp (g0→a ) · (1 − P0 ) · hp,0→a + Pp (g0→a ) · P0 · hp,0→a hg,min 1 = (1 − Pp (g1→0 ) − Pp (g1→a )) · h,min 1
, (1)
+ Pp (g1→0 ) · h,max 0 + Pp (g1→a ) · (1 − P1 ) · hp,1→a (2)
+ Pp (g1→a ) · P1 · hp,1→a (10)
where P0 and P1 are probabilities of failure of the local gate output g for logic-0 and logic-1 respectively, as presented at the beginning of Section II. Not all the elements of the sum in (10) have the same impact on hg,max 0 (hg,min 1 ). The impact is determined by probability factors that multiply PDFs on the right-hand side of (10), since the integral of each of these PDFs is equal to one. The probability factors ratio is given as 1 − Pp (g0→1 ) − Pp (g0→a ) Pp (g0→1 ) > > Pp (g0→a ) · (1 − P0 ) Pp (g0→a ) · P0 . 1 − Pp (g1→0 ) − Pp (g1→a ) Pp (g1→0 ) > > Pp (g1→a ) · (1 − P1 ) Pp (g1→a ) · P1 (11)
The smallest propagation factor (the last element on the righthand side of (11)) can be disregarded. After introducing this approximation, (10) becomes hg,max 0 ≈ (1 − Pp (g0→1 ) − Pp (g0→a )) · h,max 0 (1)
+ Pp (g0→1 ) · h,min 1 + Pp (g0→a ) · hp,0→a . ≈ (1 − Pp (g1→0 ) − Pp (g1→a )) · h,min 1
(12)
(1)
+ Pp (g1→0 ) · h,max 0 + Pp (g1→a ) · hp,1→a (7)
If we mark the PDF of the local gate output g for the worst case logic-0 (logic-1) as h,max 0 (h,min 1 ) and hp,0→a (hp,1→a ) the PDF at the output of g for 0 → a (1 → a) propagation error then hg,max 0 and hg,min 1 are expressed as hg,max 0 = (1 − Pp (g0→1 ) − Pp (g0→a )) · h,max 0 + Pp (g0→1 ) · h,min 1 + Pp (g0→a ) · hp,0→a . hg,min 1 = (1 − Pp (g1→0 ) − Pp (g1→a )) · h,min 1 + Pp (g1→0 ) · h,max 0 + Pp (g1→a ) · hp,1→a
(1)
hp,1→a = (1 − P1 ) · hp,1→a + P1 · hp,1→a
hg,min 1 g g g g
(2)
(2)
III. O UTPUT PDF M ODELING
Pr(g0→1 ) =
(1)
hp,0→a = (1 − P0 ) · hp,0→a + P0 · hp,0→a
(8)
hp,0→a and hp,1→a consist of two components; one for the fault-free g and another for the faulty g
(1)
The unknowns in (12) are Pp (g0→a ) · hp,0→a and Pp (g1→a ) · (1) hp,1→a . All other elements can be subsequently derived. To determine the unknowns, we observe the transformation of PDFs at the input of g by the gate transfer function. The transfer function is determined for a fault-free library gate with default (output gate) load. Similarly as in previous Section, the 2-input NAND gate is considered without loosing generality, and the circuit example is depicted in Figure 1. A single input transfer function for a typical 2-input NAND gate is depicted in Figure 3a. In order for the 0 → a (1 → a) event to occur, one input has to be in the region defined as [a , VDD − a ] with fault-free value at logic-1 (logic-0) and another input has to be at logic-1. If we mark the PDFs for the worst case logic-0 and logic-1 at inputs i and j of g as hi,max 0 , hi,min 1 , hj,max 0
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Gate output value [Vdd]
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0 0
1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 2-input NAND output value[Vdd]
(b)
1
(c)
Figure 3. 2-input NAND (a) gate transfer function; (b) PDF for the worst case logic-0 in [a , VDD − a ] region; (c) transformation of PDF from (b) through gate transfer function from (a).
and hj,min 1 , respectively, and the gate g transfer function of the PDF in the region of interest ([a , VDD − a ]) as fT
be omitted. Since Pp (g0→a ) (Pp (g1→a )) is the smallest factor in (12), this approximation is justified. For the same reason, factors Pr(i1→0 ) and Pr(j1→0 ) are omitted from (13). Finally,
(1)
Pp (g0→a ) · hp,0→a = fT (hi,min 1 )(1 − Pr(j1→0 )) + fT (hj,min 1 )(1 − Pr(i1→0 )) (1)
Pp (g1→a ) · hp,1→a = fT (hi,max 0 )(1 − Pr(j1→0 )) + fT (hj,max 0 )(1 − Pr(i1→0 ))
(1)
Pp (g0→a ) · hp,0→a ≈ 2fT (h,min 1 ) .
(13)
hi,max 0 , hi,min 1 , hj,max 0 and hj,min 1 also respect (12). fT is computed numerically using the gate g transfer function. The PDF of the 2-input NAND gate in the region of interest ([a , VDD − a ]) (depicted in green in Figure 3b) ha and its transformation through the transfer function fT (ha ) are given in Figure 3b and 3c, respectively. By increasing voltage gain of the transfer function, the probability values in [a , VDD − a ] region of the transformed PDF - fT (ha ) reduce and already for voltage gain equal to ten can be totally omitted. Taking this fact into consideration, hi,max 0 and hi,min 1 (hj,max 0 and hj,min 1 ) which also comply with (12) can be approximated with h,max 0 and h,min 1 in the region of (1) interest. This approximation means that Pp (g0→a )·hp,0→a and (1) Pp (g1→a ) · hp,1→a only depend on the PDFs of individual gates in the last layer of the fanin cone (outputs i and j in Figure 1), and that propagating factors in these PDFs can
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(1)
Pp (g1→a ) · hp,1→a ≈ 2fT (h,max 0 )
.
(14)
From (14), Pp (g0→a ) and Pp (g1→a ) are expressed as Pp (g0→a ) ≈ Pp (g1→a ) ≈
1
0 1 0
2fT (h,max 0 ) .
(15)
2fT (h,min 1 )
After replacing (12) into (6) and solving for Pp (g0→1 ) and Pp (g1→0 ) the remaining unknown factors from (12) are derived as Pr(g0→1 ) − (1 − Pp (g0→a ))P0 1 − P0 − P1 1 (1) Pp (g0→a ) 0.5 hp,0→a (x)dx − 1 − P0 − P1 . Pr(g1→0 ) − (1 − Pp (g1→a ))P1 Pp (g1→0 ) = 1 − P0 − P1 0.5 (1) Pp (g1→a ) 0 hp,1→a (x)dx − 1 − P0 − P1
Pp (g0→1 ) =
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IV. R ESULTS A set of MATLAB scripts has been developed to automate the described process related to output PDF modeling. The actual calculations implemented in MATLAB are performed on discrete data sets where PDFs are represented with 100 points histograms. The calculations and simulations were run on 2.66-GHz quad core-based system with 4GB of memory. A MC framework performing SPICE-level simulations is used to obtain data for the comparison and the necessary PDFs of the library gates. All possible combinations of single and double permanent faults are injected in each standard library gate in order to generate PDFs, for values of the probability of fault per transistor (pf ) in the range from 0.1% to 20%. 4-bit full adder is used as the main benchmark circuit. This is an area/delay minimized realization of an adder, synthesized in Synopsis using the reduced library set consisting of 2 and 3-input NAND and NOR gates and inverters. The benchmark circuit consists of 39 gates in total. The modeled PDFs for the worst case logic-0 and logic1 at outputs of 4-bit full adder (denoted as “modeled” in the figures) are compared with the equivalent PDFs acquired using MC tool (denoted as “simulated” in the figures). Single, double and triple permanent faults have been injected into the MC framework. The number of MC iterations is set to 3 × 320 000 in order to minimize the error due to sampling. The values of modeled and simulated PDFs for the worst case logic-0 are depicted in Figure 4a and 4b. Likewise, the values of modeled and simulated PDFs for the worst case logic-1 are depicted in Figure 5a and 5b. The applied pf to obtain data depicted in figures is 2%. All values are depicted in 100 bins original histograms (without interpolation). The values of histograms for the output equal to zero and V dd are excluded for better visualization, since they are few orders of magnitude larger than other values in the histogram. The difference between PDFs is not noticeable. The intrinsic property of our method is that the runtime does not depend on the complexity of the circuit once the circuit output probability of failure is acquired. The average runtime of our tool for the benchmark circuit (for different values of pf ), including single pass reliability analysis tool, is under 100ms. In order to compare modeled and simulated PDFs, Pearson’s chi-square test [13] for histogram comparison has been performed. The chi-square statistics calculates the difference between simulated and modeled histogram as X2 =
r (Si − nMi )2 , nMi i=1
(17)
where X 2 is the test statistic that asymptotically approaches a χ2 distribution, Si is the simulated histogram value (acquired directly from MC simulations), Mi is the modeled histogram value (normalized - sum of its values is equal to one), n is number of iterations (only iterations when circuit output was faulty are included) and r is the number of histogram bins (100 in our case). The null-hypothesis is that compared distributions
are identical. This hypothesis can be rejected with significance level α (the rejecting error of the correct null-hypothesis) if and only if X 2 > ε1−α , where ε1−α is 1 − α quantile of the χ2 (r − 1) distribution. Table II shows X 2 values for PDFs of each output of the 4-bit full adder (Sum1 to Sum4 ) for the worst case logic0 and logic-1 and for different values of pf . 1% and 5% quantile values for ε1−α used for comparison are 134.642 and 123.225 respectively. Following the chi-square test results, the hypothesis that modeled and simulated distributions are identical can not be rejected for any significance level and for any of the compared PDFs. All X 2 values are smaller than the value of ε0.95 . X 2 value does not change noticeably for different pf . C HI - SQUARE TEST RESULTS : X 2
Table II
VALUES FOR OUTPUTS OF 4-bit full adder FOR THE WORST CASE LOGIC -0 AND LOGIC -1 AND FOR DIFFERENT VALUES OF pf .
output Sum1 Sum2 Sum3 Sum4
logic-0 logic-1 logic-0 logic-1 logic-0 logic-1 logic-0 logic-1
pf =0.1% X2 35.72 23.30 68.13 51.86 44.24 61.47 55.29 76.43
pf =1% X2 38.49 29.88 62.56 60.06 38.42 65.07 54.57 82.74
pf =5% X2 28.15 19.41 61.98 57.33 41.79 69.51 51.84 74.86
pf =20% X2 34.93 31.23 72.54 50.43 47.62 62.83 59.90 81.03
V. C ONCLUSION The need for EDA tools that offer realistic reliability evaluation and modeling by employing a data collection without over-simplification of the models is becoming more prominent. The precise evaluation of the reliability of logic circuits has a significant importance not only because of the possibility to compare different fault-tolerance techniques, but also because the circuit design in highly-defective and future nanotechnologies can be enhanced. Our novel method has demonstrated that output PDFs of an arbitrary gate are only dependent on PDFs of gates located in the last two stages of the output cone and on output probability of failure. This enables a fast and accurate modeling of output PDFs for logic-0 and logic-1 of an arbitrary circuit. The method has been evaluated in standard CMOS technology for permanent defects modeled with detailed transistor fault models. However, no restriction apply on the method implementation in any fabrication technology including future nanodevices. The method is not restricted to permanent defects and can be applied to transient faults in an equal manner. The accuracy of the method has been demonstrated and confirmed with Pearson’s chi-square test. This method has several potential applications, including the analysis of averaging (analog) fault-tolerant techniques, fine-grained redundancy insertion, and reliability-driven design optimization.
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-3
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(b) 4-bit full-adder worst case logic-1 PDF: (a) modeled; (b) simulated.
R EFERENCES [1] James D. Meindl, Qiang Chen, and Jeffrey A. Davis, “Limits on silicon nanoelectronics for terascale integration”, Science, vol. 293, no. 5537, pp. 2044 – 2049, 2001. [2] G. Bourianoff, “The future of nanocomputing”, Computer, vol. 36, no. 8, pp. 44–53, Aug. 2003. [3] Chenxiang Lin, Yan Liu, Sherri Rinker, and Hao Yan, “DNA tile based self-assembly: Building complex nanoarchitectures”, ChemPhysChem, vol. 7, no. 8, pp. 1641–1647, 2006. [4] R. I. Bahar, J. Chen, and J. Mundy, Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, chapter A probabilistic-based design for nanoscale computation, pp. 133–156, Kluwer Academic Publishers, 2004. [5] J. von Neumann, Automata Studies, chapter Probabilistic logic and the synthesis of reliable organisms from unreliable components, pp. 43–98, Prinston, NJ: Princeton Univ. Press, 1956. [6] S. Krishnaswamy, G. F. Viamontes, I. L. Markov, and J. P. Hayes, “Accurate reliability evaluation and enhancement via probabilistic transfer matrices”, in Proc. Design, Automation and Test in Europe (DATE), 2005, pp. 282–287. [7] T. Rejimon and S. Bhanja, “Scalable probabilistic computing models using Bayesian networks”, in Proc. 48th Midwest Symposium on Circuits and Systems (MWSCAS), 7–10 Aug. 2005, pp. 712–715. [8] E. Taylor, Jie Han, and J. Fortes, “Towards accurate and efficient reliability modeling of nanoelectronic circuits”, in Proc. Sixth IEEE
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4-bit full-adder worst case logic-0 PDF: (a) modeled; (b) simulated.
simulated PDF
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0.4 0.6 Sum4 output value [Vdd]
[9] [10] [11]
[12] [13]
Conference on Nanotechnology (IEEE-NANO), 17–20 June 2006, vol. 1, pp. 395–398. M. R. Choudhury and K. Mohanram, “Reliability analysis of logic circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 3, pp. 392–405, March 2009. D. T. Franco, M. C. Vasconcelosa, L. Navinera, and J.-F. Navinera, “Signal probability for reliability evaluation of logic circuits”, Microelectronics Reliability, vol. 48, no. 8-9, pp. 1586–1591, 2008. M. Stanisavljevic, A. Schmid, and Y. Leblebici, “Fault-tolerance of robust feed-forward architecture using single-ended and differential deepsubmicron circuits under massive defect density”, in Proc. International Joint Conference on Neural Networks (IJCNN), 16–21 July 2006, pp. 2771–2778. S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricco, “Estimate of signal probability in combinational logic networks”, in Proc. 1st European Test Conference, 12–14 April 1989, pp. 132–138. A. Papoulis and S. U. Pillai, Probability, Random Variables and Stohastic Processes, NY: McGraw-Hill, 4th edition, 2002.
2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010)
I. I NTRODUCTION CMOS scaling has been a principle which has provided the semiconductor industry with historically unprecedented gains in productivity and performance. Scaling has been the trend for decades and even though it has faced many hurdles, clever engineering solutions, new materials and new device architectures have thus far broken through such barriers enabling scaling to continue with constant or slightly slower pace in the next ten years. Due to the foreseeable limitations of CMOS technology and the promising results of various new devices operating at nanometer level, there is a worldwide attention to the research and development of new electronic devices that could be the base of this future technology. Future systems based on non-CMOS nanodevices are expected to suffer from low reliability due to both permanent and transient errors [1], [2]. Permanent error rate will increase due to constraints imposed by fabrication technologies [3]. Transient error rate will increase due to nondeterministic parasitic effects such as background charge, which may disrupt correct operation of devices both in the time and space domain in a random way. An accurate calculation (estimation) of the reliability of nano-architectures through simulations is essential for future designs. It would allow not only verifying the theoretical results but could also help in designing or selecting the most suitable (nano)architecture that satisfies all delay, power, area, and reliability requirements. As a common denominator, most of statistical methods enabling the reliability evaluation use a single probability value to describe the fault-tolerance of each gate in a circuit.
c 978-1-4244-6471-5/10/$26.00 2010 IEEE
This value is the probability of failure of a device (or a logic gate). However, when analyzing fault-tolerant techniques like averaging, which inherently use analog signals, a wide range of output probability values is required. In this case, each output of a logic circuit can be described in a statistical manner using probability density functions (PDFs). PDFs can be constructed by analyzing the distribution of different faults in the given circuit, as well as the impact of every single fault on the circuit output. PDFs can also be obtained using a Monte Carlo (MC) simulator, to acquire output values on a large sample of different fault patterns. PDFs of future nano-devices can be modeled using Gibbs distribution and the approach described in [4]. This work presents a novel method for modeling output PDFs of an arbitrary logic circuit. A fast and accurate reliability evaluation tool is necessary in order to acquire output PDFs of a logic unit of an arbitrary size. Analytical and experimental methods (discreteevent simulation) are directly applicable to circuit output PDFs generation. An example of discrete-event simulation is a Monte Carlo framework which uses fault injection and simulation. Although parallelizable, MC tools are still not efficient to be used for large circuits. Analytical methods enabling the reliability analysis are applicable to very simple structures such as 2-input and 3input gates, and regular fabrics [5]. Despite the fact that they can be applied to large multi-level circuits, a significant loss in accuracy is observed due to simplified assumptions and compositional rules. Numerical methods enabling reliability evaluation use a single probability value to describe the fault-tolerance of each gate in the circuit. Moreover, the output result of the evaluation is a set of probability values for some input vector sets. Recent advances in reliability analysis presented such as probabilistic transfer matrices (PTMs) [6] and Bayesian networks [7] require significant runtimes for small benchmarks. Other works like [8] do not satisfy accuracy requirements. Two most recent approaches, single-pass reliability analysis [9] and signal probability analysis [10] satisfy accuracy and scalability requirements. The single-pass reliability analysis tool offers better performance in terms of speed and scalability, with lower memory requirement. It implements a fast, accurate and scalable algorithm for reliability analysis. The original algorithm is intended for transient errors which can be modeled as a symmetrical flip of a gate output, with the same probability of error. The tool provides the probability of error for a 0 → 1
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(logic-0 error) or 1 → 0 flip (logic-1 error) at the given output of the circuit and accounts for reconvergent fanout. The method enabling modeling output PDFs uses these probability of error values and PDFs of gates in the last two layers of the output cone to model the output PDFs by propagation of intermediate PDFs. The method can be equally applied to transient and permanent errors. Results are verified using the MC tool that performs SPICE-level simulations using fault injection and transistor fault models for permanent errors as presented in [11]. Therefore, we modified the single-pass reliability analysis tool to include permanent errors, as well. This paper is organized as follows. Section II presents, in brief, the existing single-pass reliability analysis tool and its modifications to account for permanent errors. The circuit output PDFs modeling method is presented in Section III. The results and the accuracy of the method are demonstrated in Section IV. Finally, the conclusion is given in Section V. II. S INGLE -PASS R ELIABILITY A NALYSIS T OOL In the original algorithm [9], gates are topologically sorted and processed in a single pass from the inputs to the outputs. Topological sorting ensures that before a gate is processed, the effects of multiple gate failures in the fanin cone of the gate are computed and stored at the inputs of the gate. At the core of this algorithm is the observation that an error at the output of any gate results from the cumulative effect of a local error component attributed to the probability of failure of the observed gate, and a propagated error component attributed to the failure of gates in its fanin cone. The following two events are important: • 0 → 1, which marks an event where the output of the gate is at logic-1, whereas its fault-free value is logic-0 (referred also as worst-case logic-0 error); • accordingly, 1 → 0, which marks an event where the output of the gate is at logic-0, whereas its fault-free value is logic-1 (referred also as worst-case logic-1 error). In this paper the following symbol convention is used: • the arbitrary gate output is marked as g; • the total error probability at g for 0 → 1 and 1 → 0 events is marked as Pr(g0→1 ) and Pr(g1→0 ), respectively; • the propagation error probability at g (which is defined further in the text) for 0 → 1 and 1 → 0 events is marked as Pp (g0→1 ) and Pp (g1→0 ), respectively; • the single gate error probability for a 0 → 1 and 1 → 0 events are marked as P0 and P1 , respectively; • the joint single gate error probability for a 0 → 1 and 1 → 0 events is marked as P01 . In general, Pr(g0→1 ) = Pr(g1→0 ) for an internal gate, located inside a circuit. Initially, Pr(xi,0→1 ) and Pr(xi,1→0 ) are known for the primary inputs xi of the circuit. In the core computational step of the algorithm, the 0 → 1 and 1 → 0 error components of input vectors at the inputs of a gate are combined to obtain propagation error probability Pp (g0→1 ) and Pp (g1→0 ). These probabilities are then combined with the local gate failure probability to obtain Pr(g0→1 ) and Pr(g1→0 ) at the output of the gate.
The single-pass reliability analysis is performed by recursively applying the core computational step of the algorithm to the gates in a topological order. At the end of the single-pass, Pr(y0→1 ) and Pr(y1→0 ) are obtained for the output y of the circuit. The time complexity of the algorithm is O(n), where n is the number of gates in the circuit. Note that the singlepass reliability analysis gives the exact values of probability of error at the output in the absence of reconvergent fanout. The modification of the original algorithm in order to account for the permanent errors is reflected in the way the propagation error probabilities, Pr(g0→1 ) and Pr(g1→0 ) are calculated. Transient errors (whose effects are observable not longer than one clock period) can affect the output value that corresponds to only one input vector active at that time. Permanent errors on the other hand, are present all the time and affect the output value that corresponds to each input vector. Expression of propagation error probabilities: The 0 → 1 and 1 → 0 input error probability at g are given as Pp (g0→1 ) = Pr(g0→1 | g is fault free) . Pp (g1→0 ) = Pr(g1→0 | g is fault free)
(1)
These are probabilities that the output g would be erroneous (whereas the gate does not fail) for at least one input vector, i.e. probabilities for combined input error vectors. Expressions for the propagation error probabilities and its components, for a 2-input NAND gate with inputs i and j (gate labeled with 3 in Figure 1), are given in Table I. P00 , P01 , P10 and P11 represent the propagation error probability components for input vectors 00, 01, 10 and 11 respectively. P00/01 , P00/10 , P01/10 and P00/01/10 represent the joint propagation error probability components for 00/01, 00/10, 01/10 and 00/01/11 input vectors respectively. Expressions of Pr(g0→1 ) and Pr(g1→0 ): If P0 and P1 are the 0 → 1 and 1 → 0 probabilities of failure of the local gate output g, respectively, the following expressions are obtained: Pr(g0→1 ) = (1 − Pp (g0→1 )) · P0 + Pp (g0→1 ) · (1 − P1 ) . Pr(g1→0 ) = (1 − Pp (g1→0 )) · P1 + Pp (g1→0 ) · (1 − P0 )
(2)
Note that events at inputs i and j are assumed independent which is valid if the gate is not a site of reconvergence of fanout. Since reconvergence causes the two events to be correlated, it is handled separately, in the following Subsection. The single-pass reliability analysis is illustrated for the circuit shown in Figure 1. The gate failure probabilities (P0 and P1 ), and probabilities of the 0 → 1 and 1 → 0 error are
a b
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0ĺ1 1ĺ0 probability of error
Figure 1. Small circuit example realized with 2-input NAND gates used as a logic unit.
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Table I E XPRESSIONS OF INPUT ERROR COMPONENTS FOR A 2- INPUT NAND Input vector 00 01 10 00/01 00/10 01/10 00/01/10 Total
1 → 0 input error component P00 = Pr(i0→1 ) Pr(j0→1 ) P01 = Pr(i0→1 )(1 − Pr(j1→0 )) P10 = Pr(j0→1 )(1 − Pr(i1→0 )) P00/01 = Pr(i0→1 ) Pr(j0→1 )(1 − Pr(j1→0 )) P00/10 = Pr(i0→1 ) Pr(j0→1 )(1 − Pr(i1→0 )) P00/10 = Pr(i0→1 ) Pr(j0→1 )(1 − Pr(i1→0 ))(1 − Pr(j1→0 )) P00/10/10 = Pr(i0→1 ) Pr(j0→1 )(1 − Pr(i1→0 ))(1 − Pr(j1→0 )) Pp (g1→0 ) = P00 + P01 + P10 − P00/01 − P00/10
Input vector 11 Total
0 → 1 input error component P11 = Pr(i1→0 ) + Pr(j1→0 ) − Pr(i1→0 ) Pr(j1→0 ) Pp (g0→1 ) = P11
indicated for each gate. The gates are numbered in the order in which they are processed. Although the computation has been illustrated for an NAND gate, the computation for NORs, inverters, ANDs, ORs, and XORs are all handled in a similar manner and the corresponding tables have been excluded for brevity. Only 2 and 3-input gates are supported. However, the tool can easily be enhanced to support more input gates by extending propagation probability tables. A. Handling Reconvergent Fanout The single-pass reliability algorithm computes the exact value of the probability of failure of circuits with no reconvergent fanouts. The presence of reconvergent fanout renders the single-pass reliability analysis approximate because the events of a 0 → 1 or 1 → 0 error of the inputs of a gate may not be independent at the point of reconvergence. The theory of correlation coefficients used in signal probability computation [12] is extended to make single-pass reliability analysis more accurate in the presence of reconvergent fanout. The original approach from [9] is followed, but the new way the correlation coefficient are calculated is adopted. Let v and w represent two wires, then four correlation coefficients for this pair are denoted by Cvw , Cvw , Cvw˜ , and Cv˜w˜ , where v, w, v˜, and w ˜ refer to the event of a 0 → 1, 0 → 1, 1 → 0, and 1 → 0 error at v and w respectively. The correlation coefficients must be considered at the gates whose inputs are the site of reconvergence of fanout. At such gates, the events of a 0 → 1 or 1 → 0 error at the inputs are not independent. Thus, the entries in the second column of Table I are weighted by the appropriate correlation coefficient, e.g., Pr(i0→1 )(1 − Pr(j1→0 )) becomes Pr(i0→1 )(1 − Pr(j1→0 )Ci˜j ). Correlation coefficient computation: The correlation coefficient of a pair of wires can be calculated by computing the correlation coefficients of the wires in the fanout source that cause the correlation in the first step, and then propagating these correlation coefficients along the appropriate paths leading to the pair of wires. Note that all four correlation coefficients for two independent wires are equal to 1. The computation of correlation coefficients for the fanout source and the propagation of correlation coefficients at a 2-input
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NAND gate are described in the following. Computation at fanout source node: Following the definition of the correlation coefficient, the correlation coefficient for the pair of wires {l, m} with fanout source node i (Figure 2a) is computed as follows: Pr(l0→1 ) = Pr(l0→1 , m0→1 ) = Pr(l0→1 ) Pr(m0→1 )Clm . 1 Clm = Pr(m0→1 )
(3)
C˜lm ˜ ˜ can be computed in a similar manner. C˜ lm and Clm are equal to zero since it is not possible to have a 0 → 1 error on m and a 1 → 0 error on l, or vice-versa.
l i
m
i j k
(a) Figure 2.
l
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Computation/propagation of correlation coefficient.
Propagation at a NAND gate: The propagation of correlation coefficients is illustrated for the NAND gate in Figure 2b. Let i, j, k be three wires whose pairwise correlation coefficients are known. The computation of the correlation coefficients for the pair {l, k} involves the propagation of the correlation coefficients through the NAND gate, using the correlation coefficients for pairs (i, k) and (j, k). Following the definition of the correlation coefficient and the definition of the conditional probability [13]: Clk =
Pr(l1→0 , k0→1 ) Pr(l1→0 |k0→1 ) = . Pr(l1→0 ) Pr(k1→0 ) Pr(l1→0 )
(4)
The expression of Pr(l1→0 |k0→1 ) in terms of the correlation coefficients for pairs of inputs (i, k) and (j, k) is given as: Pr(l1→0 |k0→1 ) = (1 − Pp (l1→0 |k0→1 )) · P0 + Pp (l1→0 |k0→1 ) · P1 and Pp (l1→0 |k0→1 ) = Pr(i0→1 )Cik Pr(j0→1 )Cjk Cij + Pr(i0→1 )Cik (1 − Pr(j1→0 ))C˜jk Ci˜j + Pr(j0→1 )Cjk (1 − Pr(i1→0 ))C˜ik C˜ij + Pr(i0→1 )Cik Pr(j0→1 )Cjk (1 − Pr(j1→0 ))C˜jk Cij + Pr(i0→1 )Cik Pr(j0→1 )Cjk (1 − Pr(i1→0 ))C˜ik Cij
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(5)
The terms in the expression of Pp (l1→0 |k0→1 ) are similar to the terms in the second column of Table I. The difference is that the probability of the 0 → 1 and 1 → 0 errors are multiplied by the appropriate correlation coefficients. The expression for Clk is derived in a similar manner using the lower part of Table I. Expressions for Clk˜ and C˜lk˜ are derived by replacing k with k˜ in expressions for Clk and C˜lk respectively. In comparison with the original algorithm presented in [9], this modified version has the same level of accuracy and slightly improved computational speed. The speed improvement is due to the omission of the weight vector calculation.
The procedure for modeling PDFs for the worst case logic-0 and logic-1 at the output of an arbitrary circuit gate g is presented in the following. The example circuit from Figure 1 is used. If we mark the desired PDFs as hg,max 0 and hg,min 1 , the probability of failure acquired using the single-pass reliability tool is given as
1
hg,max 0 (x)dx and , 0.5 0.5 hg,min 1 (x)dx Pr(g1→0 ) =
(6)
0
since all output values for logic-0 (logic-1) that are higher (lower) than a threshold of 0.5 are assumed as erroneous. Output PDFs are modeled using the two values for the probability of the gate failure from (6) acquired with the single-pass reliability tool and PDFs of individual gates that are close to output in a topological sense. 0 → a marks an event where the output of the gate is at any level that is different from logic-0 and logic-1 (0 < a < 1) when its faultfree value is logic-0. Accordingly, 1 → a marks an event that output of the gate is at any level different from logic-0 and logic-1 (0 < a < 1) when its fault-free value is logic-1. We differentiate four distinctive cases of the propagation error probability at g Pp (g0→1 ) = Pr(g0→1 | Pp (g0→a ) = Pr(g0→a | Pp (g1→0 ) = Pr(g1→0 | Pp (g1→a ) = Pr(g1→a |
is is is is
fault fault fault fault
free) free) . free) free)
(2)
(1)
,
(9)
(1)
where hp,0→a (hp,1→a ) is the PDF at the output of g for the (2) (2) 0 → a (1 → a) event when g is fault-free and hp,0→a (hp,1→a ) is the PDF at the output of g for the 0 → a (1 → a) event when g is faulty. After inserting (9) into (8) hg,max 0 = (1 − Pp (g0→1 ) − Pp (g0→a )) · h,max 0 (1)
+ Pp (g0→1 ) · h,min 1 + Pp (g0→a ) · (1 − P0 ) · hp,0→a + Pp (g0→a ) · P0 · hp,0→a hg,min 1 = (1 − Pp (g1→0 ) − Pp (g1→a )) · h,min 1
, (1)
+ Pp (g1→0 ) · h,max 0 + Pp (g1→a ) · (1 − P1 ) · hp,1→a (2)
+ Pp (g1→a ) · P1 · hp,1→a (10)
where P0 and P1 are probabilities of failure of the local gate output g for logic-0 and logic-1 respectively, as presented at the beginning of Section II. Not all the elements of the sum in (10) have the same impact on hg,max 0 (hg,min 1 ). The impact is determined by probability factors that multiply PDFs on the right-hand side of (10), since the integral of each of these PDFs is equal to one. The probability factors ratio is given as 1 − Pp (g0→1 ) − Pp (g0→a ) Pp (g0→1 ) > > Pp (g0→a ) · (1 − P0 ) Pp (g0→a ) · P0 . 1 − Pp (g1→0 ) − Pp (g1→a ) Pp (g1→0 ) > > Pp (g1→a ) · (1 − P1 ) Pp (g1→a ) · P1 (11)
The smallest propagation factor (the last element on the righthand side of (11)) can be disregarded. After introducing this approximation, (10) becomes hg,max 0 ≈ (1 − Pp (g0→1 ) − Pp (g0→a )) · h,max 0 (1)
+ Pp (g0→1 ) · h,min 1 + Pp (g0→a ) · hp,0→a . ≈ (1 − Pp (g1→0 ) − Pp (g1→a )) · h,min 1
(12)
(1)
+ Pp (g1→0 ) · h,max 0 + Pp (g1→a ) · hp,1→a (7)
If we mark the PDF of the local gate output g for the worst case logic-0 (logic-1) as h,max 0 (h,min 1 ) and hp,0→a (hp,1→a ) the PDF at the output of g for 0 → a (1 → a) propagation error then hg,max 0 and hg,min 1 are expressed as hg,max 0 = (1 − Pp (g0→1 ) − Pp (g0→a )) · h,max 0 + Pp (g0→1 ) · h,min 1 + Pp (g0→a ) · hp,0→a . hg,min 1 = (1 − Pp (g1→0 ) − Pp (g1→a )) · h,min 1 + Pp (g1→0 ) · h,max 0 + Pp (g1→a ) · hp,1→a
(1)
hp,1→a = (1 − P1 ) · hp,1→a + P1 · hp,1→a
hg,min 1 g g g g
(2)
(2)
III. O UTPUT PDF M ODELING
Pr(g0→1 ) =
(1)
hp,0→a = (1 − P0 ) · hp,0→a + P0 · hp,0→a
(8)
hp,0→a and hp,1→a consist of two components; one for the fault-free g and another for the faulty g
(1)
The unknowns in (12) are Pp (g0→a ) · hp,0→a and Pp (g1→a ) · (1) hp,1→a . All other elements can be subsequently derived. To determine the unknowns, we observe the transformation of PDFs at the input of g by the gate transfer function. The transfer function is determined for a fault-free library gate with default (output gate) load. Similarly as in previous Section, the 2-input NAND gate is considered without loosing generality, and the circuit example is depicted in Figure 1. A single input transfer function for a typical 2-input NAND gate is depicted in Figure 3a. In order for the 0 → a (1 → a) event to occur, one input has to be in the region defined as [a , VDD − a ] with fault-free value at logic-1 (logic-0) and another input has to be at logic-1. If we mark the PDFs for the worst case logic-0 and logic-1 at inputs i and j of g as hi,max 0 , hi,min 1 , hj,max 0
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Gate output value [Vdd]
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(b)
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Figure 3. 2-input NAND (a) gate transfer function; (b) PDF for the worst case logic-0 in [a , VDD − a ] region; (c) transformation of PDF from (b) through gate transfer function from (a).
and hj,min 1 , respectively, and the gate g transfer function of the PDF in the region of interest ([a , VDD − a ]) as fT
be omitted. Since Pp (g0→a ) (Pp (g1→a )) is the smallest factor in (12), this approximation is justified. For the same reason, factors Pr(i1→0 ) and Pr(j1→0 ) are omitted from (13). Finally,
(1)
Pp (g0→a ) · hp,0→a = fT (hi,min 1 )(1 − Pr(j1→0 )) + fT (hj,min 1 )(1 − Pr(i1→0 )) (1)
Pp (g1→a ) · hp,1→a = fT (hi,max 0 )(1 − Pr(j1→0 )) + fT (hj,max 0 )(1 − Pr(i1→0 ))
(1)
Pp (g0→a ) · hp,0→a ≈ 2fT (h,min 1 ) .
(13)
hi,max 0 , hi,min 1 , hj,max 0 and hj,min 1 also respect (12). fT is computed numerically using the gate g transfer function. The PDF of the 2-input NAND gate in the region of interest ([a , VDD − a ]) (depicted in green in Figure 3b) ha and its transformation through the transfer function fT (ha ) are given in Figure 3b and 3c, respectively. By increasing voltage gain of the transfer function, the probability values in [a , VDD − a ] region of the transformed PDF - fT (ha ) reduce and already for voltage gain equal to ten can be totally omitted. Taking this fact into consideration, hi,max 0 and hi,min 1 (hj,max 0 and hj,min 1 ) which also comply with (12) can be approximated with h,max 0 and h,min 1 in the region of (1) interest. This approximation means that Pp (g0→a )·hp,0→a and (1) Pp (g1→a ) · hp,1→a only depend on the PDFs of individual gates in the last layer of the fanin cone (outputs i and j in Figure 1), and that propagating factors in these PDFs can
332
(1)
Pp (g1→a ) · hp,1→a ≈ 2fT (h,max 0 )
.
(14)
From (14), Pp (g0→a ) and Pp (g1→a ) are expressed as Pp (g0→a ) ≈ Pp (g1→a ) ≈
1
0 1 0
2fT (h,max 0 ) .
(15)
2fT (h,min 1 )
After replacing (12) into (6) and solving for Pp (g0→1 ) and Pp (g1→0 ) the remaining unknown factors from (12) are derived as Pr(g0→1 ) − (1 − Pp (g0→a ))P0 1 − P0 − P1 1 (1) Pp (g0→a ) 0.5 hp,0→a (x)dx − 1 − P0 − P1 . Pr(g1→0 ) − (1 − Pp (g1→a ))P1 Pp (g1→0 ) = 1 − P0 − P1 0.5 (1) Pp (g1→a ) 0 hp,1→a (x)dx − 1 − P0 − P1
Pp (g0→1 ) =
2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010)
(16)
IV. R ESULTS A set of MATLAB scripts has been developed to automate the described process related to output PDF modeling. The actual calculations implemented in MATLAB are performed on discrete data sets where PDFs are represented with 100 points histograms. The calculations and simulations were run on 2.66-GHz quad core-based system with 4GB of memory. A MC framework performing SPICE-level simulations is used to obtain data for the comparison and the necessary PDFs of the library gates. All possible combinations of single and double permanent faults are injected in each standard library gate in order to generate PDFs, for values of the probability of fault per transistor (pf ) in the range from 0.1% to 20%. 4-bit full adder is used as the main benchmark circuit. This is an area/delay minimized realization of an adder, synthesized in Synopsis using the reduced library set consisting of 2 and 3-input NAND and NOR gates and inverters. The benchmark circuit consists of 39 gates in total. The modeled PDFs for the worst case logic-0 and logic1 at outputs of 4-bit full adder (denoted as “modeled” in the figures) are compared with the equivalent PDFs acquired using MC tool (denoted as “simulated” in the figures). Single, double and triple permanent faults have been injected into the MC framework. The number of MC iterations is set to 3 × 320 000 in order to minimize the error due to sampling. The values of modeled and simulated PDFs for the worst case logic-0 are depicted in Figure 4a and 4b. Likewise, the values of modeled and simulated PDFs for the worst case logic-1 are depicted in Figure 5a and 5b. The applied pf to obtain data depicted in figures is 2%. All values are depicted in 100 bins original histograms (without interpolation). The values of histograms for the output equal to zero and V dd are excluded for better visualization, since they are few orders of magnitude larger than other values in the histogram. The difference between PDFs is not noticeable. The intrinsic property of our method is that the runtime does not depend on the complexity of the circuit once the circuit output probability of failure is acquired. The average runtime of our tool for the benchmark circuit (for different values of pf ), including single pass reliability analysis tool, is under 100ms. In order to compare modeled and simulated PDFs, Pearson’s chi-square test [13] for histogram comparison has been performed. The chi-square statistics calculates the difference between simulated and modeled histogram as X2 =
r (Si − nMi )2 , nMi i=1
(17)
where X 2 is the test statistic that asymptotically approaches a χ2 distribution, Si is the simulated histogram value (acquired directly from MC simulations), Mi is the modeled histogram value (normalized - sum of its values is equal to one), n is number of iterations (only iterations when circuit output was faulty are included) and r is the number of histogram bins (100 in our case). The null-hypothesis is that compared distributions
are identical. This hypothesis can be rejected with significance level α (the rejecting error of the correct null-hypothesis) if and only if X 2 > ε1−α , where ε1−α is 1 − α quantile of the χ2 (r − 1) distribution. Table II shows X 2 values for PDFs of each output of the 4-bit full adder (Sum1 to Sum4 ) for the worst case logic0 and logic-1 and for different values of pf . 1% and 5% quantile values for ε1−α used for comparison are 134.642 and 123.225 respectively. Following the chi-square test results, the hypothesis that modeled and simulated distributions are identical can not be rejected for any significance level and for any of the compared PDFs. All X 2 values are smaller than the value of ε0.95 . X 2 value does not change noticeably for different pf . C HI - SQUARE TEST RESULTS : X 2
Table II
VALUES FOR OUTPUTS OF 4-bit full adder FOR THE WORST CASE LOGIC -0 AND LOGIC -1 AND FOR DIFFERENT VALUES OF pf .
output Sum1 Sum2 Sum3 Sum4
logic-0 logic-1 logic-0 logic-1 logic-0 logic-1 logic-0 logic-1
pf =0.1% X2 35.72 23.30 68.13 51.86 44.24 61.47 55.29 76.43
pf =1% X2 38.49 29.88 62.56 60.06 38.42 65.07 54.57 82.74
pf =5% X2 28.15 19.41 61.98 57.33 41.79 69.51 51.84 74.86
pf =20% X2 34.93 31.23 72.54 50.43 47.62 62.83 59.90 81.03
V. C ONCLUSION The need for EDA tools that offer realistic reliability evaluation and modeling by employing a data collection without over-simplification of the models is becoming more prominent. The precise evaluation of the reliability of logic circuits has a significant importance not only because of the possibility to compare different fault-tolerance techniques, but also because the circuit design in highly-defective and future nanotechnologies can be enhanced. Our novel method has demonstrated that output PDFs of an arbitrary gate are only dependent on PDFs of gates located in the last two stages of the output cone and on output probability of failure. This enables a fast and accurate modeling of output PDFs for logic-0 and logic-1 of an arbitrary circuit. The method has been evaluated in standard CMOS technology for permanent defects modeled with detailed transistor fault models. However, no restriction apply on the method implementation in any fabrication technology including future nanodevices. The method is not restricted to permanent defects and can be applied to transient faults in an equal manner. The accuracy of the method has been demonstrated and confirmed with Pearson’s chi-square test. This method has several potential applications, including the analysis of averaging (analog) fault-tolerant techniques, fine-grained redundancy insertion, and reliability-driven design optimization.
2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010)
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-3
1.2
-3
worst case logic-0, zoomed
x 10
1.2 1 simulated PDF
modeled PDF
1
worst case logic-0, zoomed
x 10
0.8 0.6 0.4
0.8 0.6 0.4 0.2
0.2 0 0
0.1
0.2
0.3 0.4 0.5 0.6 0.7 Sum4 output value [Vdd]
0.8
0.9
0 0
1
0.2
(a) Figure 4. -3
-3
1.2
1
1
0.8
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0.6 0.4 0.2 0 0
worst case logic-1, zoomed
x 10
0.6 0.4 0.2
0.1
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0.3 0.4 0.5 0.6 0.7 Sum4 output value [Vdd]
0.8
0.9
0 0
1
(a) Figure 5.
0.1
0.2
0.3 0.4 0.5 0.6 0.7 0.8 Sum4 output value [Vdd]
0.9
1
(b) 4-bit full-adder worst case logic-1 PDF: (a) modeled; (b) simulated.
R EFERENCES [1] James D. Meindl, Qiang Chen, and Jeffrey A. Davis, “Limits on silicon nanoelectronics for terascale integration”, Science, vol. 293, no. 5537, pp. 2044 – 2049, 2001. [2] G. Bourianoff, “The future of nanocomputing”, Computer, vol. 36, no. 8, pp. 44–53, Aug. 2003. [3] Chenxiang Lin, Yan Liu, Sherri Rinker, and Hao Yan, “DNA tile based self-assembly: Building complex nanoarchitectures”, ChemPhysChem, vol. 7, no. 8, pp. 1641–1647, 2006. [4] R. I. Bahar, J. Chen, and J. Mundy, Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, chapter A probabilistic-based design for nanoscale computation, pp. 133–156, Kluwer Academic Publishers, 2004. [5] J. von Neumann, Automata Studies, chapter Probabilistic logic and the synthesis of reliable organisms from unreliable components, pp. 43–98, Prinston, NJ: Princeton Univ. Press, 1956. [6] S. Krishnaswamy, G. F. Viamontes, I. L. Markov, and J. P. Hayes, “Accurate reliability evaluation and enhancement via probabilistic transfer matrices”, in Proc. Design, Automation and Test in Europe (DATE), 2005, pp. 282–287. [7] T. Rejimon and S. Bhanja, “Scalable probabilistic computing models using Bayesian networks”, in Proc. 48th Midwest Symposium on Circuits and Systems (MWSCAS), 7–10 Aug. 2005, pp. 712–715. [8] E. Taylor, Jie Han, and J. Fortes, “Towards accurate and efficient reliability modeling of nanoelectronic circuits”, in Proc. Sixth IEEE
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4-bit full-adder worst case logic-0 PDF: (a) modeled; (b) simulated.
simulated PDF
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0.4 0.6 Sum4 output value [Vdd]
[9] [10] [11]
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Conference on Nanotechnology (IEEE-NANO), 17–20 June 2006, vol. 1, pp. 395–398. M. R. Choudhury and K. Mohanram, “Reliability analysis of logic circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 3, pp. 392–405, March 2009. D. T. Franco, M. C. Vasconcelosa, L. Navinera, and J.-F. Navinera, “Signal probability for reliability evaluation of logic circuits”, Microelectronics Reliability, vol. 48, no. 8-9, pp. 1586–1591, 2008. M. Stanisavljevic, A. Schmid, and Y. Leblebici, “Fault-tolerance of robust feed-forward architecture using single-ended and differential deepsubmicron circuits under massive defect density”, in Proc. International Joint Conference on Neural Networks (IJCNN), 16–21 July 2006, pp. 2771–2778. S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricco, “Estimate of signal probability in combinational logic networks”, in Proc. 1st European Test Conference, 12–14 April 1989, pp. 132–138. A. Papoulis and S. U. Pillai, Probability, Random Variables and Stohastic Processes, NY: McGraw-Hill, 4th edition, 2002.
2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010)
