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PARTIAL SCAN DESIGN BASED ON STATE TRANSITION MODELING Vamsi Boppana Coordinated Science Laboratory University of Illinois Urbana, IL 61801 [email protected]
Abstract Selection of flip-flops that provide the best improvements in testability is a critical part of the partial scan design process. This paper describes a new technique for flip-flop selection that models the effect of scan in terms of the introduction of pseudo state transitions in the state transition graph. The identification of (desired) state transitions that provide for improved testability is based on an analysis of the known reachable states and desired states which ensure improved fault detection. Experiments are presented on the ISCAS 89 circuits to show significant improvements in the testability of the resulting partial scan design.
1 Introduction Partial scan design, in which a subset of flip-flops is selected to be scanned, provides a wide spectrum of design solutions that trade off testability for the overheads incurred by scan design. The overheads introduced by the incorporation of scan include area overheads and timing penalties. In partial scan design, a designer is typically interested in selecting the best set of flip-flops to be scanned under a given set of constraints.
1.1
Previous Work
Previous research on partial scan design can be categorized into three areas: flip-flop selection [1–25], test length reduction [26–29], and retiming [30–33]. Flip-flop selection is a crucial part of the design process and hence intensive research has been performed in this area [1–17, 19– 25]. The problem addressed in this paper is that of flip-flop selection during the partial scan design process. Previous methods for selecting flip-flops are based on one or several of the three following techniques: testability analysis This research was supported in part by the Semiconductor Research Corporation (SRC) under grant 95-DP-109, by the Office of Naval Research (ONR) under grant N00014-95-1-1049, and by an equipment grant from Hewlett-Packard.
W. Kent Fuchs School of Electrical and Computer Engineering Purdue University West Lafayette, IN 47907-1285 [email protected]
[1, 2, 4–8], structural analysis [2, 3, 12–17, 19–25], and test generation [3, 9–11]. Early partial scan design employed a simple testability-based method for the selection of flipflops [1]. Schemes based on sophisticated testability analysis have since been proposed [6–8]. Several techniques that employ testability analysis in conjunction with other schemes are also known [4, 5]. However, one of the main problems associated with testability analysis-based techniques is that the fault coverage achieved for circuits with complex structure may not be satisfactory. Structural analysis has been used to remove all feedback loops in a given circuit, resulting in a simpler circuit structure to be handled by the test generation algorithm. The first approach in this direction is the removal of all feedback loops, so that the resulting circuit works in a pipelined fashion [12, 13]. Another approach, called cycle-breaking, removes all feedback loops except self-loops [14–17, 19–24]. The cycle-breaking algorithm is simple and relatively effective. However, it has been observed that even if all cycles are broken, the algorithm may not cover all faults for some circuits [3]. More importantly, for many circuits, it may be infeasible or unnecessary to break all feedback loops to achieve desirable fault coverages [3]. Cycle cutting has also been accomplished by using intensive valid state analysis to assess the impact of cutting specific cycles [25]. Test generation-based methods exploit information available from the test generator to drive the scan selection process [3, 9–11]. The main advantage of using test generation-based techniques is that it is possible to target specific fault detection objectives rather than simplify the circuit (by structural analysis) or improve testability of specific regions in the circuit (by testability analysis). This typically results in the expensive computational and storage requirements associated with pure test generation-based techniques [11]. For circuits with reset state knowledge (typically small in size), effective solutions are known [10]. An efficient technique that exploits information available from the test generator, but does not suffer from the computational limitations of the test generation-based techniques, is the OPUS partial scan selection technique [3]. Here, the
computational requirements are reduced by the use of structural analysis in conjunction with the test generation information.
1.2
Summary of Our Contributions
In this paper, we provide a new partial scan selection method based on the modeling of the scanning of a flipflop, by the introduction of pseudo state transitions in the state transition graph of the original circuit to obtain an enhanced state transition graph (E-STG). This model is effectively utilized to achieve desirable fault coverage by using the introduced state transitions for the efficient navigation of the machines to desirable states. For each fault that is aborted by the test generation procedure, it is first noted whether the fault is aborted due to a state justification failure or a propagation failure. In the case of propagation failures, information on states that show the fault effects is recorded. This is used to introduce pseudo state transitions that enable the detection of the fault under consideration. For justification failures, information is collected on states that, when reached, can detect the fault under consideration. This phase is similar to the justification and propagation requirement identification phases proposed earlier [11]. In addition to this information, we collect information about the states that are already known to be reachable. This information is then used to create the most effective (least expensive) pseudo state transition between a state already known to be reachable and a desired state. The desired state is thus made reachable by the help of the introduced pseudo state transition and ensures the detection of the targeted fault. Experimental results are presented on large ISCAS 89 circuits and are compared to the OPUS partial scan selection algorithm [3] (a test generation-based technique that is capable of handling large circuits) and shown to be superior. Important contributions of this work are listed below.
It provides a theoretical model for analyzing the effects of introduction of scan in the original state transition graph. Previous methods for partial scan selection based on test generation information have not been able to exploit the knowledge of reachable states, because of the lack of such a model. It provides techniques that effectively apply test generation-based partial scan selection to large circuits. The identification of desirable state transitions based on test generation and fault simulation knowledge provides a basis for flip-flop selection. The computational and storage requirements are effectively reduced by showing that good circuit information alone (as opposed to multiple faulty
circuit information) can be used to determine the desired state transitions.
2 Modeling of Scan Effects in the STG This section provides the theoretical model that allows for incorporating the effects of scan in the original state transition graph.
2.1 Preliminaries Let the circuit under consideration consist of NS flipflops, NI primary inputs and NO primary outputs. Hence, the state can be completely expressed as an NS -tuple whose entries are 0s or 1s. It may also be noted that X values are often used to compactly enumerate multiple states. A value of X at one of the positions means that the flip-flop corresponding to that position has either a 0 or a 1 value. Let us indicate an input tuple by Ij = (I N1 ; I N2 ; : : : ; I NNI ) and an output tuple by Oj = (OP1 ; OP2 ; : : : ; OPNO ). We note that I Nj ; 8 j 2 (1; : : : ; NI ) and OPj ; 8 j 2 (1; : : : ; NO ) can take the values of 0 or 1 or X . Let us further indicate a state tuple by Sj = (F F1 ; F F2 ; : : : ; F FNS ) meaning that F Fj ; 8 j 2 (1; : : : ; NS ) is the value of flip-flop j and may have the value 0, 1 or X . Definition 1 (State Transition Graph (STG)) The state transition graph is defined as the graph G(V ; E ), where the set of vertices V is the set of all possible states (2NS in number) and an edge is of the form ((Si ; Sj )(Ii ; Oj )) where Si and Sj are state tuples, Ii is an input tuple, and Oj is an output tuple, and the machine transfers from state Si to state Sj upon application of the input Ii and produces an output Oj .
2.2 Pseudo State Transitions for Modeling Scan We now define the enhanced STG that captures the incorporation of scan into the original STG. Let the number of flip-flops chosen for scan be NR and the set of those flipflops be given by S F F = (S F F1 ; S F F2 ; : : : ; S F FNR ), where S F Fj ; 8j 2 (1; 2; : : : ; NR ) indicates the position number of a flip-flop in the original state tuple. Definition 2 (Enhanced State Transition Graph (E-STG)) In addition to the set of inputs and outputs from the original STG, the enhanced state transition graph has two pseudo inputs called P S I N1 and P S I N2 , and NR pseudo outputs called (P S OP1 ; P S OP2 ; : : : ; P S OPNR ). The state continues to be expressed as an NS tuple. Hence, the
set of vertices remains the same. The new input and output tuples are therefore given by : Input : Ij = (I N1 ; I N2 ; : : : ; I NNI ; P S I N1 ; P S I N2 ). Output : Oj = (OP1 ; OP2 ; : : : ; OPNO ; P S OP1 ; P S OP2 ; : : : ; P S OPNR ). The new state transitions are defined as follows :
For each transition ((Sx ; Sy )(Ii ; Oj )) from the original state transition graph, create a transition ((Sx ; Sy )(Ik ; Ol )) in the enhanced state transition graph, where the first NI elements of the tuple Ik are exactly the same as in Ii and the last two tuples are set to 0 and 0, and the first NO elements of the tuple Ol are the same as in Oj and the last NR elements of the tuple are set to the value X . For each state Sj = (F F1 ; F F2 ; : : : ; F FNS ), create a pseudo transition given by ((Sj ; Sj )(Ix ; Oy )), where Ix = (X; X; : : : ; X; 1; 0), i.e., P S I N1 = 1 and P S I N2 = 0 and every other position equal to the X value, and the output tuple Oy = (X; X; : : : ; X; F FSF F1 ; F FSF F2 ; : : : ; F FSF FNR ). For each state pair Si & Sj such that the only positions where the values of their tuples are different belongs to the set S F F = (S F F1 ; S F F2 ; : : : ; S F FNR ), introduce the two pseudo transitions ((Si ; Sj )(Ix ; Oy )) and ((Sj ; Si )(Ix ; Oy )), where Ix = (X; X; : : : ; X; X; 1), i.e., P S I N1 = X and P S I N2 = 1 and every other position equal to the X value, and the output tuple Oy = (X; X; : : : ; X; X ), i.e., the output tuple consists of all positions taking the value X .
2.3
Intuition Behind the Model
The introduction of scan provides for two improvements in the state machine testability. The first arises from the observability of the state lines and the second comes from the additional control ability provided to guide the machine to desirable states. The pseudo transitions introduced in our modeling phase are intended to capture exactly these two improvements. The pseudo inputs are used to capture the operation of the machine in three modes :
P S I N1
=0
; P S I N2
= 0:
The original machine
2.4 Example Illustrating the Model As an example to illustrate the definition of the E-STG, consider a finite state machine whose state transition graph is shown in Figure 1. This machine has 3 flip-flops, 1 input and 1 output. Hence, there are eight states in the machine. A state transition is indicated by an arrow from the starting state to the final state, and the input causing the transition and the output produced by it are indicated by an I =O symbol associated with the arrow. For example, there exists a state transition between states 000 and 001 caused by an input symbol X and producing the output value 0. This means that either of inputs 0 or 1 will transfer the machine from the state 000 to the state 001 producing an output of 0. Let us now assume that the flip-flop corresponding to the most significant (leftmost) bit is scanned. The effects of this scanning have been captured by the enhanced STG shown in Figure 2. The input tuple size has been increased from 1 to 3, and the output tuple size has been increased from 1 to 2 because of the scanning of 1 flip-flop. The pseudo transitions introduced have been shown by the dotted arcs, while the transitions present in the original STG are in solid arcs. The self-loop transitions indicated by the dotted arcs are the pseudo transitions corresponding to the machine mode with P S I N1 = 1; P S I N2 = 0. The eight transitions between the state pairs (000)(100), (001)(101), (010)(110) and (011)(111) are the pseudo transitions corresponding to the machine mode with P S I N1 = X; P S I N2 = 1. The fact that the E-STG has considerably more arcs than the original STG helps in the partial scan design process because it substantially simplifies the process of navigating through the state machine.
3 Partial Scan Design Strategy In this section, we describe our partial scan selection techniques based on the new model of the scan process. Methods for effective partial scan selection in large circuits are presented.
3.1 New Formulation of the Partial Scan Flip-flop Selection Problem
STG is captured by this mode.
P S I N1
=1
; P S I N2
= 0 : This scan mode captures
the increased observability provided by the addition of scan.
= X; P S I N2 = 1 : This scan mode captures the ability of the machine to be transferred to specific states because of the addition of scan.
P S I N1
We can now formulate the partial scan design problem in terms of the E-STG as the identification of the best set of flip-flops that gives an E-STG with highest fault detection capability. Hence, the problem of partial scan flipflop selection can be effectively solved by choosing a set of flip-flops that introduces the most desirable state transitions, i.e., the state transitions that ensure the maximum
000 X/0
X/0
100 X/0
X/0 001
111
011
101 X/0
X/0
X/0
X/0
010
110
Figure 1: Original State Transition Graph
X10/X1
XX1/XX X10/X0 000 X10/X0
X00/0X
100
X10/X0 XX1/XX
X00/0X
X00/0X
X00/0X
X10/X0
X00/0X
X00/0X
X10/X1
001 011
X10/X1
101 X10/X1X00/0X
010
111
X00/0X
110 XX1/XX
XX1/XX True Transitions Pseudo Transitions Figure 2: Enhanced State Transition Graph
number of detections. In order to determine the state transitions that are most desirable, we gather information from the test generation algorithm identifying states that, when reached, ensure the detectability of specific faults. An exhaustive run of the test generator (with large backtrack and time limits) is not required for this identification. We shall then couple this desired state information with information about states that are already known to be reachable (this information is shown to be easily gathered by a fault simulation run). Knowledge of the known reachable states is then used in conjunction with the desirable state information to identify the introduction of profitable state transitions.
3.2
Identification of the Desired States from the Sequential Test Generation Algorithm
In this work, it is assumed that sequential test generation is performed in two steps of forward fault propagation and backward state justification. Specifically, in our experimentation, the HITEC sequential test generation program [34] was used. The sequential test generation aims to propagate the fault effect to at least one primary output and to justify signal values assigned during the propagation process. Suppose that the test generation algorithm fails to generate a test for a particular fault that is not redundant in the full-scan version of the circuit. The algorithm may have failed for either of two reasons. There may be a propagation failure if fault effects cannot be propagated to a primary output (possibly because of a specified time/backtrack limit). Alternatively, there may be a justification failure if no justification sequence is found (again, possibly because of a specified time/backtrack limit) to transfer the faulty/good machine pair to any desired state pair from which there is a propagation path. It has been observed in the past [10, 11] and confirmed by our experiments that the backward justification phase presents the main difficulty in fault detection. Hence, for each fault for which there is a propagation failure, there exist states (by a state, we mean faulty/good state pair) from which the introduction of a P S I N1 = 1; P S I N2 = 0 transition ensures the detection of that fault. More important is the case of justification failures. For each such failure, a set of states (again, by a state, we mean faulty/good state pair) exists, which, when reached, ensures the detection of the fault (because the test generator has already been able to find a set of inputs that ensures the detection of the fault from such a state).
above. In addition, the set of known reachable states is also obtained. The test generation algorithm provides a set of vectors that detects a subset of the entire set of faults. These vectors often transfer the machines (faulty/good) to states that are near (a measure for the distance will be presented shortly) the desired states (identified from the test generation phase). An intuitive explanation of this phenomenon is found in the fact that the faults in a circuit are not entirely uncorrelated; this implies similarities in the state spaces of various faulty circuits. Hence, a set of reachable states is found for each faulty/good machine pair through fault simulation of the already available vectors. This consists of the known reachable state information.
3.4 Computation of the Best Flip-Flops to Scan Given the sets of known reachable states and the sets of desirable states for each of the faults that were not detected, we present an algorithm to find the best set of flip-flops to scan. We now present a measure of the distance between a pair of faulty/good states. This is necessary because a lesser distance indicates a smaller number of flip-flops to scan to achieve the desired state. The distance between a pair of states (F S1 =GS1 ) and (F S2 =GS2 ), where F S1 = (F F 11 ; F F 12 ; : : : ; F F 1NS ) GS1 = (GF 11 ; GF 12 ; : : : ; GF 1NS ) F S2 = (F F 21 ; F F 22 ; : : : ; F F 2NS ) and GS2 = (GF 21 ; GF 22 ; : : : ; GF 2NS ) is
PNi
((
Distance
S
=1
)(
)) = (( 1i 1i ) ( 2i (( 1 1 ) ( 2 2 ))
F S1 =GS1 ; F S2 =GS2
F aulty
& &
where F aulty
GoodDist
GoodDist
def ined as in T able
1
FF
=GF
X =Y
; FF
; X =Y
=GF
2i ))
is
:
In Table 1, an entry of 0 indicates that no scan is required for making the transition at that bit position, 1 indicates that scan is required for making the state transition, and c ( = NS + 1) means that even the introduction of scan cannot create the required state transition. The algorithm to assign a profit for each flip-flop in the circuit based on the possible improvements in detection provided by that flipflop is presented in Figure 3. The intuition behind the reduced weighting for flip-flops involved in the creation of transitions for tackling propagation failures is that the main problem in sequential test generation is caused by justification failures. We show through our experimentation that the ordering of flip-flops generated through our scheme is indeed superior.
3.5 Effective Algorithm for Large Circuits 3.3
Identification of Known Reachable States
The identification of states that are desired to be reachable is performed by the test generation algorithm stated
The algorithm for assigning profits to flip-flops cannot be directly applied to large circuits, because of the overheads involved in the storage of the desired and known reachable
;
// Input: Desired states and known reachable states for each fault. // Function: Assigns profits to all the flip-flops based on an analysis of the detections possible by scanning them. // Routine Is propagation failure(f) gives a true or a false depending on whether the fault is a propagation failure; // if not a propagation failure, it has to be a justification failure. // Routine Desired states(f) gives the set of desired states for the fault f. // Routine Known reachable states(f) gives the set of known reachable states for the fault f. // Routine Get state with max detections(Desired states(f)) // returns the state with the max number of detections and the number of detections for the fault f. // Routine Get least distance state pair(Known reachable states(f), Desired states(f)) // returns the state pair with minimum distance between them and also the distance. // Routine Assign prop profits(S max, det) finds all ffs with a detection in // the state S max and increments the profit of each such ff by 5 NS =det. // Routine Assign just profits(S from, S to, dist) finds all ffs that have caused the distance between // S from and S to and increments the profit of each such ff by 10 NS =dist. for each fault f in the aborted fault list do if (Is propagation failure(f) == true) (S max, det) = Get state with max detections(Desired states(f)); Assign prop profits(S max, det); else (S from, S to, dist) = Get least distance state pair(Known reachable states(f), Desired states(f)); Assign just profits(S from, S to, dist); Figure 3: The Flip-flop profit assignment algorithm
state information. We now present heuristics for handling large circuits and show experimentally that the use of these heuristics does not result in a loss of the final partial scan design quality. We first introduce the notion that the knowledge of desired and reachable states need not be gathered for the faulty circuits, i.e., we claim that it suffices to gather information about the desired and reachable states in the good circuit alone. 3.5.1 Good Circuit Information is Enough! For making use of the good circuit information, we now introduce the crucial distance computation measure. Note that the state consists of just the good circuit state alone. Distance between a pair of states (GS1 ) and (GS2 ), where GS1 = (GF 11 ; GF 12 ; : : : ; GF 1NS ) GS2 = (GF 21 ; GF 22 ; : : : ; GF 2NS ) is
PN
((
Distance
S
i=1
) ( )) = (( 1i ) ( 2i )) (( 1 ) ( 2 ))
GS1 ; GS2
GoodDist
where GoodDist as in T able
2
:
GF X
; GF
; X
;
is def ined
The entries in Table 2 have the same meaning as before. The desired state information identification phase (performed inside the sequential test generation algorithm) now collects the desired state information only for the good circuit. Similarly, the known reachable state information identification (performed with the help of fault-simulating existing vectors) is performed only for the good circuit. This results in a major reduction in the overhead involved in storing the faulty circuit reachable states. In addition, a saving in the fault simulation cost is also achieved. To further reduce the storage requirements, we restrict the number of desired states per fault to one. Since the requirements on state lines in the justification process are reduced as the test generation process moves back (left) in the reverse-time process, we identify desired state information of only the leftmost time frame. Further, only a single state is identified for propagation requirements. This reduction in the amount of state information required by our algorithm provides significant savings in the memory requirements, thus making it feasible to run our algorithm on large circuits.
Table 1: Faulty&GoodDist Computation Table To ! From # 0/0 0/X 0/1 X/0 X/X X/1 1/0 1/X 1/1
0/0 0/X 0/1 X/0 X/X X/1 1/0 1/X 1/1 0 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1
c c 0 c c c c c c
0 1 1 0 1 1 0 1 1
0 0 0 0 0 0 0 0 0
1 1 0 1 1 0 1 1 0
c c c c c c 0 c c
1 1 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1 0
Table 2: GoodDist Computation Table To ! From # 0 X 1
0
X
1
0 1 1
0 0 0
1 1 0
4 Experimental Results In this section, we present experimental results comparing our scan selection technique with the test generation/structural analysis-based technique OPUS [3]. We also present data supporting the claim that the heuristics that were introduced for enabling the method to handle large circuits do not result in a significant loss in the quality of the partial scan solution. The test generation algorithm that was used in our experimentation was the HITEC test generation algorithm [34]. The PROOFS fault simulator [35] was used for the reachable state analysis. We first present the results of the test generation algorithm on the original ISCAS 89 circuits. These results are presented in Table 3. The time limit and backtrack limit for each fault were set to be 20 seconds and 100000 respectively in each of the circuits, except for s35932, because of the excessive amount of time required for test generation for it. For this circuit, a 2-second time limit and a backtrack limit of 10000 were placed. The columns in the table indicate the circuit name, the number of detected faults, the number of faults proven to be undetectable by the test generator, the number of aborted faults, the time taken in seconds, and the number of vectors respectively. From the set of benchmarks in Table 3, we now run the partial scan selection experiments for the circuits with at
least one aborted fault. We compare the performance of the test generation-based OPUS algorithm [3] with that of our algorithm (E-STG). These results are presented in Table 4, where we set the number of flip-flops to be scanned to 10% and 20% of the total number of flip-flops in the original circuit, and observe the improvements provided by scan. The table does not show the time taken for the scan selection phase itself, because for both of the algorithms, those times are too small to list (of the order of 0.1sec). For circuits for which only the results for 20% scan are shown, the circuits had less than or equal to 5 flip-flops, thus obviating the necessity for a run with 10% scan. From the results shown for the 24 scanned circuits, the same flip-flops were selected for scan by both OPUS and E-STG for 4 of the circuits, and hence exactly the same test generation results are produced for both algorithms. We now observe the performance of the two algorithms on the remaining circuits. We consider a test generation result better if the fault efficiency provided by one design is better than the other; and if the fault efficiency is exactly the same, then we opt for the design that has higher fault coverage. Thus, for the remaining 20 scanned circuits, better results were provided by E-STG over OPUS for 17 of the circuits. In particular, it is important to note the substantial improvements obtained for some circuits like s526(20%), for which the fault coverage (fault efficiency) can be improved from 51%(56%) provided by OPUS to 93%(97%) provided by E-STG.
Table 3: Original Test Generation Results Circuit s298 s344 s400 s420 s526 s641 s713 s820 s832 s953 s1238 s1423 s1488 s1494 s5378 s35932
Det 265 314 336 28 51 404 476 812 816 89 1283 555 1439 1439 3152 34719
Undet 26 8 9 152 17 61 105 31 46 990 72 11 27 27 148 3856
Abort 17 20 81 275 487 2 0 7 8 0 0 949 20 20 1303 519
Time(s) 389 489 1888 6235 10883 89 23 433 500 147 14 20359 1238 1238 27078 7172
Vecs 306 117 1644 16 34 219 177 928 967 14 478 88 1124 1124 949 317
We now provide experimental evidence that the heuristics introduced to handle large circuits do not lead to a sub-
Table 4: Comparison of the scan algorithms Circuit
% scan
s298 s298 s344 s344 s400 s400 s420 s420 s526 s526 s641 s641 s820 s832 s1423 s1423 s1488 s1488 s1494 s1494 s5378 s5378 s35932 s35932
10 20 10 20 10 20 10 20 10 20 10 20 20 20 10 20 10 20 10 20 10 20 10 20
Det 292 293 314 331 396 400 36 52 280 283 405 464 850 855 870 1028 1438 1477 1449 1473 4257 4506 35100 35108
Undet 15 14 8 10 16 17 154 167 20 217 62 3 0 14 11 12 28 6 40 26 196 81 3984 3984
OPUS Abort Time(s) 1 39 1 25 20 472 1 52 12 395 7 213 265 5737 236 5262 255 5273 245 5224 0 48 0 13 0 98 1 98 634 14795 475 11063 20 1261 3 278 17 799 7 349 150 4089 16 548 10 6166 2 6211
stantial loss in the quality of the resulting design. For this, we consider some ISCAS 89 circuits on which it is feasible to run both the expensive (using the faulty circuit information) and the simplified algorithms (using only good circuit information) and present the results provided by the two algorithms. This data is presented in Table 5. The data shows that while it is likely that the same set of flipflops would be identified for scan, the simplified algorithm may actually work better than the expensive faulty circuit information-based algorithm. This may seem counterintuitive at first, but can be explained by the loss in accuracy of the faulty information-based algorithm (unlike the good circuit information-based algorithm) when the numerous state transitions involved in multiple faulty circuits are considered.
Vec 581 231 95 97 1780 764 18 16 558 264 195 250 920 914 155 213 1105 1364 1159 766 1665 1477 373 399
Det 302 304 328 337 386 414 44 96 326 517 408 464 850 855 943 1127 1439 1484 1449 1492 4355 4428 35109 35110
Undet 6 4 9 4 14 10 141 141 20 22 59 3 0 14 11 10 28 1 40 13 141 119 3984 3984
E-STG Abort Time(s) 0 23 0 6 5 177 1 28 24 642 0 42 270 5967 218 4858 209 4643 16 996 0 41 0 12 0 98 1 98 561 13972 378 8626 19 1240 1 469 17 799 1 363 107 2858 56 1476 1 5951 0 5972
Vec 653 398 95 94 398 321 14 28 241 1155 205 255 920 914 235 254 1124 1327 1159 1241 1684 960 517 366
cuit graph. Based on this model, a new formulation of the partial scan design problem has been presented in terms of the enhanced state transition graph (E-STG). This is utilized to identify state transitions that need to be created between desired states (identified by the test generation algorithm) and known reachable states (identified by fault simulation). These transitions are then introduced by the scan flip-flop selection algorithm. We also presented heuristics based on good circuit information for the effective handling of large circuits. Experimental results were presented to justify the heuristics introduced and also to show that significant improvements in the quality of the resulting partially scanned circuit can be obtained for our process.
References 5 Conclusions In this paper, we have introduced a model that captures the effects of the introduction of scan into the original cir-
[1] E. Trischler, “Incomplete scan path with an automatic test generation methodology,” in Proceedings of the International Test Conference, pp. 153–162, November 1980.
Table 5: Comparison of the faulty circuit and the good circuit algorithms Circuit s298 s344 s400 s420 s641
% scan 20 20 20 20 20
Det 303 337 408 96 464
Faulty Ckt. Info. Undet Abort Time(s) 4 1 24 4 1 26 13 3 91 141 218 4856 3 0 13
[2] V. Chickermane and J. H. Patel, “An optimization based approach to the partial scan design problem,” in Proceedings of the International Test Conference, pp. 377–386, September 1990. [3] V. Chickermane and J. H. Patel, “A fault oriented partial scan design approach,” in Proceedings of the International Conference on Computer-Aided Design, pp. 400–403, November 1991. [4] K. S. Kim and C. R. Kime, “Partial scan by use of empirical testability,” in Proceedings of the International Conference on Computer-Aided Design, pp. 314–317, November 1990. [5] K. S. Kim and C. R. Kime, “Partial scan flip-flop selection by use of empirical testability,” Journal of Electronic Testing, vol. 7, pp. 47–60, August/October 1995. [6] M. Abramovici, J. J. Kulikowski, and R. K. Roy, “The best flip-flops to scan,” in Proceedings of the International Test Conference, pp. 166–173, October 1991. [7] P. S. Parikh and M. Abramovici, “A cost based approach to partial scan design,” in Proceedings of the Design Automation Conference, pp. 225–259, June 1993. [8] P. S. Parikh and M. Abramovici, “Testability-based partial scan analysis,” Journal of Electronic Testing, vol. 7, pp. 61–70, August/October 1995. [9] V. D. Agrawal, K.-T. Cheng, D. D. Johnson, and T. Lin, “Designing circuits with partial scan,” IEEE Design & Test of Computers, vol. 5, pp. 8–15, April 1988. [10] H. K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovanni-Vincentelli, “An incomplete scan design approach to test generation for sequential machines,” in Proceedings of the International Test Conference, pp. 730–734, September 1988. [11] I. Park, D. S. Ha, and G. Sim, “A new method for partial scan design based on propagation and justification
Vec 305 76 368 28 250
Det 304 337 414 96 464
Only Good Ckt. Info. Undet Abort Time(s) 4 0 6 4 1 28 10 0 42 141 218 4858 3 0 12
Vec 398 94 321 28 255
requirements of faults,” in Proceedings of the International Test Conference, pp. 413–422, October 1995. [12] R. Gupta, R. Gupta, and M. A. Breuer, “Ballast: A methodology for partial scan design,” in Proceedings of the Fault Tolerant Computing Symposium, pp. 118– 125, June 1989. [13] A. Kunzmann and H.-J. Wunderlich, “An analytical approach to the partial scan problem,” Journal of Electronic Testing: Theory and Applications, pp. 163–174, May 1990. [14] K.-T. Cheng and V. D. Agrawal, “A partial scan method for sequential circuits with feedback,” IEEE Transactions on Computers, vol. 39, pp. 544–548, April 1990. [15] S. Bhawmik, C. J. Lin, K.-T. Cheng, and V. D. Agrawal, “Pascant: A partial scan and test generation system,” in Proceedings of the Custom Integrated Circuits Conference, pp. 17.3.1–17.3.4, May 1991. [16] D. H. Lee and S. M. Reddy, “On determining scan flip-flops in partial scan designs,” in Proceedings of the International Conference on Computer-Aided Design, pp. 322–325, November 1990. [17] S. Park and S. B. Akers, “A graph theoretic approach to partial scan design by k-cycle elimination,” in Proceedings of the International Test Conference, pp. 303–311, September 1992. [18] I. Pomeranz and S. M. Reddy, “Design and synthesis for testability of synchronous sequential circuits based on strong-connectivity,” in Proceedings of the Fault Tolerant Computing Symposium, pp. 492–501, June 1993. [19] S. E. Tai and D. Bhattacharya, “A three stage partial scan design method using the sequential circuit flow graph,” in Proceedings of the International Conference on VLSI Design, pp. 101–106, January 1994. [20] S. E. Tai and D. Bhattacharya, “A three-stage partial scan design method to ease atpg,” Journal of Elec-
tronic Testing, vol. 7, pp. 95–104, August/October 1995. [21] S. T. Chakradhar, A. Balakrishnan, and V. D. Agrawal, “An exact algorithm for selecting partial scan flip-flops,” in Proceedings of the Design Automation Conference, pp. 81–86, June 1994. [22] S. T. Chakradhar, A. Balakrishnan, and V. D. Agrawal, “An exact algorithm for selecting partial scan flip-flops,” Journal of Electronic Testing, vol. 7, pp. 83–94, August/October 1995. [23] P. Ashar and S. Malik, “Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications,” in Proceedings of the Design Automation Conference, pp. 77–80, June 1994. [24] T. Orenstein, Z. Kohavi, and I. Pomeranz, “An optimal algorithm for cycle breaking in directed graphs,” Journal of Electronic Testing, vol. 7, pp. 71–82, August/October 1995.
[28] S. Lee and K. G. Shin, “Design for test using partial parallel scan,” IEEE Transactions on ComputerAided Design, vol. 9, pp. 203–211, March 1990. [29] Y. Higami, S. Kajihara, and K. Kinoshita, “Partial scan design and test sequence generation based on reduced scan shift method,” Journal of Electronic Testing, vol. 7, pp. 115–124, August/October 1995. [30] S. T. Chakradhar and S. Dey, “Resynthesis and retiming for optimum partial scan,” in Proceedings of the Design Automation Conference, pp. 87–93, June 1994. [31] S. Dey and S. T. Chakradhar, “Design of testable sequential circuits by repositioning flip-flops,” Journal of Electronic Testing, vol. 7, pp. 105–114, August/October 1995. [32] D. Kagaris and S. Tragoudas, “Partial scan with retiming,” in Proceedings of the Design Automation Conference, pp. 249–254, June 1993.
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Abstract Selection of flip-flops that provide the best improvements in testability is a critical part of the partial scan design process. This paper describes a new technique for flip-flop selection that models the effect of scan in terms of the introduction of pseudo state transitions in the state transition graph. The identification of (desired) state transitions that provide for improved testability is based on an analysis of the known reachable states and desired states which ensure improved fault detection. Experiments are presented on the ISCAS 89 circuits to show significant improvements in the testability of the resulting partial scan design.
1 Introduction Partial scan design, in which a subset of flip-flops is selected to be scanned, provides a wide spectrum of design solutions that trade off testability for the overheads incurred by scan design. The overheads introduced by the incorporation of scan include area overheads and timing penalties. In partial scan design, a designer is typically interested in selecting the best set of flip-flops to be scanned under a given set of constraints.
1.1
Previous Work
Previous research on partial scan design can be categorized into three areas: flip-flop selection [1–25], test length reduction [26–29], and retiming [30–33]. Flip-flop selection is a crucial part of the design process and hence intensive research has been performed in this area [1–17, 19– 25]. The problem addressed in this paper is that of flip-flop selection during the partial scan design process. Previous methods for selecting flip-flops are based on one or several of the three following techniques: testability analysis This research was supported in part by the Semiconductor Research Corporation (SRC) under grant 95-DP-109, by the Office of Naval Research (ONR) under grant N00014-95-1-1049, and by an equipment grant from Hewlett-Packard.
W. Kent Fuchs School of Electrical and Computer Engineering Purdue University West Lafayette, IN 47907-1285 [email protected]
[1, 2, 4–8], structural analysis [2, 3, 12–17, 19–25], and test generation [3, 9–11]. Early partial scan design employed a simple testability-based method for the selection of flipflops [1]. Schemes based on sophisticated testability analysis have since been proposed [6–8]. Several techniques that employ testability analysis in conjunction with other schemes are also known [4, 5]. However, one of the main problems associated with testability analysis-based techniques is that the fault coverage achieved for circuits with complex structure may not be satisfactory. Structural analysis has been used to remove all feedback loops in a given circuit, resulting in a simpler circuit structure to be handled by the test generation algorithm. The first approach in this direction is the removal of all feedback loops, so that the resulting circuit works in a pipelined fashion [12, 13]. Another approach, called cycle-breaking, removes all feedback loops except self-loops [14–17, 19–24]. The cycle-breaking algorithm is simple and relatively effective. However, it has been observed that even if all cycles are broken, the algorithm may not cover all faults for some circuits [3]. More importantly, for many circuits, it may be infeasible or unnecessary to break all feedback loops to achieve desirable fault coverages [3]. Cycle cutting has also been accomplished by using intensive valid state analysis to assess the impact of cutting specific cycles [25]. Test generation-based methods exploit information available from the test generator to drive the scan selection process [3, 9–11]. The main advantage of using test generation-based techniques is that it is possible to target specific fault detection objectives rather than simplify the circuit (by structural analysis) or improve testability of specific regions in the circuit (by testability analysis). This typically results in the expensive computational and storage requirements associated with pure test generation-based techniques [11]. For circuits with reset state knowledge (typically small in size), effective solutions are known [10]. An efficient technique that exploits information available from the test generator, but does not suffer from the computational limitations of the test generation-based techniques, is the OPUS partial scan selection technique [3]. Here, the
computational requirements are reduced by the use of structural analysis in conjunction with the test generation information.
1.2
Summary of Our Contributions
In this paper, we provide a new partial scan selection method based on the modeling of the scanning of a flipflop, by the introduction of pseudo state transitions in the state transition graph of the original circuit to obtain an enhanced state transition graph (E-STG). This model is effectively utilized to achieve desirable fault coverage by using the introduced state transitions for the efficient navigation of the machines to desirable states. For each fault that is aborted by the test generation procedure, it is first noted whether the fault is aborted due to a state justification failure or a propagation failure. In the case of propagation failures, information on states that show the fault effects is recorded. This is used to introduce pseudo state transitions that enable the detection of the fault under consideration. For justification failures, information is collected on states that, when reached, can detect the fault under consideration. This phase is similar to the justification and propagation requirement identification phases proposed earlier [11]. In addition to this information, we collect information about the states that are already known to be reachable. This information is then used to create the most effective (least expensive) pseudo state transition between a state already known to be reachable and a desired state. The desired state is thus made reachable by the help of the introduced pseudo state transition and ensures the detection of the targeted fault. Experimental results are presented on large ISCAS 89 circuits and are compared to the OPUS partial scan selection algorithm [3] (a test generation-based technique that is capable of handling large circuits) and shown to be superior. Important contributions of this work are listed below.
It provides a theoretical model for analyzing the effects of introduction of scan in the original state transition graph. Previous methods for partial scan selection based on test generation information have not been able to exploit the knowledge of reachable states, because of the lack of such a model. It provides techniques that effectively apply test generation-based partial scan selection to large circuits. The identification of desirable state transitions based on test generation and fault simulation knowledge provides a basis for flip-flop selection. The computational and storage requirements are effectively reduced by showing that good circuit information alone (as opposed to multiple faulty
circuit information) can be used to determine the desired state transitions.
2 Modeling of Scan Effects in the STG This section provides the theoretical model that allows for incorporating the effects of scan in the original state transition graph.
2.1 Preliminaries Let the circuit under consideration consist of NS flipflops, NI primary inputs and NO primary outputs. Hence, the state can be completely expressed as an NS -tuple whose entries are 0s or 1s. It may also be noted that X values are often used to compactly enumerate multiple states. A value of X at one of the positions means that the flip-flop corresponding to that position has either a 0 or a 1 value. Let us indicate an input tuple by Ij = (I N1 ; I N2 ; : : : ; I NNI ) and an output tuple by Oj = (OP1 ; OP2 ; : : : ; OPNO ). We note that I Nj ; 8 j 2 (1; : : : ; NI ) and OPj ; 8 j 2 (1; : : : ; NO ) can take the values of 0 or 1 or X . Let us further indicate a state tuple by Sj = (F F1 ; F F2 ; : : : ; F FNS ) meaning that F Fj ; 8 j 2 (1; : : : ; NS ) is the value of flip-flop j and may have the value 0, 1 or X . Definition 1 (State Transition Graph (STG)) The state transition graph is defined as the graph G(V ; E ), where the set of vertices V is the set of all possible states (2NS in number) and an edge is of the form ((Si ; Sj )(Ii ; Oj )) where Si and Sj are state tuples, Ii is an input tuple, and Oj is an output tuple, and the machine transfers from state Si to state Sj upon application of the input Ii and produces an output Oj .
2.2 Pseudo State Transitions for Modeling Scan We now define the enhanced STG that captures the incorporation of scan into the original STG. Let the number of flip-flops chosen for scan be NR and the set of those flipflops be given by S F F = (S F F1 ; S F F2 ; : : : ; S F FNR ), where S F Fj ; 8j 2 (1; 2; : : : ; NR ) indicates the position number of a flip-flop in the original state tuple. Definition 2 (Enhanced State Transition Graph (E-STG)) In addition to the set of inputs and outputs from the original STG, the enhanced state transition graph has two pseudo inputs called P S I N1 and P S I N2 , and NR pseudo outputs called (P S OP1 ; P S OP2 ; : : : ; P S OPNR ). The state continues to be expressed as an NS tuple. Hence, the
set of vertices remains the same. The new input and output tuples are therefore given by : Input : Ij = (I N1 ; I N2 ; : : : ; I NNI ; P S I N1 ; P S I N2 ). Output : Oj = (OP1 ; OP2 ; : : : ; OPNO ; P S OP1 ; P S OP2 ; : : : ; P S OPNR ). The new state transitions are defined as follows :
For each transition ((Sx ; Sy )(Ii ; Oj )) from the original state transition graph, create a transition ((Sx ; Sy )(Ik ; Ol )) in the enhanced state transition graph, where the first NI elements of the tuple Ik are exactly the same as in Ii and the last two tuples are set to 0 and 0, and the first NO elements of the tuple Ol are the same as in Oj and the last NR elements of the tuple are set to the value X . For each state Sj = (F F1 ; F F2 ; : : : ; F FNS ), create a pseudo transition given by ((Sj ; Sj )(Ix ; Oy )), where Ix = (X; X; : : : ; X; 1; 0), i.e., P S I N1 = 1 and P S I N2 = 0 and every other position equal to the X value, and the output tuple Oy = (X; X; : : : ; X; F FSF F1 ; F FSF F2 ; : : : ; F FSF FNR ). For each state pair Si & Sj such that the only positions where the values of their tuples are different belongs to the set S F F = (S F F1 ; S F F2 ; : : : ; S F FNR ), introduce the two pseudo transitions ((Si ; Sj )(Ix ; Oy )) and ((Sj ; Si )(Ix ; Oy )), where Ix = (X; X; : : : ; X; X; 1), i.e., P S I N1 = X and P S I N2 = 1 and every other position equal to the X value, and the output tuple Oy = (X; X; : : : ; X; X ), i.e., the output tuple consists of all positions taking the value X .
2.3
Intuition Behind the Model
The introduction of scan provides for two improvements in the state machine testability. The first arises from the observability of the state lines and the second comes from the additional control ability provided to guide the machine to desirable states. The pseudo transitions introduced in our modeling phase are intended to capture exactly these two improvements. The pseudo inputs are used to capture the operation of the machine in three modes :
P S I N1
=0
; P S I N2
= 0:
The original machine
2.4 Example Illustrating the Model As an example to illustrate the definition of the E-STG, consider a finite state machine whose state transition graph is shown in Figure 1. This machine has 3 flip-flops, 1 input and 1 output. Hence, there are eight states in the machine. A state transition is indicated by an arrow from the starting state to the final state, and the input causing the transition and the output produced by it are indicated by an I =O symbol associated with the arrow. For example, there exists a state transition between states 000 and 001 caused by an input symbol X and producing the output value 0. This means that either of inputs 0 or 1 will transfer the machine from the state 000 to the state 001 producing an output of 0. Let us now assume that the flip-flop corresponding to the most significant (leftmost) bit is scanned. The effects of this scanning have been captured by the enhanced STG shown in Figure 2. The input tuple size has been increased from 1 to 3, and the output tuple size has been increased from 1 to 2 because of the scanning of 1 flip-flop. The pseudo transitions introduced have been shown by the dotted arcs, while the transitions present in the original STG are in solid arcs. The self-loop transitions indicated by the dotted arcs are the pseudo transitions corresponding to the machine mode with P S I N1 = 1; P S I N2 = 0. The eight transitions between the state pairs (000)(100), (001)(101), (010)(110) and (011)(111) are the pseudo transitions corresponding to the machine mode with P S I N1 = X; P S I N2 = 1. The fact that the E-STG has considerably more arcs than the original STG helps in the partial scan design process because it substantially simplifies the process of navigating through the state machine.
3 Partial Scan Design Strategy In this section, we describe our partial scan selection techniques based on the new model of the scan process. Methods for effective partial scan selection in large circuits are presented.
3.1 New Formulation of the Partial Scan Flip-flop Selection Problem
STG is captured by this mode.
P S I N1
=1
; P S I N2
= 0 : This scan mode captures
the increased observability provided by the addition of scan.
= X; P S I N2 = 1 : This scan mode captures the ability of the machine to be transferred to specific states because of the addition of scan.
P S I N1
We can now formulate the partial scan design problem in terms of the E-STG as the identification of the best set of flip-flops that gives an E-STG with highest fault detection capability. Hence, the problem of partial scan flipflop selection can be effectively solved by choosing a set of flip-flops that introduces the most desirable state transitions, i.e., the state transitions that ensure the maximum
000 X/0
X/0
100 X/0
X/0 001
111
011
101 X/0
X/0
X/0
X/0
010
110
Figure 1: Original State Transition Graph
X10/X1
XX1/XX X10/X0 000 X10/X0
X00/0X
100
X10/X0 XX1/XX
X00/0X
X00/0X
X00/0X
X10/X0
X00/0X
X00/0X
X10/X1
001 011
X10/X1
101 X10/X1X00/0X
010
111
X00/0X
110 XX1/XX
XX1/XX True Transitions Pseudo Transitions Figure 2: Enhanced State Transition Graph
number of detections. In order to determine the state transitions that are most desirable, we gather information from the test generation algorithm identifying states that, when reached, ensure the detectability of specific faults. An exhaustive run of the test generator (with large backtrack and time limits) is not required for this identification. We shall then couple this desired state information with information about states that are already known to be reachable (this information is shown to be easily gathered by a fault simulation run). Knowledge of the known reachable states is then used in conjunction with the desirable state information to identify the introduction of profitable state transitions.
3.2
Identification of the Desired States from the Sequential Test Generation Algorithm
In this work, it is assumed that sequential test generation is performed in two steps of forward fault propagation and backward state justification. Specifically, in our experimentation, the HITEC sequential test generation program [34] was used. The sequential test generation aims to propagate the fault effect to at least one primary output and to justify signal values assigned during the propagation process. Suppose that the test generation algorithm fails to generate a test for a particular fault that is not redundant in the full-scan version of the circuit. The algorithm may have failed for either of two reasons. There may be a propagation failure if fault effects cannot be propagated to a primary output (possibly because of a specified time/backtrack limit). Alternatively, there may be a justification failure if no justification sequence is found (again, possibly because of a specified time/backtrack limit) to transfer the faulty/good machine pair to any desired state pair from which there is a propagation path. It has been observed in the past [10, 11] and confirmed by our experiments that the backward justification phase presents the main difficulty in fault detection. Hence, for each fault for which there is a propagation failure, there exist states (by a state, we mean faulty/good state pair) from which the introduction of a P S I N1 = 1; P S I N2 = 0 transition ensures the detection of that fault. More important is the case of justification failures. For each such failure, a set of states (again, by a state, we mean faulty/good state pair) exists, which, when reached, ensures the detection of the fault (because the test generator has already been able to find a set of inputs that ensures the detection of the fault from such a state).
above. In addition, the set of known reachable states is also obtained. The test generation algorithm provides a set of vectors that detects a subset of the entire set of faults. These vectors often transfer the machines (faulty/good) to states that are near (a measure for the distance will be presented shortly) the desired states (identified from the test generation phase). An intuitive explanation of this phenomenon is found in the fact that the faults in a circuit are not entirely uncorrelated; this implies similarities in the state spaces of various faulty circuits. Hence, a set of reachable states is found for each faulty/good machine pair through fault simulation of the already available vectors. This consists of the known reachable state information.
3.4 Computation of the Best Flip-Flops to Scan Given the sets of known reachable states and the sets of desirable states for each of the faults that were not detected, we present an algorithm to find the best set of flip-flops to scan. We now present a measure of the distance between a pair of faulty/good states. This is necessary because a lesser distance indicates a smaller number of flip-flops to scan to achieve the desired state. The distance between a pair of states (F S1 =GS1 ) and (F S2 =GS2 ), where F S1 = (F F 11 ; F F 12 ; : : : ; F F 1NS ) GS1 = (GF 11 ; GF 12 ; : : : ; GF 1NS ) F S2 = (F F 21 ; F F 22 ; : : : ; F F 2NS ) and GS2 = (GF 21 ; GF 22 ; : : : ; GF 2NS ) is
PNi
((
Distance
S
=1
)(
)) = (( 1i 1i ) ( 2i (( 1 1 ) ( 2 2 ))
F S1 =GS1 ; F S2 =GS2
F aulty
& &
where F aulty
GoodDist
GoodDist
def ined as in T able
1
FF
=GF
X =Y
; FF
; X =Y
=GF
2i ))
is
:
In Table 1, an entry of 0 indicates that no scan is required for making the transition at that bit position, 1 indicates that scan is required for making the state transition, and c ( = NS + 1) means that even the introduction of scan cannot create the required state transition. The algorithm to assign a profit for each flip-flop in the circuit based on the possible improvements in detection provided by that flipflop is presented in Figure 3. The intuition behind the reduced weighting for flip-flops involved in the creation of transitions for tackling propagation failures is that the main problem in sequential test generation is caused by justification failures. We show through our experimentation that the ordering of flip-flops generated through our scheme is indeed superior.
3.5 Effective Algorithm for Large Circuits 3.3
Identification of Known Reachable States
The identification of states that are desired to be reachable is performed by the test generation algorithm stated
The algorithm for assigning profits to flip-flops cannot be directly applied to large circuits, because of the overheads involved in the storage of the desired and known reachable
;
// Input: Desired states and known reachable states for each fault. // Function: Assigns profits to all the flip-flops based on an analysis of the detections possible by scanning them. // Routine Is propagation failure(f) gives a true or a false depending on whether the fault is a propagation failure; // if not a propagation failure, it has to be a justification failure. // Routine Desired states(f) gives the set of desired states for the fault f. // Routine Known reachable states(f) gives the set of known reachable states for the fault f. // Routine Get state with max detections(Desired states(f)) // returns the state with the max number of detections and the number of detections for the fault f. // Routine Get least distance state pair(Known reachable states(f), Desired states(f)) // returns the state pair with minimum distance between them and also the distance. // Routine Assign prop profits(S max, det) finds all ffs with a detection in // the state S max and increments the profit of each such ff by 5 NS =det. // Routine Assign just profits(S from, S to, dist) finds all ffs that have caused the distance between // S from and S to and increments the profit of each such ff by 10 NS =dist. for each fault f in the aborted fault list do if (Is propagation failure(f) == true) (S max, det) = Get state with max detections(Desired states(f)); Assign prop profits(S max, det); else (S from, S to, dist) = Get least distance state pair(Known reachable states(f), Desired states(f)); Assign just profits(S from, S to, dist); Figure 3: The Flip-flop profit assignment algorithm
state information. We now present heuristics for handling large circuits and show experimentally that the use of these heuristics does not result in a loss of the final partial scan design quality. We first introduce the notion that the knowledge of desired and reachable states need not be gathered for the faulty circuits, i.e., we claim that it suffices to gather information about the desired and reachable states in the good circuit alone. 3.5.1 Good Circuit Information is Enough! For making use of the good circuit information, we now introduce the crucial distance computation measure. Note that the state consists of just the good circuit state alone. Distance between a pair of states (GS1 ) and (GS2 ), where GS1 = (GF 11 ; GF 12 ; : : : ; GF 1NS ) GS2 = (GF 21 ; GF 22 ; : : : ; GF 2NS ) is
PN
((
Distance
S
i=1
) ( )) = (( 1i ) ( 2i )) (( 1 ) ( 2 ))
GS1 ; GS2
GoodDist
where GoodDist as in T able
2
:
GF X
; GF
; X
;
is def ined
The entries in Table 2 have the same meaning as before. The desired state information identification phase (performed inside the sequential test generation algorithm) now collects the desired state information only for the good circuit. Similarly, the known reachable state information identification (performed with the help of fault-simulating existing vectors) is performed only for the good circuit. This results in a major reduction in the overhead involved in storing the faulty circuit reachable states. In addition, a saving in the fault simulation cost is also achieved. To further reduce the storage requirements, we restrict the number of desired states per fault to one. Since the requirements on state lines in the justification process are reduced as the test generation process moves back (left) in the reverse-time process, we identify desired state information of only the leftmost time frame. Further, only a single state is identified for propagation requirements. This reduction in the amount of state information required by our algorithm provides significant savings in the memory requirements, thus making it feasible to run our algorithm on large circuits.
Table 1: Faulty&GoodDist Computation Table To ! From # 0/0 0/X 0/1 X/0 X/X X/1 1/0 1/X 1/1
0/0 0/X 0/1 X/0 X/X X/1 1/0 1/X 1/1 0 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1
c c 0 c c c c c c
0 1 1 0 1 1 0 1 1
0 0 0 0 0 0 0 0 0
1 1 0 1 1 0 1 1 0
c c c c c c 0 c c
1 1 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1 0
Table 2: GoodDist Computation Table To ! From # 0 X 1
0
X
1
0 1 1
0 0 0
1 1 0
4 Experimental Results In this section, we present experimental results comparing our scan selection technique with the test generation/structural analysis-based technique OPUS [3]. We also present data supporting the claim that the heuristics that were introduced for enabling the method to handle large circuits do not result in a significant loss in the quality of the partial scan solution. The test generation algorithm that was used in our experimentation was the HITEC test generation algorithm [34]. The PROOFS fault simulator [35] was used for the reachable state analysis. We first present the results of the test generation algorithm on the original ISCAS 89 circuits. These results are presented in Table 3. The time limit and backtrack limit for each fault were set to be 20 seconds and 100000 respectively in each of the circuits, except for s35932, because of the excessive amount of time required for test generation for it. For this circuit, a 2-second time limit and a backtrack limit of 10000 were placed. The columns in the table indicate the circuit name, the number of detected faults, the number of faults proven to be undetectable by the test generator, the number of aborted faults, the time taken in seconds, and the number of vectors respectively. From the set of benchmarks in Table 3, we now run the partial scan selection experiments for the circuits with at
least one aborted fault. We compare the performance of the test generation-based OPUS algorithm [3] with that of our algorithm (E-STG). These results are presented in Table 4, where we set the number of flip-flops to be scanned to 10% and 20% of the total number of flip-flops in the original circuit, and observe the improvements provided by scan. The table does not show the time taken for the scan selection phase itself, because for both of the algorithms, those times are too small to list (of the order of 0.1sec). For circuits for which only the results for 20% scan are shown, the circuits had less than or equal to 5 flip-flops, thus obviating the necessity for a run with 10% scan. From the results shown for the 24 scanned circuits, the same flip-flops were selected for scan by both OPUS and E-STG for 4 of the circuits, and hence exactly the same test generation results are produced for both algorithms. We now observe the performance of the two algorithms on the remaining circuits. We consider a test generation result better if the fault efficiency provided by one design is better than the other; and if the fault efficiency is exactly the same, then we opt for the design that has higher fault coverage. Thus, for the remaining 20 scanned circuits, better results were provided by E-STG over OPUS for 17 of the circuits. In particular, it is important to note the substantial improvements obtained for some circuits like s526(20%), for which the fault coverage (fault efficiency) can be improved from 51%(56%) provided by OPUS to 93%(97%) provided by E-STG.
Table 3: Original Test Generation Results Circuit s298 s344 s400 s420 s526 s641 s713 s820 s832 s953 s1238 s1423 s1488 s1494 s5378 s35932
Det 265 314 336 28 51 404 476 812 816 89 1283 555 1439 1439 3152 34719
Undet 26 8 9 152 17 61 105 31 46 990 72 11 27 27 148 3856
Abort 17 20 81 275 487 2 0 7 8 0 0 949 20 20 1303 519
Time(s) 389 489 1888 6235 10883 89 23 433 500 147 14 20359 1238 1238 27078 7172
Vecs 306 117 1644 16 34 219 177 928 967 14 478 88 1124 1124 949 317
We now provide experimental evidence that the heuristics introduced to handle large circuits do not lead to a sub-
Table 4: Comparison of the scan algorithms Circuit
% scan
s298 s298 s344 s344 s400 s400 s420 s420 s526 s526 s641 s641 s820 s832 s1423 s1423 s1488 s1488 s1494 s1494 s5378 s5378 s35932 s35932
10 20 10 20 10 20 10 20 10 20 10 20 20 20 10 20 10 20 10 20 10 20 10 20
Det 292 293 314 331 396 400 36 52 280 283 405 464 850 855 870 1028 1438 1477 1449 1473 4257 4506 35100 35108
Undet 15 14 8 10 16 17 154 167 20 217 62 3 0 14 11 12 28 6 40 26 196 81 3984 3984
OPUS Abort Time(s) 1 39 1 25 20 472 1 52 12 395 7 213 265 5737 236 5262 255 5273 245 5224 0 48 0 13 0 98 1 98 634 14795 475 11063 20 1261 3 278 17 799 7 349 150 4089 16 548 10 6166 2 6211
stantial loss in the quality of the resulting design. For this, we consider some ISCAS 89 circuits on which it is feasible to run both the expensive (using the faulty circuit information) and the simplified algorithms (using only good circuit information) and present the results provided by the two algorithms. This data is presented in Table 5. The data shows that while it is likely that the same set of flipflops would be identified for scan, the simplified algorithm may actually work better than the expensive faulty circuit information-based algorithm. This may seem counterintuitive at first, but can be explained by the loss in accuracy of the faulty information-based algorithm (unlike the good circuit information-based algorithm) when the numerous state transitions involved in multiple faulty circuits are considered.
Vec 581 231 95 97 1780 764 18 16 558 264 195 250 920 914 155 213 1105 1364 1159 766 1665 1477 373 399
Det 302 304 328 337 386 414 44 96 326 517 408 464 850 855 943 1127 1439 1484 1449 1492 4355 4428 35109 35110
Undet 6 4 9 4 14 10 141 141 20 22 59 3 0 14 11 10 28 1 40 13 141 119 3984 3984
E-STG Abort Time(s) 0 23 0 6 5 177 1 28 24 642 0 42 270 5967 218 4858 209 4643 16 996 0 41 0 12 0 98 1 98 561 13972 378 8626 19 1240 1 469 17 799 1 363 107 2858 56 1476 1 5951 0 5972
Vec 653 398 95 94 398 321 14 28 241 1155 205 255 920 914 235 254 1124 1327 1159 1241 1684 960 517 366
cuit graph. Based on this model, a new formulation of the partial scan design problem has been presented in terms of the enhanced state transition graph (E-STG). This is utilized to identify state transitions that need to be created between desired states (identified by the test generation algorithm) and known reachable states (identified by fault simulation). These transitions are then introduced by the scan flip-flop selection algorithm. We also presented heuristics based on good circuit information for the effective handling of large circuits. Experimental results were presented to justify the heuristics introduced and also to show that significant improvements in the quality of the resulting partially scanned circuit can be obtained for our process.
References 5 Conclusions In this paper, we have introduced a model that captures the effects of the introduction of scan into the original cir-
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Table 5: Comparison of the faulty circuit and the good circuit algorithms Circuit s298 s344 s400 s420 s641
% scan 20 20 20 20 20
Det 303 337 408 96 464
Faulty Ckt. Info. Undet Abort Time(s) 4 1 24 4 1 26 13 3 91 141 218 4856 3 0 13
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