PDF (Supplemental Material)
22.2 An Octave-Range Watt-Level Fully Integrated CMOS Switching Power Mixer Array for Linearization and Back-Off Efficiency Improvement
Shouhei Kousai*1*2 and Ali Hajimiri*1 *1 California Institute of Technology *2 Toshiba Corporation
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Outline • • • • • •
Background Power mixer array Power mixer details Block diagram and operation modes Measurement results Conclusion
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Primary Constraints in Wireless Communication
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Pros and Cons of Conventional Approaches Efficiency 1
Supply modulation Out-phasing Digital PA
0.5
Doherty
Class-AB
• Class-AB – Poor efficiency
• Doherty & Out-phasing – Phase shifter
• Supply modulation – DC-DC converter
• Digital PA – Aliasing & output noise
0 Output Power
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Outline • • • • • •
Background Power mixer array Power mixer details Block diagram and operation mode Measurement results Conclusion
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Power Mixer Array Transmitter Subsystem • Power generation is done by several identical mixers • Power mixer array subsumes some of the functionality of a conventional transmitter
Envelope (BB)
t
RF Output t
t
Phase (LO) t
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Segmented Power Generation • When a symbol does not require full output power some power generation blocks are turned off 1
Q 2
3
Ι
n
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Back-Off Efficiency Improvement • Power efficient and compatible with CMOS processes • CMOS is good at switching on and off 1
Power Consumption 2
3
Output Power n
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Linearity Improvement
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Linearity Improvement
V1
1
V V2
2
3
V Vk n
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Linearity Improvement • Linearity improves as the output increases
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
BB Input Signal Generation • Input signals are pulse shaped to avoid spurious and alias problems Analog residue of the BB envelope
Filtered Digital BB Pulse
BB Envelope
RF Output t
Phase (LO) t
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
BB Circuit Sharing • BB circuits such as DAC and LPF can be shared by using switch
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Output Network and Signal Combination • Transformer is suitable for a large impedance transformation ratio • Output current of the power mixers can be linearly combined at the output network
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Outline • • • • • •
Background Power mixer array Power mixer details Block diagram and operation mode Measurement results Conclusion
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Power Mixer • Current commuting mixer
• Boost the voltage swing & output impedance • Amplitude modulation – “Linear” Amplitude modulation – Large bandwidth
• Switching operation – High Efficiency – Low Noise
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Transient Waveform of Power Mixer • Peak efficiency = 60%, Peak power = 33dBm @ 1.8 GHz
8
[V, A]
6 4 2 0 -2 0
0.2
0.4
0.6 time [ns]
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
0.8
1
1.2
Gain and Non-Linearity of Power Mixer • The transconductance and the current gain is non-linear to the differential mode of the input voltage (VDIFF)
iLO iLO,S
VDIFF
iRF iLO 1
VDIFF
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
1. Class-AB Operation • These non-linearities can cancel each other • Improved back-off efficiency
iLO iLO,S VCM
VDIFF
iRF iLO 1
VDIFF
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
2. Baseband Replica Linearizer • Dynamically match the power mixer core and BB replica amplifier using feedback iRF+
M8
M7
M3
Baseband Replica Amplifier
Power Mixer Core iRF-
X
M4
M5
BBout-
M6
LBB+
iLO+
RCM
BBout+ M10 Y
iLO-
RCM
M11
LBB-
I DC LO+
LO-
M1
M2
LBB+
CM
LBB-
R2
BBinBBin+
R1
+
CM+ Vref R1
CM-
+
+
+
BBout+
BB Replica
BBout-
R2
Analog BB Replica Linearizer © 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Outline • • • • • •
Background Power mixer array Power mixer details Block diagram and operation modes Measurement results Conclusion
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Block Diagram of the Implemented System On-Chip
LBB+
Iout+
CM
Iout
LBB-
PM0
C1
LBB+ 6 CM 6 LBB-
Analog BB Distributor
VDD PM13
1:2
Analog BB Replica Linearizer Array
6 PM14
C2
6
6
BBin+ BBin-
6
6
Bypass
Envelope (BB)
Digital Controller
LO-
LO+
PM15
Digital LO Distributor PAD
Digital Control
+ Phase (LO)
RF Output t
t t © 2009 IEEE International Solid-State Circuits Conference
RLoad
© 2009 IEEE
1. Baseline Analog (BA) Mode • Class-AB operation for linearity and efficiency improvement • Equivalent to one large power mixer Power Mixer Array Current
Iout+ Iout
Envelope (BB)
PM0
BBin+
Input Amplitude (BB Envelope)
PM13
BBin
Output Amplitude (RF)
PM14
Digital Controller
LO-
LO+
PM15
Digital LO Distributor
+ Phase (LO) © 2009 IEEE International Solid-State Circuits Conference
Input Amplitude (BB Envelope)
© 2009 IEEE
2. Linearized Analog (LA) Mode • One large power mixer with feedback linearizer Power Mixer Array Current
Input Amplitude (BB Envelope)
LO-
LO+
Output Amplitude (RF)
Input Amplitude (BB Envelope)
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
3. Efficient Segmented (ES) Mode • Segmented power generation for linearity and efficiency improvement Power Mixer Array Current
Input Amplitude (BB Envelope)
LO-
LO+
Output Amplitude (RF)
Input Amplitude (BB Envelope)
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Die Photo
Analog BB Distributor
Analog BB Replica Linearizer Array
• Fully-integrated in a 130nm CMOS Technology
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Outline • • • • • •
Background Power mixer array Power mixer details Block diagram and operation modes Measurement results Conclusion
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Frequency Response • PAE is larger than 40% from 1.5 to 2 GHz • Output power is larger than 1W from 1.2 to 2.4 GHz 50
43%
32
40
31
30
+31.4 dBm
30 29
20 10
Output power PAE
28 1
1.5
2
PAE [%]
Output power [dBm]
33
0 2.5
Frequency [GHz]
LO input power = +3 dBm BB input(0-p, single) = 450mV © 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Gain and PAE for Different Operation Mode • BA and LA mode have very high linearity • ES mode and BA mode show improved efficiency Reference BA Mode LA Mode ES Mode
2 1
BA Mode LA Mode ES Mode
50 40 PAE [%]
Conversion Gain (Normarized) [dB]
3
0 -1 -2
30 20 10
-3 -4
0 -10
0
10
20
30
40
Output Power [dBm ]
-10
0 10 20 30 Output Power [dBm]
Frequency = 1.8 GHz, CW
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
40
Linearity Robustness • LA and ES modes are robust to power mixer linearity
Gain (Normarized) [dB]
VCM = 0.4V VCM = 0.45V VCM = 0.5V BA Mode
3
LA Mode
3
2
2
2
1
1
1
0
0
0
-1
-1
-1
-2
-2
-2
-3
-3
-3
-4
-4
-4
-10
0 10 20 30 40 Output Power [dBm ]
-10
0
10
20
ES Mode
3
30
40
Output Power [dBm ]
-10
0
10
30
Output Power [dBm ]
Frequency = 1.8 GHz, CW © 2009 IEEE International Solid-State Circuits Conference
20
© 2009 IEEE
40
EVM & PAE for 16QAM Modulation 30 BA Mode LA Mode ES Mode
BA Mode LA Mode ES Mode
25 PAE[%]
EVM[%]
10
5
20 15 10 5
0
0 10
15
20
25
30
Average Output Power [dBm]
Frequency = 1.8 GHz Symbol Rate = 50 kSym/s
10
15
20
25
30
Average Output Power [dBm]
BA Mode LA Mode ES Mode Pout [dBm] +27.1 +27.6 +26.4 PAE
25%
18%
26%
EVM
4.3%
5.0%
4.5%
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
LO Leakage and Output Power Range • More than 100dB output power range is achieved BA Mode, w/ DC Offset Adj. BA Mode LA Mode ES Mode
-60
12
-65
10
16QAM EVM [%]
LO Leak [dBm]
Frequency = 1.8 GHz # of the Power Mixer = 1 VCM = 0.2V
-70 -75 -80 -85 -90 -95 -1.2 -0.8 -0.4
0
0.4
0.8 1.2
Differential Input [mV]
© 2009 IEEE International Solid-State Circuits Conference
8 6
103dB
4 2 0 -100 -80
-60
-40
-20
0
20
Average Output Power [dBm]
© 2009 IEEE
40
WCDMA (PAPR = 3.5 dB, 3.84Mcps) BA Mode, Band III(1.75GHz) 10
[dBm/10kHz]
0 -10 -20 -30 -40 -50 -15
-10 -5 0 5 10 Frequency Offset [MHz]
Band I Frequency [GHz] 1.95
15
Band II Band III 1.83 1.75
Power [dBm] PAE
+28.4 28%
+28.3 28%
+28.3 30%
EVM
3.7%
3.5%
2.9%
© 2009 IEEE International Solid-State Circuits Conference
EVM = 2.9%
• Output power > +28dBm • PAE ∼ 30% • EVM, spectrum mask, and ACLR specifications are satisfied © 2009 IEEE
WCDMA (PAPR = 5.2 dB, 3.84Mcps) BA Mode, Band III(1.75GHz)
10
[dBm/10kHz]
0 -10 -20 -30 -40 -50 -15
-10
-5
0
5
10
15
EVM = 3.1%
Frequency Offset [MHz]
Band I Frequency [GHz] 1.95
Band II Band III 1.83 1.75
Power [dBm] PAE
+25.1 19%
+25.3 20%
+25.5 21%
EVM
3.4%
3.0%
3.1%
© 2009 IEEE International Solid-State Circuits Conference
• Output power > +25dBm • PAE ∼ 20% • EVM, spectrum mask, and ACLR specifications are satisfied © 2009 IEEE
WiMAX (5MHz & 10MHz BW) BA Mode, Frequency = 1.75GHz, BW = 5MHz, 99.9% PAPR = 8.5dB 10 [dBm/10kHz]
0 -10 -20 -30 -40 -50 -60
POUT = +25.0 dBm -10 -7.5
-5
-2.5
0
2.5
5
7.5
10
EVM = 4.9%
Frequency Offset [MHz]
Bandwidth [MHz] Output Power [dBm] PAE EVM © 2009 IEEE International Solid-State Circuits Conference
5 +25.0 20% 4.9%
10 +25.0 20% 4.8% © 2009 IEEE
Performance Summary Modulation performance Modulation 16QAM WCDMA WiMax
Frequency
PAPR
Modulation BW Mode BA 1.8 GHz 5.9 dB 50 kHz LA ES 3.5 dB BA 1.75 - 1.95 GHz 3.84 MHz 5.2 dB BA 1.75 GHz 8.5 dB (99%) 5, 10 MHz BA
Basic performance Frequency Maximum Output Power Peak PAE LO Input Power Die Area Max. LO to RF Power Gain BB to RF Voltage Max. Conversion Gain Min. Output Power Range BA-mode OP1dB LA-mode ES-mode
Pout +27.1 dBm +27.6 dBm +26.5 dBm +28.0 dBm +25.5 dBm +25.0 dBm
PAE 25% 18% 26% 30% 21% 20%
EVM 4.3% 5.0% 4.5% 2.9% 3.1% 4.9%
Power consumption 1.8 GHz +31.3 dBm 42 % 3 dBm 2.56 mm2 28.3 dB 20.2 dB -18.6 dB 103 dB +30.2 dBm +31.3 dBm +28.5 dBm
© 2009 IEEE International Solid-State Circuits Conference
Power Mixer Array Digital LO Distributor Analog BB Replica Linearizer Analog BB Distributor Digital Controller
Supply
Power
3V
2.94 W
1.2 V
0.27 W
3V
18 mW
3V
< 0.1 mW
1.2 V
< 0.1 mW
© 2009 IEEE
Conclusion • Fully-integrated power mixer array transmitter subsystem occupies 2.6mm2 in a 130nm CMOS technology. • Output power is larger than 1W with a PAE of 40%, from 1.5 to 2 GHz. • Three operation modes of BA, LA, and ES are demonstrated with high linearity and improved efficiency. • Output power range of greater than 100dB is achieved without any RF gain control circuit. • WCDMA and WiMax modulated output signals are successfully measured with a linear output power of +28.2dBm and with a PAE of 30% for WCDMA.
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Acknowledgement • The member of Caltech High-speed Integrated Circuits Group for Discussions and Suggestions • H. Mani and M. Loh from Caltech for chip testing setup • Rogers Corporation for high frequency laminates • Texas Instruments for DAC chips
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
For additional multimedia material: See http://www.isscc.org
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Shouhei Kousai*1*2 and Ali Hajimiri*1 *1 California Institute of Technology *2 Toshiba Corporation
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Outline • • • • • •
Background Power mixer array Power mixer details Block diagram and operation modes Measurement results Conclusion
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Primary Constraints in Wireless Communication
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Pros and Cons of Conventional Approaches Efficiency 1
Supply modulation Out-phasing Digital PA
0.5
Doherty
Class-AB
• Class-AB – Poor efficiency
• Doherty & Out-phasing – Phase shifter
• Supply modulation – DC-DC converter
• Digital PA – Aliasing & output noise
0 Output Power
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Outline • • • • • •
Background Power mixer array Power mixer details Block diagram and operation mode Measurement results Conclusion
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Power Mixer Array Transmitter Subsystem • Power generation is done by several identical mixers • Power mixer array subsumes some of the functionality of a conventional transmitter
Envelope (BB)
t
RF Output t
t
Phase (LO) t
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Segmented Power Generation • When a symbol does not require full output power some power generation blocks are turned off 1
Q 2
3
Ι
n
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Back-Off Efficiency Improvement • Power efficient and compatible with CMOS processes • CMOS is good at switching on and off 1
Power Consumption 2
3
Output Power n
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Linearity Improvement
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Linearity Improvement
V1
1
V V2
2
3
V Vk n
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Linearity Improvement • Linearity improves as the output increases
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
BB Input Signal Generation • Input signals are pulse shaped to avoid spurious and alias problems Analog residue of the BB envelope
Filtered Digital BB Pulse
BB Envelope
RF Output t
Phase (LO) t
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
BB Circuit Sharing • BB circuits such as DAC and LPF can be shared by using switch
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Output Network and Signal Combination • Transformer is suitable for a large impedance transformation ratio • Output current of the power mixers can be linearly combined at the output network
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Outline • • • • • •
Background Power mixer array Power mixer details Block diagram and operation mode Measurement results Conclusion
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Power Mixer • Current commuting mixer
• Boost the voltage swing & output impedance • Amplitude modulation – “Linear” Amplitude modulation – Large bandwidth
• Switching operation – High Efficiency – Low Noise
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Transient Waveform of Power Mixer • Peak efficiency = 60%, Peak power = 33dBm @ 1.8 GHz
8
[V, A]
6 4 2 0 -2 0
0.2
0.4
0.6 time [ns]
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
0.8
1
1.2
Gain and Non-Linearity of Power Mixer • The transconductance and the current gain is non-linear to the differential mode of the input voltage (VDIFF)
iLO iLO,S
VDIFF
iRF iLO 1
VDIFF
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
1. Class-AB Operation • These non-linearities can cancel each other • Improved back-off efficiency
iLO iLO,S VCM
VDIFF
iRF iLO 1
VDIFF
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
2. Baseband Replica Linearizer • Dynamically match the power mixer core and BB replica amplifier using feedback iRF+
M8
M7
M3
Baseband Replica Amplifier
Power Mixer Core iRF-
X
M4
M5
BBout-
M6
LBB+
iLO+
RCM
BBout+ M10 Y
iLO-
RCM
M11
LBB-
I DC LO+
LO-
M1
M2
LBB+
CM
LBB-
R2
BBinBBin+
R1
+
CM+ Vref R1
CM-
+
+
+
BBout+
BB Replica
BBout-
R2
Analog BB Replica Linearizer © 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Outline • • • • • •
Background Power mixer array Power mixer details Block diagram and operation modes Measurement results Conclusion
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Block Diagram of the Implemented System On-Chip
LBB+
Iout+
CM
Iout
LBB-
PM0
C1
LBB+ 6 CM 6 LBB-
Analog BB Distributor
VDD PM13
1:2
Analog BB Replica Linearizer Array
6 PM14
C2
6
6
BBin+ BBin-
6
6
Bypass
Envelope (BB)
Digital Controller
LO-
LO+
PM15
Digital LO Distributor PAD
Digital Control
+ Phase (LO)
RF Output t
t t © 2009 IEEE International Solid-State Circuits Conference
RLoad
© 2009 IEEE
1. Baseline Analog (BA) Mode • Class-AB operation for linearity and efficiency improvement • Equivalent to one large power mixer Power Mixer Array Current
Iout+ Iout
Envelope (BB)
PM0
BBin+
Input Amplitude (BB Envelope)
PM13
BBin
Output Amplitude (RF)
PM14
Digital Controller
LO-
LO+
PM15
Digital LO Distributor
+ Phase (LO) © 2009 IEEE International Solid-State Circuits Conference
Input Amplitude (BB Envelope)
© 2009 IEEE
2. Linearized Analog (LA) Mode • One large power mixer with feedback linearizer Power Mixer Array Current
Input Amplitude (BB Envelope)
LO-
LO+
Output Amplitude (RF)
Input Amplitude (BB Envelope)
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
3. Efficient Segmented (ES) Mode • Segmented power generation for linearity and efficiency improvement Power Mixer Array Current
Input Amplitude (BB Envelope)
LO-
LO+
Output Amplitude (RF)
Input Amplitude (BB Envelope)
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Die Photo
Analog BB Distributor
Analog BB Replica Linearizer Array
• Fully-integrated in a 130nm CMOS Technology
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Outline • • • • • •
Background Power mixer array Power mixer details Block diagram and operation modes Measurement results Conclusion
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Frequency Response • PAE is larger than 40% from 1.5 to 2 GHz • Output power is larger than 1W from 1.2 to 2.4 GHz 50
43%
32
40
31
30
+31.4 dBm
30 29
20 10
Output power PAE
28 1
1.5
2
PAE [%]
Output power [dBm]
33
0 2.5
Frequency [GHz]
LO input power = +3 dBm BB input(0-p, single) = 450mV © 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Gain and PAE for Different Operation Mode • BA and LA mode have very high linearity • ES mode and BA mode show improved efficiency Reference BA Mode LA Mode ES Mode
2 1
BA Mode LA Mode ES Mode
50 40 PAE [%]
Conversion Gain (Normarized) [dB]
3
0 -1 -2
30 20 10
-3 -4
0 -10
0
10
20
30
40
Output Power [dBm ]
-10
0 10 20 30 Output Power [dBm]
Frequency = 1.8 GHz, CW
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
40
Linearity Robustness • LA and ES modes are robust to power mixer linearity
Gain (Normarized) [dB]
VCM = 0.4V VCM = 0.45V VCM = 0.5V BA Mode
3
LA Mode
3
2
2
2
1
1
1
0
0
0
-1
-1
-1
-2
-2
-2
-3
-3
-3
-4
-4
-4
-10
0 10 20 30 40 Output Power [dBm ]
-10
0
10
20
ES Mode
3
30
40
Output Power [dBm ]
-10
0
10
30
Output Power [dBm ]
Frequency = 1.8 GHz, CW © 2009 IEEE International Solid-State Circuits Conference
20
© 2009 IEEE
40
EVM & PAE for 16QAM Modulation 30 BA Mode LA Mode ES Mode
BA Mode LA Mode ES Mode
25 PAE[%]
EVM[%]
10
5
20 15 10 5
0
0 10
15
20
25
30
Average Output Power [dBm]
Frequency = 1.8 GHz Symbol Rate = 50 kSym/s
10
15
20
25
30
Average Output Power [dBm]
BA Mode LA Mode ES Mode Pout [dBm] +27.1 +27.6 +26.4 PAE
25%
18%
26%
EVM
4.3%
5.0%
4.5%
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
LO Leakage and Output Power Range • More than 100dB output power range is achieved BA Mode, w/ DC Offset Adj. BA Mode LA Mode ES Mode
-60
12
-65
10
16QAM EVM [%]
LO Leak [dBm]
Frequency = 1.8 GHz # of the Power Mixer = 1 VCM = 0.2V
-70 -75 -80 -85 -90 -95 -1.2 -0.8 -0.4
0
0.4
0.8 1.2
Differential Input [mV]
© 2009 IEEE International Solid-State Circuits Conference
8 6
103dB
4 2 0 -100 -80
-60
-40
-20
0
20
Average Output Power [dBm]
© 2009 IEEE
40
WCDMA (PAPR = 3.5 dB, 3.84Mcps) BA Mode, Band III(1.75GHz) 10
[dBm/10kHz]
0 -10 -20 -30 -40 -50 -15
-10 -5 0 5 10 Frequency Offset [MHz]
Band I Frequency [GHz] 1.95
15
Band II Band III 1.83 1.75
Power [dBm] PAE
+28.4 28%
+28.3 28%
+28.3 30%
EVM
3.7%
3.5%
2.9%
© 2009 IEEE International Solid-State Circuits Conference
EVM = 2.9%
• Output power > +28dBm • PAE ∼ 30% • EVM, spectrum mask, and ACLR specifications are satisfied © 2009 IEEE
WCDMA (PAPR = 5.2 dB, 3.84Mcps) BA Mode, Band III(1.75GHz)
10
[dBm/10kHz]
0 -10 -20 -30 -40 -50 -15
-10
-5
0
5
10
15
EVM = 3.1%
Frequency Offset [MHz]
Band I Frequency [GHz] 1.95
Band II Band III 1.83 1.75
Power [dBm] PAE
+25.1 19%
+25.3 20%
+25.5 21%
EVM
3.4%
3.0%
3.1%
© 2009 IEEE International Solid-State Circuits Conference
• Output power > +25dBm • PAE ∼ 20% • EVM, spectrum mask, and ACLR specifications are satisfied © 2009 IEEE
WiMAX (5MHz & 10MHz BW) BA Mode, Frequency = 1.75GHz, BW = 5MHz, 99.9% PAPR = 8.5dB 10 [dBm/10kHz]
0 -10 -20 -30 -40 -50 -60
POUT = +25.0 dBm -10 -7.5
-5
-2.5
0
2.5
5
7.5
10
EVM = 4.9%
Frequency Offset [MHz]
Bandwidth [MHz] Output Power [dBm] PAE EVM © 2009 IEEE International Solid-State Circuits Conference
5 +25.0 20% 4.9%
10 +25.0 20% 4.8% © 2009 IEEE
Performance Summary Modulation performance Modulation 16QAM WCDMA WiMax
Frequency
PAPR
Modulation BW Mode BA 1.8 GHz 5.9 dB 50 kHz LA ES 3.5 dB BA 1.75 - 1.95 GHz 3.84 MHz 5.2 dB BA 1.75 GHz 8.5 dB (99%) 5, 10 MHz BA
Basic performance Frequency Maximum Output Power Peak PAE LO Input Power Die Area Max. LO to RF Power Gain BB to RF Voltage Max. Conversion Gain Min. Output Power Range BA-mode OP1dB LA-mode ES-mode
Pout +27.1 dBm +27.6 dBm +26.5 dBm +28.0 dBm +25.5 dBm +25.0 dBm
PAE 25% 18% 26% 30% 21% 20%
EVM 4.3% 5.0% 4.5% 2.9% 3.1% 4.9%
Power consumption 1.8 GHz +31.3 dBm 42 % 3 dBm 2.56 mm2 28.3 dB 20.2 dB -18.6 dB 103 dB +30.2 dBm +31.3 dBm +28.5 dBm
© 2009 IEEE International Solid-State Circuits Conference
Power Mixer Array Digital LO Distributor Analog BB Replica Linearizer Analog BB Distributor Digital Controller
Supply
Power
3V
2.94 W
1.2 V
0.27 W
3V
18 mW
3V
< 0.1 mW
1.2 V
< 0.1 mW
© 2009 IEEE
Conclusion • Fully-integrated power mixer array transmitter subsystem occupies 2.6mm2 in a 130nm CMOS technology. • Output power is larger than 1W with a PAE of 40%, from 1.5 to 2 GHz. • Three operation modes of BA, LA, and ES are demonstrated with high linearity and improved efficiency. • Output power range of greater than 100dB is achieved without any RF gain control circuit. • WCDMA and WiMax modulated output signals are successfully measured with a linear output power of +28.2dBm and with a PAE of 30% for WCDMA.
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
Acknowledgement • The member of Caltech High-speed Integrated Circuits Group for Discussions and Suggestions • H. Mani and M. Loh from Caltech for chip testing setup • Rogers Corporation for high frequency laminates • Texas Instruments for DAC chips
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
For additional multimedia material: See http://www.isscc.org
© 2009 IEEE International Solid-State Circuits Conference
© 2009 IEEE
