Presentation - IBM Research | Zurich
A Compression-based Morphable PCM Architecture for Improving Resistance Drift Tolerance and HPCAN Lab, Computer Engineering Department, Sharif University of Technology , Tehran, Iran
ASAP2014, 18-20 June 2014, IBM-Zurich. ASAP’14 Computer Engineering Department
Sharif University of Tech.
Phase Change Memory More cores in system More concurrency Larger working set Larger memory DRAM-based memory system hitting: power, cost, scaling wall Phase Change Memory (PCM): Emerging technology, more scalable, denser, more power-efficient
Chalcogenide glass Ge2Sb2Te5 (GST)
2 Computer Engineering Department
Sharif University of Tech.
Phase Change Memory PCM can be: - Single-Level Cell (SLC)
3 Computer Engineering Department
Sharif University of Tech.
Phase Change Memory PCM can be: - Single-Level Cell (SLC) - Multi-level Cell (MLC)
4 Computer Engineering Department
Sharif University of Tech.
Phase Change Memory PCM can be: - Single-Level Cell (SLC) - Multi-level Cell (MLC) • Read
5 Computer Engineering Department
Sharif University of Tech.
Phase Change Memory PCM can be: - Single-Level Cell (SLC) - Multi-level Cell (MLC) • Read • Write
6 Computer Engineering Department
Sharif University of Tech.
Problem Overview • Designing a MLC PCM has a serious challenge: A PCM-dedicated sort of soft error appears in the MLC PCM • Resistance drift
• MLC PCM has • More storage capacity • Higher rate of soft error
Building a Reliable MLC PCM 7 Computer Engineering Department
Sharif University of Tech.
A Deeper Look at Resistance Drift What is resistance drift?
❖Resistance value of the cell increases over time! Content of the cell “01” “00”
❖Why ? Due to structural relaxation of GST. ❖How? There is an accurate and prototype-justified model. R0 = initial resistance t = elapsed time d = drift exponent t0 = normalized time constant 8 Computer Engineering Department
Sharif University of Tech.
Probability of Soft Error “11” and “00” are resistance drift resilient states. “10” and “01” are resistance drift prone patterns.
❖For t=16 seconds:
ASAP2014, 18-20 June 2014, IBM-Zurich. ASAP’14 Computer Engineering Department
Sharif University of Tech.
Phase Change Memory More cores in system More concurrency Larger working set Larger memory DRAM-based memory system hitting: power, cost, scaling wall Phase Change Memory (PCM): Emerging technology, more scalable, denser, more power-efficient
Chalcogenide glass Ge2Sb2Te5 (GST)
2 Computer Engineering Department
Sharif University of Tech.
Phase Change Memory PCM can be: - Single-Level Cell (SLC)
3 Computer Engineering Department
Sharif University of Tech.
Phase Change Memory PCM can be: - Single-Level Cell (SLC) - Multi-level Cell (MLC)
4 Computer Engineering Department
Sharif University of Tech.
Phase Change Memory PCM can be: - Single-Level Cell (SLC) - Multi-level Cell (MLC) • Read
5 Computer Engineering Department
Sharif University of Tech.
Phase Change Memory PCM can be: - Single-Level Cell (SLC) - Multi-level Cell (MLC) • Read • Write
6 Computer Engineering Department
Sharif University of Tech.
Problem Overview • Designing a MLC PCM has a serious challenge: A PCM-dedicated sort of soft error appears in the MLC PCM • Resistance drift
• MLC PCM has • More storage capacity • Higher rate of soft error
Building a Reliable MLC PCM 7 Computer Engineering Department
Sharif University of Tech.
A Deeper Look at Resistance Drift What is resistance drift?
❖Resistance value of the cell increases over time! Content of the cell “01” “00”
❖Why ? Due to structural relaxation of GST. ❖How? There is an accurate and prototype-justified model. R0 = initial resistance t = elapsed time d = drift exponent t0 = normalized time constant 8 Computer Engineering Department
Sharif University of Tech.
Probability of Soft Error “11” and “00” are resistance drift resilient states. “10” and “01” are resistance drift prone patterns.
❖For t=16 seconds:
