Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide ...
Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors Yuan Liu†, Jian Guo†, Yecun Wu‡, Enbo Zhu†, Nathan O Weiss†, Qiyuan He‡, Hao Wu†, Hung-Chieh Cheng†, Yang Xu‡, Imran Shakir§, Yu Huang†,|| and Xiangfeng Duan*,†,|| †
Department of Materials Science and Engineering, University of California, Los
Angeles, CA 90095, USA; ‡Department of Chemistry and Biochemistry, University of California, Los Angeles, CA 90095, USA; §Sustainable Energy Technologies Centre, College of Engineering, King Saud University, Riyadh 11421,Kingdom of Saudi Arabia; ||California Nanosystems Institute, University of California, Los Angeles, CA 90095, USA.
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Figure S1. (a) The optical image of a typical device with nanowire integrated on top of MoS2. The scale bar is 10 µm. (b) Atomic Force Microscope (AFM) image of the highlighted region in (a). (c) The height difference of the white dash line (b), demonstrating the thickness of MoS2 is 3.8 nm.
Figure S2. The influence of oxygen plasma to electrical performance of MoS2. (a) The schematics of graphene/MoS2 hybrid device etched by oxygen plasma. (b) The Ids-Vg transfer curve of the device with various plasma etching time. Below 10 s etching, the graphene characteristic still exist. With increasing etching time, the device begins to show n-type characteristic as the current drops quickly. By 35 s etching time, the device shows current on the scale of ~nA, indicating the MoS2 surface is damaged by the plasma process. Bias voltage is 1 V. (c) The Ids-Vds output curve of the device at various plasma etching durations. With increasing etching time, the current drop quickly. Gate voltage is 60 V.
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Figure S3. (a) The distribution of the ON current density of 7 devices at room temperature, where the largest current density (0.83 mA/µm) device is shown in Fig. 2. (b-g) The Ids-Vds output curve of six other devices at room temperature. The gate voltage is from -25 V to 25 V, with 10 V step.
Figure S4. The fabrication process of the contact resistance devices. (a) The CVD grown monolayer graphene is transferred on top of Si/SiO2 sacrificial wafer using standard wet transfer technique. b) Graphene is patterned into stripes (3 µm×40 µm) using photolithography, followed by oxygen plasma etching. The distance between
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graphene stripes are controlled to be 3 µm, 6 µm and 9 µm. (c-e) The graphene stripes are transferred on top of MoS2 flake using standard wet transfer technique. (f) Metal (Ni/Au) is deposited on the side of MoS2 flake to contact graphene, and to extract the contact resistance of graphene/MoS2. (g) Metal (Ni/Au) is deposited on top of MoS2/graphene heterostructure to extract the contact resistance of Ni/graphene/MoS2 hybrid stack,
Figure S5. The contact resistance of Ni/MoS2 at room temperature. (a) Schematics of contact resistance measurement using multi-terminal transfer line method. (b) Contact resistance vs. back gate voltage. The inset is a zoom in view in gate voltage range from 10 V to 25 V. The contact resistance at Vg=25 V is 2.9 - 7.5 kΩ μm, which is ~5 times larger than that in Ni/graphene/MoS2 hybrid stack.
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Figure S6. The contact resistance of graphene/MoS2 contact at room temperature. (a) Schematics of contact resistance measurement using multi-terminal transfer line method. Graphene is van der Waals contacted with MoS2 and metal is contact with graphene on the side. (b) Contact resistance vs. back gate voltage. The inset is a zoom in graph at gate voltage ranging from 0 to 25 V. The contact resistance at Vg=25 V is 5.6 kΩ μm to 11 kΩ μm, which is about 10 times larger than that in Ni/graphene/MoS2 hybrid contact.
Figure S7. Effective extrinsic mobility measured in long channel devices (L=7 μm and W=5 μm). The contact is Ni/graphene hybrid and the measurement bias is 1 V.
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Figure S8. Schottky barrier height extracted in Ni-MoS2 contact. The obtained barrier height is around twice of that with Ni/graphene/MoS2 contact. Bias voltage is 0.1 V.
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Department of Materials Science and Engineering, University of California, Los
Angeles, CA 90095, USA; ‡Department of Chemistry and Biochemistry, University of California, Los Angeles, CA 90095, USA; §Sustainable Energy Technologies Centre, College of Engineering, King Saud University, Riyadh 11421,Kingdom of Saudi Arabia; ||California Nanosystems Institute, University of California, Los Angeles, CA 90095, USA.
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Figure S1. (a) The optical image of a typical device with nanowire integrated on top of MoS2. The scale bar is 10 µm. (b) Atomic Force Microscope (AFM) image of the highlighted region in (a). (c) The height difference of the white dash line (b), demonstrating the thickness of MoS2 is 3.8 nm.
Figure S2. The influence of oxygen plasma to electrical performance of MoS2. (a) The schematics of graphene/MoS2 hybrid device etched by oxygen plasma. (b) The Ids-Vg transfer curve of the device with various plasma etching time. Below 10 s etching, the graphene characteristic still exist. With increasing etching time, the device begins to show n-type characteristic as the current drops quickly. By 35 s etching time, the device shows current on the scale of ~nA, indicating the MoS2 surface is damaged by the plasma process. Bias voltage is 1 V. (c) The Ids-Vds output curve of the device at various plasma etching durations. With increasing etching time, the current drop quickly. Gate voltage is 60 V.
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Figure S3. (a) The distribution of the ON current density of 7 devices at room temperature, where the largest current density (0.83 mA/µm) device is shown in Fig. 2. (b-g) The Ids-Vds output curve of six other devices at room temperature. The gate voltage is from -25 V to 25 V, with 10 V step.
Figure S4. The fabrication process of the contact resistance devices. (a) The CVD grown monolayer graphene is transferred on top of Si/SiO2 sacrificial wafer using standard wet transfer technique. b) Graphene is patterned into stripes (3 µm×40 µm) using photolithography, followed by oxygen plasma etching. The distance between
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graphene stripes are controlled to be 3 µm, 6 µm and 9 µm. (c-e) The graphene stripes are transferred on top of MoS2 flake using standard wet transfer technique. (f) Metal (Ni/Au) is deposited on the side of MoS2 flake to contact graphene, and to extract the contact resistance of graphene/MoS2. (g) Metal (Ni/Au) is deposited on top of MoS2/graphene heterostructure to extract the contact resistance of Ni/graphene/MoS2 hybrid stack,
Figure S5. The contact resistance of Ni/MoS2 at room temperature. (a) Schematics of contact resistance measurement using multi-terminal transfer line method. (b) Contact resistance vs. back gate voltage. The inset is a zoom in view in gate voltage range from 10 V to 25 V. The contact resistance at Vg=25 V is 2.9 - 7.5 kΩ μm, which is ~5 times larger than that in Ni/graphene/MoS2 hybrid stack.
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Figure S6. The contact resistance of graphene/MoS2 contact at room temperature. (a) Schematics of contact resistance measurement using multi-terminal transfer line method. Graphene is van der Waals contacted with MoS2 and metal is contact with graphene on the side. (b) Contact resistance vs. back gate voltage. The inset is a zoom in graph at gate voltage ranging from 0 to 25 V. The contact resistance at Vg=25 V is 5.6 kΩ μm to 11 kΩ μm, which is about 10 times larger than that in Ni/graphene/MoS2 hybrid contact.
Figure S7. Effective extrinsic mobility measured in long channel devices (L=7 μm and W=5 μm). The contact is Ni/graphene hybrid and the measurement bias is 1 V.
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Figure S8. Schottky barrier height extracted in Ni-MoS2 contact. The obtained barrier height is around twice of that with Ni/graphene/MoS2 contact. Bias voltage is 0.1 V.
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