putomiatic Amplitude Control for - Semantic Scholar
An
Ambient Proof and Wide Tuning Range putomiatic Amplitude Control with
for
LC VCO uner
icatilons Jun Yan, Desheng Ma, Wei Mao, Ming Gu, Yin Sh Mixed Signal and Hligh Speed Circuit Lab Institute of Semiconductors, Chinese Academy of Scienc Beijing, P.R.China, 100083 Email: jyangred.semi.ac.cn
Fa Foster Dai Department of Electrical Computer Engineering Auburn University Auburn, Alabama, USA, 36849-5201 Email: daifaO1geng.auburn.edu
Abstract- This paper represents a LC VCO with AAC (Auto Amplitude Control), in which PMOS FETs are used as active components, and the varactors are directly connected to ground to widen Kvco linear range. The AAC circuitry adds little noise to the VCO and provides it with robust performance over a wide temperature and carrier frequency range. The VCO is fabricated in 50-GHz 0.35-,tm SiGe BiCMOS process. The measurement results show that it has -127.27-dBc/Hz phase noise at 1-MHz offset and a linear gain of 32.4-MHz/V between 990-MHz and 1.14-GHz. The whole circuit draws 6.6-mA current from 5.0-V supply. I. INTRODUCTION
In broadband communications systems, for instance in tuners for HDTV, DVB or cable-modem applications, VCOVoltage Control Oscillator circuits always influence the receiver performances dramatically. In such a receiver, the double-conversion architecture is often employed[l]. As shown in fig.1, this kind of receiver structure first up-convert a channel from a broadband cable input signal (handling frequency from 100-MHz to 1-GHz) to a higher constant IF, and then down-convert it directly to the baseband frequency. This structure avoids up-mixing the lower band frequency which is easy to be of poor conversion linearity for the limits of transistors' operation characteristics. Because of the system's wide band property, this receiver structure suffers the strict requirement of wide tuning range VCOs to cover the whole operation bands: the down-conversion stage needs a VCO which has 1.1-GHz carrier and 50-MHz tuning range; the up-conversion stage needs a VCO with tuning range from 100-MHz to 1-GHz, this can be achieved by shunting several VCOs, each with different carrier and about 100-MHz tuning range, or by implementing a switch resonant tank network. The higher the first IF is, the smaller relative tuning range is required from the first LO source. In our system plan the IF is 1100-MHz allowing us to use readily available low-cost SAW filter. So the VCO with over IO% tuning range is needed. For design a VCO satisfying this application, LC VCOs have been widely studied and fabricated[1]-[4]. This paper provides another design of LC VCO which uses PMOS FETs to get
0-7803-9584-0/06/$20.00(2006 IEEE.
-~~~~~~~5~H
1075MHz
200MHz
900M1GHz
ioom-
(;7,
Up
1125MHz
Co~Down
Cnver
ion
Stage
Conversion Stage VCOs
Fig. 1. Diagram of turer
wide turning range and engages an auto-amplitude-control circuit to improve the phase noise performance and the ambientproof characteristic over process, temperature, and frequency variation[ 11]. The AAC loop is carefully constructed with fewest actives so as to exclude more additional noise. Section II will discuss the design of the PMOS LC VCO. Section III will emphasize on the AAC circuit design and analysis. Section IV describes the cascode differential VCO buffer. Section V provides the measurement results of this AAC VCO.
II. PMOS LC VCO DESIGN The design principles in our design to get a VCO with wide and linear tuning range, low phase noise are described in details as follow. A. Why Tank Directly to Ground 1) High Tank Q: The varactors used in tank should be high Q at the frequency of interest so the pn junction varactors are more suitable than MOS varactors. However, pn varactor has a parasitic substrate diode formed by the n side of the junction and the p type substrate, just as Fig.2 shows. Unless the n side of the diode is connected to ac ground, the parasitic devices will be included in the tank. 2) Wide Tuning Range and Linear Gain: The CV curve of varactor is shown in Fig.3. The linear section is where Varactor should operate. In non-linear section, the tuning curve will bend and the noise contribution will increase significantly. The
2629
V+ 0
V+
V-
Depletion
Region
N n-well
PH substrate
Fig. 2. Varactor and parasitic diode OUTn
C(pF)
----
OUTp
non-linear section
Minus Bias (V)
Fig. 3. Varactor capacitance
vs.
tuning voltage
Fig. 4. VCO with AAC
VCO tuning voltage Vtu,ne must be higher than the potential of the varactor anode. So, to get a wider tuning range and a better linearity of the gain, the anode of varactor should be connected to the lowest potential of the circuit. B. Why PMOS VCO
The flicker noise of active devices is due to the random trapping and releasing charge by defects and impurities that lie in the semiconductor material. Since the MOSFETs are surface devices, they exhibit a much greater flicker noise than BJTs. The mean-square 1/f noise current is given by[12] i2
K
f
*
~2
(2
W LC2 ox
AJf
f
OT
*A Af
(l)
where A is the area of the gate and the K is a device-specific constant. K is varied from process to process and even from run to run, but in current process, K of PMOS is typically much smaller than that of NMOS. So, it is hopeful to use PMOS rather than NMOS in VCO to reach a finer noise performance. PMOS also offers the advantage of higher output swing, so the phase noise due to the high flicker noise at frequencies below corner frequency can be tolerated. This is due to the fact that PMOS transistors can operate in the triode region without affecting the VCO noise performance. C. PMOS VCO Design[5],8]-[10]
1) Design Tank for High Q: For high Q of the tank, the on-chip spiral inductor should be chosen with wide track to maximize the tank equivalent parallel resistance. In order to get an adequate tuning range and guarantee that the Varactor capacitors but not the parasitic capacitors dominate, large size varactor is needed. However, for lower noise, small Varactor size is preferred. The proper size should be determined by simulation. Additionally, fixed capacitors are needed in tank to ensure a stable oscillation frequency.
2) Bias Current: The bias current for tank should be large enough to minimize the phase noise. The swing will be maximized when the PMOS FETs are made to alternated between triode region and cut-off. When the VCO remains in the current-limit region, the amplitude approximates to
A A2 =-* Ibias * Rp 7r
(2)
Rp is the equivalent parallel resistance of the tank. Once the PMOS FETs go into the triode region, the VCO will enter voltage-limit region. In this condition, raising the current will bring no further swing and even more phase noise and current wasting. 3) PMOSActives Scale: The PMOS FETs should be scaled according to the tail current to accommodate it with enough headroom. In steady-state oscillation condition, GmRp = 1. To ensure start-up, GmRp > 1 is needed. When PMOS FETs operate in saturated region, Gm x W/L. The PMOS size should be reasonably large to make the Gm large enough. Equation (1) shows that larger MOSFETs exhibit less 1/f noise, which is because their larger gate capacitances smooth the fluctuations of channel charge. 4) LC Tank in Tail: The inductor Ltail and the capacitor Ctail added to tail current source form a tank filter which is designed to filter out noise from the bias circuitry[13]. Here Ltail and Ctail are chosen large to reject noise coming from power supply as much as possible. III.
AAC CIRCUIT DESIGN AND ANALYSIS
An automatic-amplitude-control (AAC) circuitry in VCO keep the VCO in current-limit region and alleviate the amplitude noise and the AM to PM noise. It also provides the ambient-proof characteristics and stable performance to can
VCOs.
2630
'ref -
mirror circuitry VCO ibias 'tank Vtarnk
bias
A2QS)
AI(s
'lshunt
feedback loop system can be conceptually drawn as shown in Fig.5. The transfer function of current mirror block can be written as gm3
3 S)
Al(s)=
amplitude limiting
and current shunting
Fig. 5. Diagram of AAC feedback loop
A. AAC Feedback Loop The AAC loop used in this design is shown in Fig.4. PMOS FETs M1 and M2 form a negative resistor across the LC tank. PMOS FET M3 acts as a current source to draw current for the tank. M4 is connected as diode to bias the tail current source M3. The reference current 'ref is set by biasing the base of Q3 with bandgap voltage. The sample transistors Qi and Q2 are set to behave as a Class C amplifier which is used to limit the swing of the oscillator to slightly more than one VBE. They are normally set in cut off state when the oscillation amplitude is low. Once the amplitude gets close to VBE, these transistors start to turn on slightly at the top or bottom of the oscillation swing and form the current 'a,e flowing through R3 and R4. The potential across the R3 and R4 invoked by this current will turn on PMOS FET M5 further. This will arouse the shunt current to rise, and then the current 'bias and Itank will be cut down. From (2), it is obvious that the swing amplitude will be pulled back to a value around VBE. These steps will prevent PMOS FET M1 and M2 from entering triode region and ensure that the VCO always draws just enough current to turn on these limit-transistors. Heavily turning on Qi and Q2 should be prevented; otherwise they will load the tank with their dynamic emitter resistance and de-Q the tank. C4 is included here to form a dominant and controllable pole in the AAC feedback loop so that the whole system is stable under all the operating conditions. It also filters out the noise coming from bias. Resistors R3, R4 and diode D7 can provide a dc bias a little under Vth for the shunt branch PMOS FET M5 which will improve the sensitivity of the feedback loop. Schottky diodes D3 to D5 are used to confine VCE of the transistors Qi and Q2 within breakdown voltage. They also provide bias for AAC feedback loop. D6 is reversely connected to prevent Qi and Q2 from deep saturation, that is to say, to prevent CB junction being minus biased too far. Adjusting the ratio of R3 and R4 can control the response sensitivity of the AAC feedback loop. In our design, the AAC loop feedback current 'ave is only 200-,uA. So it is a power saving scheme for amplitude controlling. Compared with previous works[1 1],[14], this AAC loop is constructed with less actives so it introduces less noise from bias circuit to the oscillation part, and saves the chip space at the same time. B. AAC System Analysis[14],[15] The point P shown in Fig.4 acts as a summing node for the three currents: 'ref, 'shunt and 'bias The VCO with AAC
C4
Itank
(3) S + gm -[bias 04 Capacitor C4 creates a dominant pole at P1 = 9m4/C4. When C4 is increased, the loop will behave more stable but the control delay will be increased. It can be noted that (2) has its obvious limitations to determine the amplitude of tank, because it doesn't include the influence of frequency. For exact analysis, the oscillator should be treated as a resonator with a current pulse applied to the tank by M1 and M2 alternatively in each equal half cycle. The second order transfer function can then be written as La 2 (4) VOC(S) Cvar (s + C ) 2 +W2 RpCvar
where w is approximately equal to the frequency of oscillation. From the equation above the transient behavior of this circuit can be determined, and the time constant RpCvar in (4) is equivalent to a pole in the response of the oscillation amplitude versus bias current. This pole can be added to (2) to describe the frequency response of the oscillation amplitude. For the resonator block, transfer function can be written as
A2 (s)
Vtank
2
Itank
r
1
C", s
+ Rp
a
(5)
A
The pole can be written as a function of Q: 1
OSC
(6) 2Q Equation (6) shows the impact of the oscillator's behavior on AAC loop. A tank with higher Q will respond more slowly and therefore has a lower frequency pole than a lower Q oscillator. A high Q VCO will lead to a less stable loop because it has more phase shift at lower frequency. Because the frequency of P2 and the gain of A2(s) are set and not allowed to be adjusted arbitrarily once the oscillator is settled according to the design requirements, the intrinsic sensitivity of the AAC loop is fixed. When the Vtank reaches VBE, the limit transistors Qi and Q2 turn on and then form narrow pulses with peak amplitude. The transfer function of the amplitude limiting block in Fig.5 can be written as
RpCvar
&'t)= 0shunt &Vtank
=KIs(R3 + yjv5)e 2tT + 2, 2Dt (
1(R3+JWC5~
IiFVVtank )e 2-T
+ VD7 -Vth)
Vs 2T
3) (7)
Vtank where K = -4,oC,,W/L. This transfer function is very nonlinear. The pole created by C4 is near the pole of VCO core so there exists a potential of oscillation. C5 is introduced to this block to produce another pole that acts as the new
2631
dominant pole with a much lower frequency and pulls the original pole to a larger frequency and one zero that minimizes the phase shift caused by the dominant pole at low frequencies. Thus we get two poles split apart far away and large phase margin. For more phase margin, the loop gain can be adjusted by changing the gain Al(s) (by adjusting the ratio of M3 to M4) or A3 (s) (by adjusting the size of limiting transistors Qi and Q2). Anyway, the gain should be kept high enough to settle the VCO amplitude at an exact and stable final value.
Vtune vs Phase Noise and Kveo
1150
-
-122
Carrier Frequeney Phase Noise
-123
1100
124 1050
125
-/
1000
-126
'I
950
'.
900
128
0.55
IV. DIFFERENTIAL VCO BUFFER
127
1.003
1.5
2.005 2.507 3.004 3.502 4.001 4.507 5.237 Vtune (V)
Fig. 8. Oscillation Frequency and Phase Noise vs. Vtune
OUTp BIAS OUTn
tuning range which covers the carrier frequency with over 100MHz tuning range (over 10%). The gain approximates to 32.4MHz/V in the linear section (Vtu,ne from 1.5-V to 5.0-V). Fig.8 also shows the AAC's function of rejecting the change of phase noise. With the carrier frequency varying from 990-MHz to 1100-MHz, the phase noise changes only a couple of dB. Phase Noise vs. Tetperatulre
Fig. 6.
1- 5
Schematic of cascode structure VCO buffer
Carrier Power -12.72 dBm Atten 0.00 dB Ref -70.OOdc/Hz
Mkrl
315
45
.55
65
7.5
815
CI&
z
Phase Noise
126.3
"W,
-126. 5
'l-w"
126. 7
126.9 127. 1 127. 3
V. DESIGN RESULTS
Fig.7 shows the design results of the phase noise of VCO with AAC. At 1-MHz frequency offset, a -127.27-dBc/Hz phase noise has been attained from a 1.14-GHz carrier. All these results are measured using Agilent E4440A spectrum analyzer. Fig.8 shows the tuning curves when Vtu,ne is set from 0.55V to 5.237-V. It can be seen that this VCO can have a linear
--*-
-126. 1
The VCO output buffer is constructed to be differential pair amplifier. Just as fig.6 depicts, Q5 and Q6 provide the bias tail current, Qi and Q2 are the two main amplify pair. Q3 and Q4 form the cascode structure for isolating the VCO core from outside to avoid the influence of load and preventing the pulling effect when the VCO is located on the same substrate as other high power blocks with close operation frequency.
-2 5
0
Fig. 9. Phase Noise vs.Temperature (Vtune=5V)
Fig.9 shows the VCO phase noise vs. temperature. With the Temperature varying from about 15-°C to 95-°C, the phase noise only changes within two dBs. For the experiment condition limits, the lower temperature performance is unable to be presented, and the 15-°C temperature value is got by estimation.
1.00000 MHz -127.27 dBc/Hz
dB/0e
100 kHz
Frequency
Fig. 7. Phase Noise Performance of VCO (Carrier Frequency is 1. 14GHz)
2632
Fig. 10. Photomicrograph of the AAC VCO and buffer
Fig. 10 is the die photo of the AAC VCO with buffer. VI. CONCLUSION This paper presents a 1.1-GHz LC VCO with a low phase noise of -127.27-dBc/Hz at 1-MHz offset and with wide tuning range and linear tuning curve. It exhibits about 32.4MHz/V linear gain from 990-MHz to 1140-MHz. The phase noise is almost constant over a wide temperature and carrier frequency range. These optimized performances are due to the PMOS VCO structure design and the optimization of the AAC circuitry design detailedly discussed above. If we reconstruct the VCO resonant tank based on this design to meet the lower frequency band, it is adequate to get all the VCOs for a whole tuner receiver system to cover all its operation frequency. REFERENCES
[1] H. Samueli, "Broadband Communication ICs: Enabling High-Bandwidth
Connectivity in the Home and Ofice", Proc. International Solid-state Circuit Conference 1999, pp. 26-33. [2] K. Stadius, K. Halonen, "Wide-Tuning-Range Dual-VCOs for CableModem Receivers", Proc. 2002 IEEE Radio Frequency Integrated Circuits Symp., pp. 471-474. [3] Raymond Montemayor, "A 410-mW 1.22-GHz Downconverter in a DualConversion Tuner IC for OpenCable Applications", IEEE J. Solid-State Circuits, vol.39, pp.714-718, April 2004. [4] Katsuyoshi Washio, Takeaki Okabe, "An All-Band TV Tuner IC with 10-GHz/100-V Mixed Analog/Digital Si Bipolar Technology", IEEE J. Solid-State Circuits, vol.27, pp.1034-1038, September 1992. [5] B. D. Muer, M. Borremans, M. Steyaert, "A 2-GHz Low-Phase-Noise Integrated LC-VCO Set with Flicker-Noise Upconversion Minimization," IEEE J. Solid-State Circuits, vol.35, pp.1264-1269, July 2000. [6] E. Hegazi, "Varactor Characteristics, Oscillator Tuning Curves, and AMFM Conversion," IEEE J. Solid-State Circuits, vol.38, pp.1033-1039, June 2003. [7] J. W. M. Rogers, F. F. Dai, M. S. Cavin, "A Multiband Delta Sigma Fractional-N Frequency Synthesizer for a MIMO WLAN Transceiver RFIC," IEEE J. Solid-State Circuits, vol.40, pp.678-689, Mar. 2005. [8] S. Levantino, C. Samori, A. Bonfanti, "Frequency Dependence on Bias Current in 5-GHz CMOS VCOs: Impact on Tuning Range and Flicker Noise Upconversion," IEEE J. Solid-State Circuits, vol.37, pp.1003-1011, August 2002. [9] A. Hajimiri, T. H. Lee, "Design Issues in CMOS Differential LC Oscillators," IEEE J. Solid-State Circuits, vol.34, pp.717-724, May 1999. [10] D. Ham, A. Hajimiri, "Concepts and Methods in Optimization of Integrated LC VCOs," IEEE J. Solid-State Circuits, vol.36, pp.896-909, June 2001. [11] J. Rogers, D. Rahn, C. Plett, "A 2.4GHz Wide Tuning Range VCO with Automatic Level Control Circuitry," IEEE Solid-State Circuit Conference (ESSRCIRC), pp.341-344, Sept. 2001. [12] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998. [13] E. Hegazi, H. Sjoland, A. Abidi, "A Filtering Technique to Lower LC Oscillator Phase Noise," IEEE J.Solid-State Circuits, vol.36, pp.19211930, Dec. 2001. [14] J. W. M. Rogers, D. Rahn, C. Plett, "A Study of Digital and Analog Automatic-Amplited Control Circuitry for Voltage-Controlled Oscillators," IEEE J. Solid-State Circuits, vol.38, pp.352-356, Feb. 2003. [15] J. Rogers, C. Plett, Radio Frequency Integrated Circuit Design, Artech House, Inc., 2003.
2633
Ambient Proof and Wide Tuning Range putomiatic Amplitude Control with
for
LC VCO uner
icatilons Jun Yan, Desheng Ma, Wei Mao, Ming Gu, Yin Sh Mixed Signal and Hligh Speed Circuit Lab Institute of Semiconductors, Chinese Academy of Scienc Beijing, P.R.China, 100083 Email: jyangred.semi.ac.cn
Fa Foster Dai Department of Electrical Computer Engineering Auburn University Auburn, Alabama, USA, 36849-5201 Email: daifaO1geng.auburn.edu
Abstract- This paper represents a LC VCO with AAC (Auto Amplitude Control), in which PMOS FETs are used as active components, and the varactors are directly connected to ground to widen Kvco linear range. The AAC circuitry adds little noise to the VCO and provides it with robust performance over a wide temperature and carrier frequency range. The VCO is fabricated in 50-GHz 0.35-,tm SiGe BiCMOS process. The measurement results show that it has -127.27-dBc/Hz phase noise at 1-MHz offset and a linear gain of 32.4-MHz/V between 990-MHz and 1.14-GHz. The whole circuit draws 6.6-mA current from 5.0-V supply. I. INTRODUCTION
In broadband communications systems, for instance in tuners for HDTV, DVB or cable-modem applications, VCOVoltage Control Oscillator circuits always influence the receiver performances dramatically. In such a receiver, the double-conversion architecture is often employed[l]. As shown in fig.1, this kind of receiver structure first up-convert a channel from a broadband cable input signal (handling frequency from 100-MHz to 1-GHz) to a higher constant IF, and then down-convert it directly to the baseband frequency. This structure avoids up-mixing the lower band frequency which is easy to be of poor conversion linearity for the limits of transistors' operation characteristics. Because of the system's wide band property, this receiver structure suffers the strict requirement of wide tuning range VCOs to cover the whole operation bands: the down-conversion stage needs a VCO which has 1.1-GHz carrier and 50-MHz tuning range; the up-conversion stage needs a VCO with tuning range from 100-MHz to 1-GHz, this can be achieved by shunting several VCOs, each with different carrier and about 100-MHz tuning range, or by implementing a switch resonant tank network. The higher the first IF is, the smaller relative tuning range is required from the first LO source. In our system plan the IF is 1100-MHz allowing us to use readily available low-cost SAW filter. So the VCO with over IO% tuning range is needed. For design a VCO satisfying this application, LC VCOs have been widely studied and fabricated[1]-[4]. This paper provides another design of LC VCO which uses PMOS FETs to get
0-7803-9584-0/06/$20.00(2006 IEEE.
-~~~~~~~5~H
1075MHz
200MHz
900M1GHz
ioom-
(;7,
Up
1125MHz
Co~Down
Cnver
ion
Stage
Conversion Stage VCOs
Fig. 1. Diagram of turer
wide turning range and engages an auto-amplitude-control circuit to improve the phase noise performance and the ambientproof characteristic over process, temperature, and frequency variation[ 11]. The AAC loop is carefully constructed with fewest actives so as to exclude more additional noise. Section II will discuss the design of the PMOS LC VCO. Section III will emphasize on the AAC circuit design and analysis. Section IV describes the cascode differential VCO buffer. Section V provides the measurement results of this AAC VCO.
II. PMOS LC VCO DESIGN The design principles in our design to get a VCO with wide and linear tuning range, low phase noise are described in details as follow. A. Why Tank Directly to Ground 1) High Tank Q: The varactors used in tank should be high Q at the frequency of interest so the pn junction varactors are more suitable than MOS varactors. However, pn varactor has a parasitic substrate diode formed by the n side of the junction and the p type substrate, just as Fig.2 shows. Unless the n side of the diode is connected to ac ground, the parasitic devices will be included in the tank. 2) Wide Tuning Range and Linear Gain: The CV curve of varactor is shown in Fig.3. The linear section is where Varactor should operate. In non-linear section, the tuning curve will bend and the noise contribution will increase significantly. The
2629
V+ 0
V+
V-
Depletion
Region
N n-well
PH substrate
Fig. 2. Varactor and parasitic diode OUTn
C(pF)
----
OUTp
non-linear section
Minus Bias (V)
Fig. 3. Varactor capacitance
vs.
tuning voltage
Fig. 4. VCO with AAC
VCO tuning voltage Vtu,ne must be higher than the potential of the varactor anode. So, to get a wider tuning range and a better linearity of the gain, the anode of varactor should be connected to the lowest potential of the circuit. B. Why PMOS VCO
The flicker noise of active devices is due to the random trapping and releasing charge by defects and impurities that lie in the semiconductor material. Since the MOSFETs are surface devices, they exhibit a much greater flicker noise than BJTs. The mean-square 1/f noise current is given by[12] i2
K
f
*
~2
(2
W LC2 ox
AJf
f
OT
*A Af
(l)
where A is the area of the gate and the K is a device-specific constant. K is varied from process to process and even from run to run, but in current process, K of PMOS is typically much smaller than that of NMOS. So, it is hopeful to use PMOS rather than NMOS in VCO to reach a finer noise performance. PMOS also offers the advantage of higher output swing, so the phase noise due to the high flicker noise at frequencies below corner frequency can be tolerated. This is due to the fact that PMOS transistors can operate in the triode region without affecting the VCO noise performance. C. PMOS VCO Design[5],8]-[10]
1) Design Tank for High Q: For high Q of the tank, the on-chip spiral inductor should be chosen with wide track to maximize the tank equivalent parallel resistance. In order to get an adequate tuning range and guarantee that the Varactor capacitors but not the parasitic capacitors dominate, large size varactor is needed. However, for lower noise, small Varactor size is preferred. The proper size should be determined by simulation. Additionally, fixed capacitors are needed in tank to ensure a stable oscillation frequency.
2) Bias Current: The bias current for tank should be large enough to minimize the phase noise. The swing will be maximized when the PMOS FETs are made to alternated between triode region and cut-off. When the VCO remains in the current-limit region, the amplitude approximates to
A A2 =-* Ibias * Rp 7r
(2)
Rp is the equivalent parallel resistance of the tank. Once the PMOS FETs go into the triode region, the VCO will enter voltage-limit region. In this condition, raising the current will bring no further swing and even more phase noise and current wasting. 3) PMOSActives Scale: The PMOS FETs should be scaled according to the tail current to accommodate it with enough headroom. In steady-state oscillation condition, GmRp = 1. To ensure start-up, GmRp > 1 is needed. When PMOS FETs operate in saturated region, Gm x W/L. The PMOS size should be reasonably large to make the Gm large enough. Equation (1) shows that larger MOSFETs exhibit less 1/f noise, which is because their larger gate capacitances smooth the fluctuations of channel charge. 4) LC Tank in Tail: The inductor Ltail and the capacitor Ctail added to tail current source form a tank filter which is designed to filter out noise from the bias circuitry[13]. Here Ltail and Ctail are chosen large to reject noise coming from power supply as much as possible. III.
AAC CIRCUIT DESIGN AND ANALYSIS
An automatic-amplitude-control (AAC) circuitry in VCO keep the VCO in current-limit region and alleviate the amplitude noise and the AM to PM noise. It also provides the ambient-proof characteristics and stable performance to can
VCOs.
2630
'ref -
mirror circuitry VCO ibias 'tank Vtarnk
bias
A2QS)
AI(s
'lshunt
feedback loop system can be conceptually drawn as shown in Fig.5. The transfer function of current mirror block can be written as gm3
3 S)
Al(s)=
amplitude limiting
and current shunting
Fig. 5. Diagram of AAC feedback loop
A. AAC Feedback Loop The AAC loop used in this design is shown in Fig.4. PMOS FETs M1 and M2 form a negative resistor across the LC tank. PMOS FET M3 acts as a current source to draw current for the tank. M4 is connected as diode to bias the tail current source M3. The reference current 'ref is set by biasing the base of Q3 with bandgap voltage. The sample transistors Qi and Q2 are set to behave as a Class C amplifier which is used to limit the swing of the oscillator to slightly more than one VBE. They are normally set in cut off state when the oscillation amplitude is low. Once the amplitude gets close to VBE, these transistors start to turn on slightly at the top or bottom of the oscillation swing and form the current 'a,e flowing through R3 and R4. The potential across the R3 and R4 invoked by this current will turn on PMOS FET M5 further. This will arouse the shunt current to rise, and then the current 'bias and Itank will be cut down. From (2), it is obvious that the swing amplitude will be pulled back to a value around VBE. These steps will prevent PMOS FET M1 and M2 from entering triode region and ensure that the VCO always draws just enough current to turn on these limit-transistors. Heavily turning on Qi and Q2 should be prevented; otherwise they will load the tank with their dynamic emitter resistance and de-Q the tank. C4 is included here to form a dominant and controllable pole in the AAC feedback loop so that the whole system is stable under all the operating conditions. It also filters out the noise coming from bias. Resistors R3, R4 and diode D7 can provide a dc bias a little under Vth for the shunt branch PMOS FET M5 which will improve the sensitivity of the feedback loop. Schottky diodes D3 to D5 are used to confine VCE of the transistors Qi and Q2 within breakdown voltage. They also provide bias for AAC feedback loop. D6 is reversely connected to prevent Qi and Q2 from deep saturation, that is to say, to prevent CB junction being minus biased too far. Adjusting the ratio of R3 and R4 can control the response sensitivity of the AAC feedback loop. In our design, the AAC loop feedback current 'ave is only 200-,uA. So it is a power saving scheme for amplitude controlling. Compared with previous works[1 1],[14], this AAC loop is constructed with less actives so it introduces less noise from bias circuit to the oscillation part, and saves the chip space at the same time. B. AAC System Analysis[14],[15] The point P shown in Fig.4 acts as a summing node for the three currents: 'ref, 'shunt and 'bias The VCO with AAC
C4
Itank
(3) S + gm -[bias 04 Capacitor C4 creates a dominant pole at P1 = 9m4/C4. When C4 is increased, the loop will behave more stable but the control delay will be increased. It can be noted that (2) has its obvious limitations to determine the amplitude of tank, because it doesn't include the influence of frequency. For exact analysis, the oscillator should be treated as a resonator with a current pulse applied to the tank by M1 and M2 alternatively in each equal half cycle. The second order transfer function can then be written as La 2 (4) VOC(S) Cvar (s + C ) 2 +W2 RpCvar
where w is approximately equal to the frequency of oscillation. From the equation above the transient behavior of this circuit can be determined, and the time constant RpCvar in (4) is equivalent to a pole in the response of the oscillation amplitude versus bias current. This pole can be added to (2) to describe the frequency response of the oscillation amplitude. For the resonator block, transfer function can be written as
A2 (s)
Vtank
2
Itank
r
1
C", s
+ Rp
a
(5)
A
The pole can be written as a function of Q: 1
OSC
(6) 2Q Equation (6) shows the impact of the oscillator's behavior on AAC loop. A tank with higher Q will respond more slowly and therefore has a lower frequency pole than a lower Q oscillator. A high Q VCO will lead to a less stable loop because it has more phase shift at lower frequency. Because the frequency of P2 and the gain of A2(s) are set and not allowed to be adjusted arbitrarily once the oscillator is settled according to the design requirements, the intrinsic sensitivity of the AAC loop is fixed. When the Vtank reaches VBE, the limit transistors Qi and Q2 turn on and then form narrow pulses with peak amplitude. The transfer function of the amplitude limiting block in Fig.5 can be written as
RpCvar
&'t)= 0shunt &Vtank
=KIs(R3 + yjv5)e 2tT + 2, 2Dt (
1(R3+JWC5~
IiFVVtank )e 2-T
+ VD7 -Vth)
Vs 2T
3) (7)
Vtank where K = -4,oC,,W/L. This transfer function is very nonlinear. The pole created by C4 is near the pole of VCO core so there exists a potential of oscillation. C5 is introduced to this block to produce another pole that acts as the new
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dominant pole with a much lower frequency and pulls the original pole to a larger frequency and one zero that minimizes the phase shift caused by the dominant pole at low frequencies. Thus we get two poles split apart far away and large phase margin. For more phase margin, the loop gain can be adjusted by changing the gain Al(s) (by adjusting the ratio of M3 to M4) or A3 (s) (by adjusting the size of limiting transistors Qi and Q2). Anyway, the gain should be kept high enough to settle the VCO amplitude at an exact and stable final value.
Vtune vs Phase Noise and Kveo
1150
-
-122
Carrier Frequeney Phase Noise
-123
1100
124 1050
125
-/
1000
-126
'I
950
'.
900
128
0.55
IV. DIFFERENTIAL VCO BUFFER
127
1.003
1.5
2.005 2.507 3.004 3.502 4.001 4.507 5.237 Vtune (V)
Fig. 8. Oscillation Frequency and Phase Noise vs. Vtune
OUTp BIAS OUTn
tuning range which covers the carrier frequency with over 100MHz tuning range (over 10%). The gain approximates to 32.4MHz/V in the linear section (Vtu,ne from 1.5-V to 5.0-V). Fig.8 also shows the AAC's function of rejecting the change of phase noise. With the carrier frequency varying from 990-MHz to 1100-MHz, the phase noise changes only a couple of dB. Phase Noise vs. Tetperatulre
Fig. 6.
1- 5
Schematic of cascode structure VCO buffer
Carrier Power -12.72 dBm Atten 0.00 dB Ref -70.OOdc/Hz
Mkrl
315
45
.55
65
7.5
815
CI&
z
Phase Noise
126.3
"W,
-126. 5
'l-w"
126. 7
126.9 127. 1 127. 3
V. DESIGN RESULTS
Fig.7 shows the design results of the phase noise of VCO with AAC. At 1-MHz frequency offset, a -127.27-dBc/Hz phase noise has been attained from a 1.14-GHz carrier. All these results are measured using Agilent E4440A spectrum analyzer. Fig.8 shows the tuning curves when Vtu,ne is set from 0.55V to 5.237-V. It can be seen that this VCO can have a linear
--*-
-126. 1
The VCO output buffer is constructed to be differential pair amplifier. Just as fig.6 depicts, Q5 and Q6 provide the bias tail current, Qi and Q2 are the two main amplify pair. Q3 and Q4 form the cascode structure for isolating the VCO core from outside to avoid the influence of load and preventing the pulling effect when the VCO is located on the same substrate as other high power blocks with close operation frequency.
-2 5
0
Fig. 9. Phase Noise vs.Temperature (Vtune=5V)
Fig.9 shows the VCO phase noise vs. temperature. With the Temperature varying from about 15-°C to 95-°C, the phase noise only changes within two dBs. For the experiment condition limits, the lower temperature performance is unable to be presented, and the 15-°C temperature value is got by estimation.
1.00000 MHz -127.27 dBc/Hz
dB/0e
100 kHz
Frequency
Fig. 7. Phase Noise Performance of VCO (Carrier Frequency is 1. 14GHz)
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Fig. 10. Photomicrograph of the AAC VCO and buffer
Fig. 10 is the die photo of the AAC VCO with buffer. VI. CONCLUSION This paper presents a 1.1-GHz LC VCO with a low phase noise of -127.27-dBc/Hz at 1-MHz offset and with wide tuning range and linear tuning curve. It exhibits about 32.4MHz/V linear gain from 990-MHz to 1140-MHz. The phase noise is almost constant over a wide temperature and carrier frequency range. These optimized performances are due to the PMOS VCO structure design and the optimization of the AAC circuitry design detailedly discussed above. If we reconstruct the VCO resonant tank based on this design to meet the lower frequency band, it is adequate to get all the VCOs for a whole tuner receiver system to cover all its operation frequency. REFERENCES
[1] H. Samueli, "Broadband Communication ICs: Enabling High-Bandwidth
Connectivity in the Home and Ofice", Proc. International Solid-state Circuit Conference 1999, pp. 26-33. [2] K. Stadius, K. Halonen, "Wide-Tuning-Range Dual-VCOs for CableModem Receivers", Proc. 2002 IEEE Radio Frequency Integrated Circuits Symp., pp. 471-474. [3] Raymond Montemayor, "A 410-mW 1.22-GHz Downconverter in a DualConversion Tuner IC for OpenCable Applications", IEEE J. Solid-State Circuits, vol.39, pp.714-718, April 2004. [4] Katsuyoshi Washio, Takeaki Okabe, "An All-Band TV Tuner IC with 10-GHz/100-V Mixed Analog/Digital Si Bipolar Technology", IEEE J. Solid-State Circuits, vol.27, pp.1034-1038, September 1992. [5] B. D. Muer, M. Borremans, M. Steyaert, "A 2-GHz Low-Phase-Noise Integrated LC-VCO Set with Flicker-Noise Upconversion Minimization," IEEE J. Solid-State Circuits, vol.35, pp.1264-1269, July 2000. [6] E. Hegazi, "Varactor Characteristics, Oscillator Tuning Curves, and AMFM Conversion," IEEE J. Solid-State Circuits, vol.38, pp.1033-1039, June 2003. [7] J. W. M. Rogers, F. F. Dai, M. S. Cavin, "A Multiband Delta Sigma Fractional-N Frequency Synthesizer for a MIMO WLAN Transceiver RFIC," IEEE J. Solid-State Circuits, vol.40, pp.678-689, Mar. 2005. [8] S. Levantino, C. Samori, A. Bonfanti, "Frequency Dependence on Bias Current in 5-GHz CMOS VCOs: Impact on Tuning Range and Flicker Noise Upconversion," IEEE J. Solid-State Circuits, vol.37, pp.1003-1011, August 2002. [9] A. Hajimiri, T. H. Lee, "Design Issues in CMOS Differential LC Oscillators," IEEE J. Solid-State Circuits, vol.34, pp.717-724, May 1999. [10] D. Ham, A. Hajimiri, "Concepts and Methods in Optimization of Integrated LC VCOs," IEEE J. Solid-State Circuits, vol.36, pp.896-909, June 2001. [11] J. Rogers, D. Rahn, C. Plett, "A 2.4GHz Wide Tuning Range VCO with Automatic Level Control Circuitry," IEEE Solid-State Circuit Conference (ESSRCIRC), pp.341-344, Sept. 2001. [12] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998. [13] E. Hegazi, H. Sjoland, A. Abidi, "A Filtering Technique to Lower LC Oscillator Phase Noise," IEEE J.Solid-State Circuits, vol.36, pp.19211930, Dec. 2001. [14] J. W. M. Rogers, D. Rahn, C. Plett, "A Study of Digital and Analog Automatic-Amplited Control Circuitry for Voltage-Controlled Oscillators," IEEE J. Solid-State Circuits, vol.38, pp.352-356, Feb. 2003. [15] J. Rogers, C. Plett, Radio Frequency Integrated Circuit Design, Artech House, Inc., 2003.
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