Random and Systematic Defect Analysis Using ... - Semantic Scholar
Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions Phil Nigh
Anne Gattiker
IBM Technology and Systems Group
Abstract This paper demonstrates IDDQ signature analysis of random and systematic defects, including yield detractors and reliability defects. Application is demonstrated for both understanding failure root cause and guiding test decisions.
1 Background IDDQ (defect-free) is increasing significantly, as much as 10X, with each technology generation [1]-[3]. To combat the attendant decreasing effectiveness of traditional IDDQ test, new methods have been developed, including IDDQ delta, IDDQ ratios, multi-parameter and spatial-based IDDQ [4]-[16]. IDDQ has also found use for failure analysis and defect characterization [2][17]-[21], as well as diagnosis/localization [22]-[28]. This paper demonstrates the continued usefulness of IDDQ for characterization for advanced technologies. We describe and apply three methods: signature analysis and classification for understanding defect characteristics, time-dependent analysis for identifying specific types of defects and footprint analysis for guiding reliability-related test decisions.
IBM Austin Research Lab
GND. The defect shown in Figure 1c could be, for example, a short from the output of a multi-input logic gate to VDD or GND, or it could be a short between 2 logic gates. The data shown above was taken for a 0.18um ASIC, but similar IDDQ signature data for technologies ranging from 0.8um to 90nm have been found. We will continue to use this type of IDDQ signature analysis method for future technologies – even if IDDQ for production test becomes less effective. IDDQ signatures contain rich information about the circuit, defect behavior and processing conditions. In this section, we describe capturing that information by classifying signatures into different categories and using the classifications to learn about the nature of the defects occurring on a variety of ASIC chips.
2 IDDQ Signature Analysis and Classification Figure 1 shows three examples of “IDDQ signatures”. Each graph shows the IDDQ measurements for a different chip where 256 IDDQ measurements are taken per chip. IDDQ signature analysis has been discussed in a number of earlier papers [4][19]-[21]. Figure 1 shows an IDDQ measurement for a defect-free chip (Fig 1a. -- all IDDQ measurements are within 1% of each other) and two defective chips. The IDDQ signatures in Figure 1b and Figure 1c are clearly caused by defects in different circuit locations. Using classifications as described in [4], the IDDQ signature shown in Figure 1a is a “0-step”, the signature shown in Figure 1b is a “1-step” and the signature shown in Figure 1c is a “3-step” signature. This is also shown in the sorted signatures in Figure 1d – Figure 1f. The defect in Figure 1b may be a simple defect where an internal wire driven by an inverter is shorted to VDD or
Figure 1. IDDQ signature examples for a 0.18um ASIC. IDDQ measurements in test application order (a-c) and in sorted order (d-f).
ITC INTERNATIONAL TEST CONFERENCE 0-7803-8580-2/04 $20.00 Copyright 2004 IEEE
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2.1 IDDQ Classification Method We have developed software that automatically classifies IDDQ signature data. It sorts the measurements, identifies the “breaks” in the sorted distribution and records which test vectors correspond to each step. It also includes checks for signatures that do not follow the typical stepand-break pattern. Such additional signatures include “time-dependent IDDQ signatures,” identified by looking for IDDQ trends in the unsorted measurement data, and signatures that do not have clear breaks, identified by looking for wider than normal IDDQ measurement spreads. Section 2.2 presents results of applying this classification scheme to a large sample of dice. 2.2
IDDQ classification results for a large sample of ASICs We have applied this IDDQ signature classification method to a large number of ASIC devices (>150,000 chips). Here we show results of an investigation of the repeatability of signatures, i.e., how frequently the same signature is seen on more than one chip, using data from a sample of 0.25um, 0.18um and 0.13um ASICs. Figure 2 shows the number of chips on which each of a large number of signatures occurred. Nearly all signatures appeared only 1-2 chips. The results suggest that for most populations of hardware, it is uncommon to have more than a few different chips produce the same IDDQ signatures. In fact, exceptions can be signs of systematic defects, as described in the next section.
IDDQ Signature Breakdown 63615 Signatures 3-5 chips 1.1%
The wafer map, shown in Figure 3, reflects a “donut” pattern; there are good devices only in the center and on the edge of the wafer.
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Figure 3. Original wafer map showing low yield with strong region dependence. (“Donut” pattern with yielding die on in center and on edge.)
To get to the root cause, the failures were identified using results from both voltage-based testing of scan chain failures and IDDQ. IDDQ analysis identified repeating signatures. Since, as described in Section 2.2, normally we find that abnormal IDDQ signatures are different from one another as one would expect for random defects, our results suggested a systematic problem. We found two IDDQ signatures, shown in Figure 4, that occurred multiple times, while for this wafer, all other IDDQ signatures were unique. Figure 4a’s signature was found for 27 different chips; Figure 4b’s for 102 chips.
>5 chips 0.4%
1-2 chips 98.4%
Figure 2. IDDQ Signature Breakdown.
2.3 Defect Classification: Systematic defect example An advantage of the fact that most signatures are unique is that exceptions can be used to identify systematic problems. This section describes successful application of our classification method for identifying two clear systematic problems. We applied our analysis to understand the problems underlying a 0.13um ASIC wafer with very low yield. Paper 11.3 310
Figure 4. Repeating IDDQ signatures.
Wafer plots of the location of the IDDQ repeating signatures, shown in Figure 5, indicate that the first repeating signature repeats on about every 9th die, which corresponds to the 3x3 reticle pattern used for this wafer.
A repeating mask problem was later found that explained this failure. The 2nd repeating signature, shown in Figures 4b and 5b, was apparently an edge-related systematic problem. It occurred only on this wafer. After the mask was fixed and the next group of wafers went through test, the problem was never seen again. Unfortunately, we do not have root cause analysis results for this systematic problem since it no longer exists. It is interesting to note that our IDDQ signature classification method was able to identify a few chips that had both types of signatures. An example is shown in Figure 4c.
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(b) Figure 5. Wafer maps with common IDDQ signatures highlighted with dots. Dies with repeating signature from Figure 4a (a) and Figure 4b (b).
3 Time-dependent IDDQ Analysis In this section, we describe another way to look at IDDQ signature data to learn about the mechanisms underlying failures on defective chips. Specifically, we present results of measuring IDDQ for an extended period of time,
which has been found to be a useful method for characterizing defects [29]-[31]. This method has the potential to identify the type of defect causing abnormally high IDDQ – e.g., “open” vs. “short” defects. Timedependent IDDQ measurements are performed in a similar way to normal IDDQ testing except that each measurement is repeated a number of times over an extended period of time (seconds). After the initial circuit conditioning, it is important that the circuit state and measurement circuitry doesn’t change and is stable to ensure that any IDDQ changes versus time are due solely to IDDQ drifts within the IC. Here we describe experimental results from measuring IDDQ versus time using a 0.25um technology CMOS ASIC with 700K logic gates. We took 16 IDDQ measurements for four different IDDQ patterns over 3.2 seconds. We have found that IDDQ measurements for most ICs are very stable over time, e.g., less than 1% change. For defect-free ICs and ICs with bridging defects, we would expect no IDDQ variation over time after the quiescent state is reached. We evaluated a large quantity of ASICS and found: • 150 devices had more than a 5% IDDQ variation vs. time. • All of these 150 devices failed the stuck-at-fault test. 3.1 Examples In this section, we will show interesting examples that had significant time-dependent IDDQ. We will use the following examples to illustrate the various behaviors that were found in the 150 examples with abnormal IDDQ vs. time measurements. Figure 6 shows a series of graphs representing different ICs with abnormal IDDQ vs. time behavior. Table 1 summarizes the observed behaviors. Table 1. Time-dependent IDDQ behavior for example chips.
Devices
IDDQ Behavior
732
Decreases for all patterns.
1163
Increases for all patterns.
254, 4147, 994
Increases, then decreases for all patterns.
4275
Increases, then decreases slightly for 3 patterns. No change for other pattern.
5088, 2441
Increases, then decreases for 1 pattern; decreases (only) for the other 3 patterns.
155
Increases, then decreases for 3 patterns; constant (and low) for 1 pattern.
625
Increases, then decreases for all patterns, but different characteristics for 1 pattern.
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10 0 60 0
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0.8
10 0
0.3
0.8
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3
IDDQ (mA)
5
2
2.6
0.8
1.4
2.6
3.2
De vice #155
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1.4
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2
2.6
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3.2
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3.2
2
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2
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3.2
Figure 6. Examples of time-dependent IDDQ outliers.
2.4
De vice #4147
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0.8
1.4
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2.6
2.5
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2
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3.2
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15
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Observations from Time-dependent IDDQ Examples From the examples shown in the previous section, it is clear that defects can cause a wide variety of timedependent IDDQ behavior. Although it is outside the scope of this paper to perform a detailed analysis of timedependent IDDQ behavior (see, for example, [29][30][32][33]), we can use the previous examples and a simple model to better understand our empiricallyobserved time-dependent IDDQ signatures. From the examples in the previous section, we observe: • The time-dependent IDDQ behavior is pattern (circuit state) dependent. • Time-dependent IDDQ behavior varies in terms of magnitudes of the peak IDDQ, time constants for IDDQ changes (some not changing for 2 seconds) and IDDQ vs. time slopes. • Typical time-dependent signatures are: − IDDQ increases (only) − IDDQ decreases (only) − IDDQ increases, then decreases A simple example can explain the most common timedependent IDDQ signatures. Figure 7 shows a CMOS NOR gate whose transistor n1 has a floating gate that is capacitively coupled to GND such that it is stuck off. When A=’1’ and B=’0’, x is in a high-impedance state, i.e., it has no connection through on-transistors to VDD or GND. In the high-impedance state, its steady-state voltage
is determined primarily by the balance between subthreshold, gate and reverse bias pn junction leakage currents flowing into and out of the node. Because those currents are very small, it may take seconds or more for Vx to reach its steady state. If Vx takes on a value between Vtn and VDD-Vtp, IDDQ flows in the downstream NOR gate (C=’0’), reaching a maximum value at approximately VDD/2, as illustrated in Figure 7b. On any given IDDQ test vector, the initial voltage on x is determined by such factors as the preceding state of the driving gate and capacitive coupling to other nodes. As Vx travels from its initial value to its steady state value, it may pass through (and potentially remain in) the IDDQ-causing range of voltages. Doing so can give rise to various signatures observed in Section 3.1, as detailed in Table 2. The pattern-dependent presence or absence of time-dependent IDDQ seen in Section 3.1 can be understood as relating to whether or not the driving gate is sensitized to the open (A=’1’ & B=’0’) and the driven gate is sensitized to x (C=’0’). IDDQ
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0V Vtn
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VDDVDD- VDD Vtp V(Input x) V(input) VDD/2
(a) (b) Figure 7. (a) Open causing high-impedance node. (b) IDDQ vs. Vx in driven NOR with C=’0.’ Table 2. Starting/final voltages for sensitized NOR input and the resulting IDDQ vs. time signature.
Initial voltage at Input X
Final voltage at Input X
IDDQ vs. time signature
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Between Vtn and VDD/2
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Between VDDVtp and VDD/2
IDDQ increases
Between Vtn and VDD/2
Below Vtn.
IDDQ decreases
Between VDDVtp and VDD/2
Above VDD-Vtp
IDDQ decreases
Below VDD/2
Above VDD/2
IDDQ increases, then decreases
Above VDD/2
Below VDD/2
IDDQ increases, then decreases
The true time-dependent IDDQ for defective ICs is more complex than shown in Figure 7 or Table 2. The precise behavior for these chips will depend on many additional factors such as defect resistance, defect location, circuit configuration, timings/transitions at inputs of the defective
logic gate, environmental factors such as VDD voltage and temperature, and capacitive “surroundings” of the defective logic. IDDQ flowing in multiple fanout gates if they existed and current that would flow in gates downstream of the driven NOR if the driven NOR’s output voltage is also at an intermediate value (between Vtn and VDD-Vtp) would also impact the IDDQ signature.
4
IDDQ Footprints: Exploring Voltagestress-sensitive chips
The above sections illustrated getting insight into failure root cause using IDDQ. Understanding failures is important, but test engineers also face daily struggles deciding how tests should be applied and what chips are really “bad.” It is often at best expensive and at worst impossible to base decisions on a gold standard, such as a thorough and representative system test or a thorough and representative burn-in. As a result, test engineers can face having to make test decisions based on incomplete information and even “gut feel.” IDDQ signature analysis with its ability to give insight into the defects causing anomalous behavior, can be a great help in making such test decisions. This section illustrates IDDQ signature analysis in that capacity for a specific example population of chips that present a vexing problem for today’s technologies. 4.1 Motivation As burn-in becomes increasingly untenable due to cost and technology considerations such as thermal runaway and NBTI [1][34], voltage stress is receiving increasing interest as a means to ensure outgoing chip reliability. Physical defects such as metal slivers [35], cracks in insulation layers [36] and metal particles and residues, including metal particles with native oxide coatings [37], are known to be accelerated by voltage stress. However, voltage stress also presents concerns for manufacturers. The first of these concerns is decreasing effectiveness. Latent defect acceleration, typically modeled as proportional to the absolue delta between stress and operating power supply voltage, is decreasing with decreasing nominal voltages, as stress voltages are typically elevated from nominal by the same percentage from technology to technology [38]. Second, Dynamic Voltage Stress (DVS) [37] [39] brings about concerns for false fails. Specifically, because during DVS the part is operated at an out-of-spec high voltage, the part may fail to operate correctly owing to phenomena such as the large IR droop that can occur due to high current draw during scanning [40]. To mitigate that problem, some chipmakers turn expects off when the part is run at DVS voltage, but doing so subjects the manufacturer to risk of missing important bad chips, if the fails are actually due to Paper 11.3 313
defects rather than being false fails. (We use the terms “in-situ DVS” for testing with expects turned on at the DVS voltage and “in-situ-only DVS fail” for chips that fail only when run with expects on at the DVS voltage. Running the part at DVS voltage with expects off and then testing the part at nominal voltage is also known as SHOVE [41].) The third concern is that some chips appear to “heal” during voltage stress in that they fail before DVS, but pass afterward [35][40]. Given that the healing may be only temporary, most manufacturers would like to detect and fail such chips. As a result, there is a concern for unintentionally healing and passing chips unless other parts of the test suite are applied before applying voltage stress. One final concern is how to disposition chips whose IDDQ shifts significantly across voltage stress. This last concern is of particular interest because of the reported large number of chips that undergo such shifts [40]. This section uses IDDQ signature analysis to investigate questions related to these concerns. The answers can be used to guide test engineering decisions. Specifically: • As we face diminishing voltage stress effectiveness we ask: Is voltage stress required for detecting some defects, or could more sensitive voltage testing suffice? (For example, very-low-voltage testing [42][43] or at-speed testing.) • As we recognize the potential for “false fails” during in-situ DVS we ask: Are in-situ-only DVS fails defect-related and therefore is in-situ DVS testing necessary? • As we recognize the potential for defective chips to heal (possibly temporarily), we ask: Is there detectable degradation remaining on apparently “healed” chips? If there is not, even very sensitive voltage testing cannot detect such chips after voltage stress and it therefore becomes especially important to apply other tests before voltage stress during manufacturing testing. • As we recognize the prevalence of chips that shift in terms of IDDQ, we ask: Are IDDQ shifts across voltage stress related to defects? 4.2 Context of study Our investigation is applicable to static CMOS circuits. In such circuits, defects such as shorts cause static current to flow when activated. We’ll term such defects “IDDQcausing” defects. Static current flow implies voltage drops (across defect resistances and/or transistor equivalent resistances). The voltage drops imply degraded voltages on circuit nodes versus full logic ‘0’ and ‘1’ voltages, which in turn cause degradation of circuit operation. The
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degradation can range from severe (hard fails) to subtle (e.g., timing or noise margin degradation). A physical defect may exist without causing any degradation of circuit voltages. For example, an area of extra conducting material may exist but not make physical contact to two circuit nodes such that the two are shorted. If a shorting defect does make contact (and the test vectors activate the defect), defect-related IDDQ will flow and circuit node voltages will be degraded. If the short doesn’t make contact, there will be no such degraded voltages. Note that in the latter case, the defect cannot be detected by voltage tests because of the absence of degraded voltages. We use the presence of elevated IDDQ as evidence that there exists a defect causing degraded voltages on a manufactured circuit. We use “IDDQ footprints” [20][21] to determine whether or not elevated IDDQ is present. An IDDQ footprint plots the IDDQ on each vector after voltage stress versus IDDQ on the same vector before voltage stress. It reflects the difference in IDDQ-causing defects present between the two test levels. Although the footprint method is not perfect, it is highly sensitive to small defect currents in the presence of high normal background leakage currents. While it may be very difficult to implement a production test technique with similar sensitivity, during characterization for test guidance purposes, we are able to detect very small (tens of uAs) defect-related current. (Some defects, such as opens that behave as stuck-ats, are well-known not to produce elevated static current [44]. Our analyses don’t apply in such cases. However, our observation is that most voltage-stress-sensitive fails are related to IDDQ-causing defects, as reflected in the results presented in this section, so that the described methods apply.) The presented results are from the testing of an example lot of a 0.25um ASIC. 4.3 Voltage stress "kills" A voltage stress "kill" passes all voltage testing applied before voltage stress, but fails that same voltage testing after voltage stress. On such chips, it could be the case that the defect that causes the voltage test fail existed and affected the circuit before voltage stress, but its effect on the circuit became more severe as a result of voltage stress. Alternatively, it could be the case that there was no defect affecting the circuit before voltage stress, but one comes into play during or after voltage stress. We are interested in determining for our hardware whether or not before voltage stress there was already evidence of degraded circuit voltages. IDDQ evidence suggesting the existence of both scenarios is illustrated by dice A and B in Figures 8 and 9. In each
of the figures, (a) shows the pre-voltage-stress IDDQ in the order the vectors were applied at test, (b) shows the post-voltage-stress IDDQ in the order the vectors were applied, the same order as in (a) and (c) presents the "footprint" where post-stress IDDQ is plotted versus the pre-stress IDDQ for each vector.
Figure 8: Die A IDDQ
Figure 9. Die B IDDQ
As described in Section 2, Figure 8a shows a typical IDDQ signature for a chip with an IDDQ-causing defect. There are two groups of IDDQ vectors, one group with relatively low current corresponding to test vectors that appear to put the circuit into a state that does not activate the defect, and another group with higher IDDQ corresponding to test vectors that put the circuit into a state that does activate the defect. The same signature appears to be present in Figure 8b. The footprint in Figure 8c confirms that the same defect signature is present both before and after stress. Specifically, the cluster of points in the lower left corner correspond to vectors that produce low current both before and after stress, while the cluster of points in the upper right corner correspond to vectors that produce high current both before and after stress. Note that while the same vectors produce elevated current both before and after stress, the magnitude of the current increases. The dotted x=y line highlights the fact that the current on the vectors that activate the defect increases from before to after voltage stress by about 300uA, or 3%. This increase could for example be caused by a short whose resistance decreases. By contrast, Figure 9a shows only a single, low level of current which indicates no IDDQ-causing defect activation, while Figure 9b shows two levels of current which indicate that now an IDDQ-causing defect is affecting the circuit; some vectors activate the defect, while others don't. The footprint in Figure 9c shows that information in that all the pre-stress vectors are on the left
side of the x-axis but post-stress some of those formerly non-defect-activating vectors have jumped up into a defect activating category on the y-axis. This footprint reflects the case where a defect comes to have an effect on the circuit only after voltage stress. This could for example be caused by a spot of extra-metal with an oxidation coating [37] that prevents contact prior to voltage stress, but breaks down during voltage stress and allows contact afterward. While the defect on Die A could potentially be detectable via sensitive voltage testing, the defect affecting Die B appears to require voltage stress to become detectable at test. Such a defect would be a reliability risk, as long-term operation could induce the circuit to failure. Note that these chips saw high-quality voltage testing before voltage stress, which indicates normal operation during test is not adequate to induce this defect to failure. As shown in Table 3, for the hardware we studied, the two situations described above occur with similar probability for voltage stress "kills." Specifically in three chips evidence of the same IDDQ-causing defect is present both before and after voltage stress, while in five chips, evidence of an IDDQ-causing defect is present only after the stress. These results suggest a significant number of voltage stress kills show no evidence of voltage degradation before voltage stress, which indicates they could not be detected by even very sensitive voltage testing prior to voltage stressing. Instead, voltage stress is necessary to detect them. (As described above, our analysis can’t draw conclusions on the two chips, for which there is no evidence of an IDDQ-detectable defect either before or after stress.) Table 3: Number of voltage-stress-sensitive chips exhibiting each IDDQ footprint category
After stress, but not before
Before stress, but not after
Before and after stress
Neither before nor after stress
Kills
5
0
3
2
In-situ-only fails
1
0
5
0
Chips that get better
0
6
0
0
IDDQ shifts up
35%
0%
35%
30%
IDDQ shifts down
0%
60%
30%
10%
IDDQcausing defect visible:
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4.4 "In-situ" DVS fails The next question we look into is whether in-situ-only DVS fails are real, defect-related fails as opposed to false fails related to the circuit not being able to operate at outof-spec high-VDD. If they are defect-related we would expect to see evidence of a defect, i.e., a multi-level IDDQ-signature after voltage stress and potentially before voltage stress as well. Chip C in Figure 10 gives an example of a case where there is indeed evidence of a defect. Note that while Figure 10 (a) and (b) leave some ambiguity as to whether or not a defect (the same or different) exists before or after voltage stress, the footprint in Figure 10c shows that indeed a defect exists and apparently causes approximately 60 uA of defect-related IDDQ. Figure 11 shows another example. This time the defect-related IDDQ drops somewhat over voltage stress (from approximately 175uA to 75uA), but the footprint in Figure 11c shows clearly that the same defect exists both before and after voltage stress. Table 3 shows that this is very much the typical case. For this hardware, then, it is clear that the in-situ DVS fails are indeed defect-related and should be rejected at test.
Figure 10. Die C IDDQ
Figure 11: Die D IDDQ
4.5 Chips that get better As shown in Table 3, in the hardware studied, all the chips that “get better,” i.e., fail a voltage test before voltage stress but pass all voltage tests after voltage stress, show evidence of an IDDQ-causing defect before voltage stress but none after voltage stress. In other words, there are degraded voltages potentially detectable by a voltage test only prior to voltage stress, not after. Figure 12 shows an example. This could be caused, for example, by a metal short that “fuses” open due to DVS’s high voltage [40]. Note that for this hardware we were able to confirm that even through burn-in no evidence of an IDDQ-causing Paper 11.3 316
defect became apparent for all of these chips that got better.
Figure 12. Die E IDDQ
(In other lots, we've seen cases where the defect is still present but becomes less severe. A chip illustrating that situation is shown in Figure 13. Note that the defectrelated IDDQ drops from about 300uA to 100uA. The voltage test results suggest the underlying circuit change (e.g., a defect resistance increasing) is enough to allow the circuit to pass voltage testing after voltage stress, but the fact that the same defect clearly remains and continues to affect the circuit suggests that the circuit is not “healed” and should not be shipped.)
Figure 13. Die F IDDQ
4.6 Chips with IDDQ shifts across voltage stress A significant number of chips had IDDQ that shifted either up or down with voltage stress. Comparing IDDQ before versus after voltage stress has been suggested as a test rejection criterion [40] [45]-[47]. We use IDDQ footprints to determine whether an IDDQ-causing defect exists and is visible in the IDDQ footprint for such chips. Table 3 shows the results for chips whose IDDQ increases or decreases by 15% or more. The breakdown of the chips whose IDDQ increases is similar to that for DVS kills. The fact that a significant number of these chips show clear evidence of defects that get worse with stress suggests they should be rejected at test. Moreover, as with DVS kills, the fact that a significant number show no evidence of voltage degradation before stress suggests that voltage stress (or some other stress mechanism) is necessary to get some fails to show themselves, i.e., they will be missed by even very sensitive voltage testing if voltage stress is not applied. The breakdown of chips whose IDDQ decreases is skewed toward the same breakdown seen in the voltage stress
“heal” population – evidence of an IDDQ-causing defect is present before voltage stress, but is no longer present after voltage stress. On a significant additional population, however, evidence of the pre-stress defect remains poststress, even if its effect on the circuit has diminished. 4.7 Discussion of voltage stress results This subsection gives answers to the questions asked in the introduction to Section 4 based on the hardware we studied. • First, we conclude a significant number of voltage stress kills show no evidence of voltage degradation before voltage stress, which indicates they could not be detected by even very sensitive voltage testing prior to voltage stressing. Instead, voltage stress is indeed necessary to detect them. • Next, our in-situ-only fails do show evidence of being caused by defects which suggests in-situ application of DVS enhances quality versus non-in-situ application. • Third, in a significant number of chips, there is no evidence of degraded voltages after voltage stress, which suggests it is indeed important to apply voltage stress after other tests to ensure symptoms of defectexistence are available to be detected on chips subject to the “healing” phenomenon. • Finally, the majority of the IDDQ-shifting population of our hardware was indeed affected by IDDQ-causing defects.
5 Summary This work illustrates the fact that IDDQ testing provides a rich source of information about defect types and behaviors. It demonstrates IDDQ’s effectiveness for understanding both aggregate and individual defect characteristics for both random and systematic defects. It also demonstrates how such understanding can be used to guide important test decisions, such as how to apply voltage stressing and disposition chips based on the results. Even as normal background levels of IDDQ increase to the point of making IDDQ ineffective for production testing, IDDQ testing will continue to be used for analysis and characterization.
References [1] “International Roadmap for Semiconductors (ITRS),” 2003 Edition. Semiconductor Industry Association. [2] J. Soden, et al., “Identifying Defects in DeepSubmicron CMOS ICs,” IEEE Spectrum, Vol. 33, No. 9, pp. 66-71, 1996.
[3] T. Williams, et al., “IDDq Testing for HighPerformance CMOS-The Next 10 Years,” European Design & Test Conference, 1996. [4] A. Gattiker and W. Maly, “Current Signatures,” VLSI Test Symp., pp. 112-117, 1996. [5] A. Gattiker et al., “Current Signatures for Production Testing,” IEEE International Workshop on IDDQ Testing, pp. 25-28, 1996. [6] S. Singh, “IDDQ Testing of Deep Sub-Micron Technologies,” International Workshop on IDDQ Testing, pp. 40-43, 1997. [7] P. Maxwell, et al., “Current Ratios: A Self-Scaling Technique for Production IDDQ Testing,” Int. Test Conf., pp. 738-746, 1999. [8] A. Miller, “IDDQ Testing in Deep Submicron Integrated Circuits,” Int. Test Conf., pp. 724-729, 1999. [9] C. Thibeault, “A Histogram Based Procedure for Current Testing of Active Defects,” Int. Test Conf., pp. 719-723, 1999. [10] S. Kundu, “IDDQ Defect Detection in Deep Submicron CMOS ICs,” Asian Test Symposium, pp. 150-152, 1998. [11] A. Keshavarzi, et al., “Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ,” Int. Test Conf., pp. 1051-1059, 2000. [12] B. Kruseman, et al., “The Future of Delta IDDQ Testing,” Int. Test Conf., pp. 101-100, 2001. [13] S. Sabade and D. Walker, “Improved Wafer-Level Spatial Analysis for IDDQ Limit Setting,” Int. Test Conf., pp. 82-91, 2001. [14] D. Bergman and H. Engler, “Improved IDDQ Testing with Empirical Linear Prediction,” Int. Test Conf., pp. 964-963, 2002. [15] R. Daasch, et al., “Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data,” Int. Test Conf., pp. 1240-1248, 2002. [16] Y. Okuda, “Eigen-signatures for Regularity-Based IDDQ Testing,” VLSI Test Symp., pp. 289-294, 2002. [17] J. Seo and C. Yoon, “Temperature Dependence of Quiescent Currents as a Defect Prognosticator and Evaluation Tool,” Int. Symp for Testing and Failure Analysis, pp. 245-249, 1996. [18] P. Nigh, et al., “Applications and Analysis of IDDq Diagnostic Software,” Int. Test Conf., pp. 319-327, 1997. [19] A. Gattiker and W. Maly, “Current Signatures: Application,” Int. Test Conf., pp. 156-164, 1997. [20] A. Gattiker and W. Maly, “Towards Understanding IDDQ-Only Fails,” Int. Test Conf., pp. 174-183, 1998. [21] A. Gattiker, et al., “Current-Signature-Based Analysis of Complex Test Fails,” 1999 Int. Symp. on Testing and Failure Analysis, 1999. [22] D. Burns, “Locating High Resistance Shorts in CMOS Circuits by Analyzing Supply Current Measurement Paper 11.3 317
Vectors,” International Symposium on Testing and Failure Analysis, pp. 231-237, 1989. [23] R. Aitken “Fault Localization with Current Monitoring,” Int. Test Conf., pp. 623-632, 1991. [24] S. Chakravarty and M. Liu, “Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults,” Design Automation Conference, pp. 353-356, 1992. [25] S. Millman and J. Acken, “Diagnosing CMOS Bridging Faults with Stuck-at, Iddq and Voting Model Fault Dictionaries,” Custom Integrated Circuits Conf., pp. 17.2-17.4, 1994. [26] C. Thibeault, “A Novel Probabilistic Approach for IC Diagnosis Based on Differential Quiescent Current Signatures,” VLSI Test Symp., pp. 80-85, 1997. [27] D. Lavo et al., “Eliminating the Ouija Board; Automatic Thresholds and Probabilistic IDDQ Diagnosis,” Int. Test Conf., pp. 1065-1072, 1999. [28] C. Patel and J. Plusquellic, “A Process and Technology-Tolerant IDDQ Method for IC Diagnosis,” VLSI Test Symp., pp. 145-150, 2001. [29] W. Maly, et al., “Testing Oriented Analysis of CMOS ICs with Opens,” Int. Conf. on Computer-Aided Design, pp. 344-347, 1988. [30] J. Soden, et al., “CMOS IC Stuck-open Fault Electrical Effects and Design Considerations,” Int. Test Conf., pp. 423-430, 1989. [31] P. Nigh, et al., “An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, IDDq and Delay-Fault Testing,” VLSI Test Symp., pp. 459464, 1997. [32] A. Singh, et al., “IDDQ Testing of CMOS Opens: An Experimental Study,” Int. Test Conf., pp. 479-489, 1995. [33] M. Renovell, et al., “Optimal Conditions for Boolean and Current Detection of Floating Gate Faults,” Int. Test Conf., pp. 477-486, 1999. [34] M. Rodgers, “Defect Screening Challenges in the Gigahertz/Nanometer Age: Keeping up with the Tails of Defect Behaviors”, Int. Test Conf., pp. 464-467, 2000.
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[35] A. Righter, et al., “CMOS IC Reliability Indicators and Burn-In Economics,” Int. Test Conf., pp. 194-203, 1998. [36] A. Kinra, “Towards Reducing ‘Functional Only’ Fails for the UltraSPARC Microprocessors,” Int. Test Conf., pp. 147-154, 1999. [37] C. Tsao, “Applying Dynamic Voltage Stressing to Reduce Early Failure Rate,” Int. Reliability Physics Symp., pp. 37-41, 2001. [38] C. Hawkins, et al., “Test and Reliability: Partners in IC Manufacturing. 2,” Design and Test of Computers, IEEE, Vol. 16, Issue 4, pp. 66-73, 1999. [39] A. Wager, “"Semiconductor Defect Reliability Screening and Modeling,” Int. Reliability Physics Symp. Tutorial, 1996. [40] M. Quach, et al., “Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation, Int. Test Conf., pp. 683-692, 2002. [41] J. Chang and E. McCluskey, “SHOrt Voltage Elevation (SHOVE) Test,” IDDQ Workshop, pp. 367378, 1996. [42] H. Hao and E. McCluskey, “Very-Low- Voltage Testing for Weak CMOS Logic ICs”, Int. Test Conf., pp. 275-284, 1993. [43] J. Chang and E. McCluskey, “SHOrt Voltage Elevation (SHOVE) Test,” Int. Test Conf., pp. 45-49, 1996. [44] C. Hawkins et al., “Defect Classes – An Overdue Paradigm for CMOS IC Testing,” Int. Test Conf., pp. 413-425, 1994. [45] A. London, et al., “Use of Voltage Stressing at Wafer Probe for Reliability Predictions,” IEEE Trans. on Semiconductor Manufacturing,” Vol. 12, Issue 4, Nov., pp. 516-522, 1999. [46] T. Powell, et al. “Delta IDDQ for Testing Reliability,” VLSI Test Symp., pp. 439-443, 2000. [47] P. Nigh and A. Gattiker, “Test Method Evaluation Experiments & Data”, Int. Test Conf., pp. 454-463, 2000.
Anne Gattiker
IBM Technology and Systems Group
Abstract This paper demonstrates IDDQ signature analysis of random and systematic defects, including yield detractors and reliability defects. Application is demonstrated for both understanding failure root cause and guiding test decisions.
1 Background IDDQ (defect-free) is increasing significantly, as much as 10X, with each technology generation [1]-[3]. To combat the attendant decreasing effectiveness of traditional IDDQ test, new methods have been developed, including IDDQ delta, IDDQ ratios, multi-parameter and spatial-based IDDQ [4]-[16]. IDDQ has also found use for failure analysis and defect characterization [2][17]-[21], as well as diagnosis/localization [22]-[28]. This paper demonstrates the continued usefulness of IDDQ for characterization for advanced technologies. We describe and apply three methods: signature analysis and classification for understanding defect characteristics, time-dependent analysis for identifying specific types of defects and footprint analysis for guiding reliability-related test decisions.
IBM Austin Research Lab
GND. The defect shown in Figure 1c could be, for example, a short from the output of a multi-input logic gate to VDD or GND, or it could be a short between 2 logic gates. The data shown above was taken for a 0.18um ASIC, but similar IDDQ signature data for technologies ranging from 0.8um to 90nm have been found. We will continue to use this type of IDDQ signature analysis method for future technologies – even if IDDQ for production test becomes less effective. IDDQ signatures contain rich information about the circuit, defect behavior and processing conditions. In this section, we describe capturing that information by classifying signatures into different categories and using the classifications to learn about the nature of the defects occurring on a variety of ASIC chips.
2 IDDQ Signature Analysis and Classification Figure 1 shows three examples of “IDDQ signatures”. Each graph shows the IDDQ measurements for a different chip where 256 IDDQ measurements are taken per chip. IDDQ signature analysis has been discussed in a number of earlier papers [4][19]-[21]. Figure 1 shows an IDDQ measurement for a defect-free chip (Fig 1a. -- all IDDQ measurements are within 1% of each other) and two defective chips. The IDDQ signatures in Figure 1b and Figure 1c are clearly caused by defects in different circuit locations. Using classifications as described in [4], the IDDQ signature shown in Figure 1a is a “0-step”, the signature shown in Figure 1b is a “1-step” and the signature shown in Figure 1c is a “3-step” signature. This is also shown in the sorted signatures in Figure 1d – Figure 1f. The defect in Figure 1b may be a simple defect where an internal wire driven by an inverter is shorted to VDD or
Figure 1. IDDQ signature examples for a 0.18um ASIC. IDDQ measurements in test application order (a-c) and in sorted order (d-f).
ITC INTERNATIONAL TEST CONFERENCE 0-7803-8580-2/04 $20.00 Copyright 2004 IEEE
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2.1 IDDQ Classification Method We have developed software that automatically classifies IDDQ signature data. It sorts the measurements, identifies the “breaks” in the sorted distribution and records which test vectors correspond to each step. It also includes checks for signatures that do not follow the typical stepand-break pattern. Such additional signatures include “time-dependent IDDQ signatures,” identified by looking for IDDQ trends in the unsorted measurement data, and signatures that do not have clear breaks, identified by looking for wider than normal IDDQ measurement spreads. Section 2.2 presents results of applying this classification scheme to a large sample of dice. 2.2
IDDQ classification results for a large sample of ASICs We have applied this IDDQ signature classification method to a large number of ASIC devices (>150,000 chips). Here we show results of an investigation of the repeatability of signatures, i.e., how frequently the same signature is seen on more than one chip, using data from a sample of 0.25um, 0.18um and 0.13um ASICs. Figure 2 shows the number of chips on which each of a large number of signatures occurred. Nearly all signatures appeared only 1-2 chips. The results suggest that for most populations of hardware, it is uncommon to have more than a few different chips produce the same IDDQ signatures. In fact, exceptions can be signs of systematic defects, as described in the next section.
IDDQ Signature Breakdown 63615 Signatures 3-5 chips 1.1%
The wafer map, shown in Figure 3, reflects a “donut” pattern; there are good devices only in the center and on the edge of the wafer.
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Figure 3. Original wafer map showing low yield with strong region dependence. (“Donut” pattern with yielding die on in center and on edge.)
To get to the root cause, the failures were identified using results from both voltage-based testing of scan chain failures and IDDQ. IDDQ analysis identified repeating signatures. Since, as described in Section 2.2, normally we find that abnormal IDDQ signatures are different from one another as one would expect for random defects, our results suggested a systematic problem. We found two IDDQ signatures, shown in Figure 4, that occurred multiple times, while for this wafer, all other IDDQ signatures were unique. Figure 4a’s signature was found for 27 different chips; Figure 4b’s for 102 chips.
>5 chips 0.4%
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Figure 2. IDDQ Signature Breakdown.
2.3 Defect Classification: Systematic defect example An advantage of the fact that most signatures are unique is that exceptions can be used to identify systematic problems. This section describes successful application of our classification method for identifying two clear systematic problems. We applied our analysis to understand the problems underlying a 0.13um ASIC wafer with very low yield. Paper 11.3 310
Figure 4. Repeating IDDQ signatures.
Wafer plots of the location of the IDDQ repeating signatures, shown in Figure 5, indicate that the first repeating signature repeats on about every 9th die, which corresponds to the 3x3 reticle pattern used for this wafer.
A repeating mask problem was later found that explained this failure. The 2nd repeating signature, shown in Figures 4b and 5b, was apparently an edge-related systematic problem. It occurred only on this wafer. After the mask was fixed and the next group of wafers went through test, the problem was never seen again. Unfortunately, we do not have root cause analysis results for this systematic problem since it no longer exists. It is interesting to note that our IDDQ signature classification method was able to identify a few chips that had both types of signatures. An example is shown in Figure 4c.
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(b) Figure 5. Wafer maps with common IDDQ signatures highlighted with dots. Dies with repeating signature from Figure 4a (a) and Figure 4b (b).
3 Time-dependent IDDQ Analysis In this section, we describe another way to look at IDDQ signature data to learn about the mechanisms underlying failures on defective chips. Specifically, we present results of measuring IDDQ for an extended period of time,
which has been found to be a useful method for characterizing defects [29]-[31]. This method has the potential to identify the type of defect causing abnormally high IDDQ – e.g., “open” vs. “short” defects. Timedependent IDDQ measurements are performed in a similar way to normal IDDQ testing except that each measurement is repeated a number of times over an extended period of time (seconds). After the initial circuit conditioning, it is important that the circuit state and measurement circuitry doesn’t change and is stable to ensure that any IDDQ changes versus time are due solely to IDDQ drifts within the IC. Here we describe experimental results from measuring IDDQ versus time using a 0.25um technology CMOS ASIC with 700K logic gates. We took 16 IDDQ measurements for four different IDDQ patterns over 3.2 seconds. We have found that IDDQ measurements for most ICs are very stable over time, e.g., less than 1% change. For defect-free ICs and ICs with bridging defects, we would expect no IDDQ variation over time after the quiescent state is reached. We evaluated a large quantity of ASICS and found: • 150 devices had more than a 5% IDDQ variation vs. time. • All of these 150 devices failed the stuck-at-fault test. 3.1 Examples In this section, we will show interesting examples that had significant time-dependent IDDQ. We will use the following examples to illustrate the various behaviors that were found in the 150 examples with abnormal IDDQ vs. time measurements. Figure 6 shows a series of graphs representing different ICs with abnormal IDDQ vs. time behavior. Table 1 summarizes the observed behaviors. Table 1. Time-dependent IDDQ behavior for example chips.
Devices
IDDQ Behavior
732
Decreases for all patterns.
1163
Increases for all patterns.
254, 4147, 994
Increases, then decreases for all patterns.
4275
Increases, then decreases slightly for 3 patterns. No change for other pattern.
5088, 2441
Increases, then decreases for 1 pattern; decreases (only) for the other 3 patterns.
155
Increases, then decreases for 3 patterns; constant (and low) for 1 pattern.
625
Increases, then decreases for all patterns, but different characteristics for 1 pattern.
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Observations from Time-dependent IDDQ Examples From the examples shown in the previous section, it is clear that defects can cause a wide variety of timedependent IDDQ behavior. Although it is outside the scope of this paper to perform a detailed analysis of timedependent IDDQ behavior (see, for example, [29][30][32][33]), we can use the previous examples and a simple model to better understand our empiricallyobserved time-dependent IDDQ signatures. From the examples in the previous section, we observe: • The time-dependent IDDQ behavior is pattern (circuit state) dependent. • Time-dependent IDDQ behavior varies in terms of magnitudes of the peak IDDQ, time constants for IDDQ changes (some not changing for 2 seconds) and IDDQ vs. time slopes. • Typical time-dependent signatures are: − IDDQ increases (only) − IDDQ decreases (only) − IDDQ increases, then decreases A simple example can explain the most common timedependent IDDQ signatures. Figure 7 shows a CMOS NOR gate whose transistor n1 has a floating gate that is capacitively coupled to GND such that it is stuck off. When A=’1’ and B=’0’, x is in a high-impedance state, i.e., it has no connection through on-transistors to VDD or GND. In the high-impedance state, its steady-state voltage
is determined primarily by the balance between subthreshold, gate and reverse bias pn junction leakage currents flowing into and out of the node. Because those currents are very small, it may take seconds or more for Vx to reach its steady state. If Vx takes on a value between Vtn and VDD-Vtp, IDDQ flows in the downstream NOR gate (C=’0’), reaching a maximum value at approximately VDD/2, as illustrated in Figure 7b. On any given IDDQ test vector, the initial voltage on x is determined by such factors as the preceding state of the driving gate and capacitive coupling to other nodes. As Vx travels from its initial value to its steady state value, it may pass through (and potentially remain in) the IDDQ-causing range of voltages. Doing so can give rise to various signatures observed in Section 3.1, as detailed in Table 2. The pattern-dependent presence or absence of time-dependent IDDQ seen in Section 3.1 can be understood as relating to whether or not the driving gate is sensitized to the open (A=’1’ & B=’0’) and the driven gate is sensitized to x (C=’0’). IDDQ
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(a) (b) Figure 7. (a) Open causing high-impedance node. (b) IDDQ vs. Vx in driven NOR with C=’0.’ Table 2. Starting/final voltages for sensitized NOR input and the resulting IDDQ vs. time signature.
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IDDQ vs. time signature
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Above VDD/2
IDDQ increases, then decreases
Above VDD/2
Below VDD/2
IDDQ increases, then decreases
The true time-dependent IDDQ for defective ICs is more complex than shown in Figure 7 or Table 2. The precise behavior for these chips will depend on many additional factors such as defect resistance, defect location, circuit configuration, timings/transitions at inputs of the defective
logic gate, environmental factors such as VDD voltage and temperature, and capacitive “surroundings” of the defective logic. IDDQ flowing in multiple fanout gates if they existed and current that would flow in gates downstream of the driven NOR if the driven NOR’s output voltage is also at an intermediate value (between Vtn and VDD-Vtp) would also impact the IDDQ signature.
4
IDDQ Footprints: Exploring Voltagestress-sensitive chips
The above sections illustrated getting insight into failure root cause using IDDQ. Understanding failures is important, but test engineers also face daily struggles deciding how tests should be applied and what chips are really “bad.” It is often at best expensive and at worst impossible to base decisions on a gold standard, such as a thorough and representative system test or a thorough and representative burn-in. As a result, test engineers can face having to make test decisions based on incomplete information and even “gut feel.” IDDQ signature analysis with its ability to give insight into the defects causing anomalous behavior, can be a great help in making such test decisions. This section illustrates IDDQ signature analysis in that capacity for a specific example population of chips that present a vexing problem for today’s technologies. 4.1 Motivation As burn-in becomes increasingly untenable due to cost and technology considerations such as thermal runaway and NBTI [1][34], voltage stress is receiving increasing interest as a means to ensure outgoing chip reliability. Physical defects such as metal slivers [35], cracks in insulation layers [36] and metal particles and residues, including metal particles with native oxide coatings [37], are known to be accelerated by voltage stress. However, voltage stress also presents concerns for manufacturers. The first of these concerns is decreasing effectiveness. Latent defect acceleration, typically modeled as proportional to the absolue delta between stress and operating power supply voltage, is decreasing with decreasing nominal voltages, as stress voltages are typically elevated from nominal by the same percentage from technology to technology [38]. Second, Dynamic Voltage Stress (DVS) [37] [39] brings about concerns for false fails. Specifically, because during DVS the part is operated at an out-of-spec high voltage, the part may fail to operate correctly owing to phenomena such as the large IR droop that can occur due to high current draw during scanning [40]. To mitigate that problem, some chipmakers turn expects off when the part is run at DVS voltage, but doing so subjects the manufacturer to risk of missing important bad chips, if the fails are actually due to Paper 11.3 313
defects rather than being false fails. (We use the terms “in-situ DVS” for testing with expects turned on at the DVS voltage and “in-situ-only DVS fail” for chips that fail only when run with expects on at the DVS voltage. Running the part at DVS voltage with expects off and then testing the part at nominal voltage is also known as SHOVE [41].) The third concern is that some chips appear to “heal” during voltage stress in that they fail before DVS, but pass afterward [35][40]. Given that the healing may be only temporary, most manufacturers would like to detect and fail such chips. As a result, there is a concern for unintentionally healing and passing chips unless other parts of the test suite are applied before applying voltage stress. One final concern is how to disposition chips whose IDDQ shifts significantly across voltage stress. This last concern is of particular interest because of the reported large number of chips that undergo such shifts [40]. This section uses IDDQ signature analysis to investigate questions related to these concerns. The answers can be used to guide test engineering decisions. Specifically: • As we face diminishing voltage stress effectiveness we ask: Is voltage stress required for detecting some defects, or could more sensitive voltage testing suffice? (For example, very-low-voltage testing [42][43] or at-speed testing.) • As we recognize the potential for “false fails” during in-situ DVS we ask: Are in-situ-only DVS fails defect-related and therefore is in-situ DVS testing necessary? • As we recognize the potential for defective chips to heal (possibly temporarily), we ask: Is there detectable degradation remaining on apparently “healed” chips? If there is not, even very sensitive voltage testing cannot detect such chips after voltage stress and it therefore becomes especially important to apply other tests before voltage stress during manufacturing testing. • As we recognize the prevalence of chips that shift in terms of IDDQ, we ask: Are IDDQ shifts across voltage stress related to defects? 4.2 Context of study Our investigation is applicable to static CMOS circuits. In such circuits, defects such as shorts cause static current to flow when activated. We’ll term such defects “IDDQcausing” defects. Static current flow implies voltage drops (across defect resistances and/or transistor equivalent resistances). The voltage drops imply degraded voltages on circuit nodes versus full logic ‘0’ and ‘1’ voltages, which in turn cause degradation of circuit operation. The
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degradation can range from severe (hard fails) to subtle (e.g., timing or noise margin degradation). A physical defect may exist without causing any degradation of circuit voltages. For example, an area of extra conducting material may exist but not make physical contact to two circuit nodes such that the two are shorted. If a shorting defect does make contact (and the test vectors activate the defect), defect-related IDDQ will flow and circuit node voltages will be degraded. If the short doesn’t make contact, there will be no such degraded voltages. Note that in the latter case, the defect cannot be detected by voltage tests because of the absence of degraded voltages. We use the presence of elevated IDDQ as evidence that there exists a defect causing degraded voltages on a manufactured circuit. We use “IDDQ footprints” [20][21] to determine whether or not elevated IDDQ is present. An IDDQ footprint plots the IDDQ on each vector after voltage stress versus IDDQ on the same vector before voltage stress. It reflects the difference in IDDQ-causing defects present between the two test levels. Although the footprint method is not perfect, it is highly sensitive to small defect currents in the presence of high normal background leakage currents. While it may be very difficult to implement a production test technique with similar sensitivity, during characterization for test guidance purposes, we are able to detect very small (tens of uAs) defect-related current. (Some defects, such as opens that behave as stuck-ats, are well-known not to produce elevated static current [44]. Our analyses don’t apply in such cases. However, our observation is that most voltage-stress-sensitive fails are related to IDDQ-causing defects, as reflected in the results presented in this section, so that the described methods apply.) The presented results are from the testing of an example lot of a 0.25um ASIC. 4.3 Voltage stress "kills" A voltage stress "kill" passes all voltage testing applied before voltage stress, but fails that same voltage testing after voltage stress. On such chips, it could be the case that the defect that causes the voltage test fail existed and affected the circuit before voltage stress, but its effect on the circuit became more severe as a result of voltage stress. Alternatively, it could be the case that there was no defect affecting the circuit before voltage stress, but one comes into play during or after voltage stress. We are interested in determining for our hardware whether or not before voltage stress there was already evidence of degraded circuit voltages. IDDQ evidence suggesting the existence of both scenarios is illustrated by dice A and B in Figures 8 and 9. In each
of the figures, (a) shows the pre-voltage-stress IDDQ in the order the vectors were applied at test, (b) shows the post-voltage-stress IDDQ in the order the vectors were applied, the same order as in (a) and (c) presents the "footprint" where post-stress IDDQ is plotted versus the pre-stress IDDQ for each vector.
Figure 8: Die A IDDQ
Figure 9. Die B IDDQ
As described in Section 2, Figure 8a shows a typical IDDQ signature for a chip with an IDDQ-causing defect. There are two groups of IDDQ vectors, one group with relatively low current corresponding to test vectors that appear to put the circuit into a state that does not activate the defect, and another group with higher IDDQ corresponding to test vectors that put the circuit into a state that does activate the defect. The same signature appears to be present in Figure 8b. The footprint in Figure 8c confirms that the same defect signature is present both before and after stress. Specifically, the cluster of points in the lower left corner correspond to vectors that produce low current both before and after stress, while the cluster of points in the upper right corner correspond to vectors that produce high current both before and after stress. Note that while the same vectors produce elevated current both before and after stress, the magnitude of the current increases. The dotted x=y line highlights the fact that the current on the vectors that activate the defect increases from before to after voltage stress by about 300uA, or 3%. This increase could for example be caused by a short whose resistance decreases. By contrast, Figure 9a shows only a single, low level of current which indicates no IDDQ-causing defect activation, while Figure 9b shows two levels of current which indicate that now an IDDQ-causing defect is affecting the circuit; some vectors activate the defect, while others don't. The footprint in Figure 9c shows that information in that all the pre-stress vectors are on the left
side of the x-axis but post-stress some of those formerly non-defect-activating vectors have jumped up into a defect activating category on the y-axis. This footprint reflects the case where a defect comes to have an effect on the circuit only after voltage stress. This could for example be caused by a spot of extra-metal with an oxidation coating [37] that prevents contact prior to voltage stress, but breaks down during voltage stress and allows contact afterward. While the defect on Die A could potentially be detectable via sensitive voltage testing, the defect affecting Die B appears to require voltage stress to become detectable at test. Such a defect would be a reliability risk, as long-term operation could induce the circuit to failure. Note that these chips saw high-quality voltage testing before voltage stress, which indicates normal operation during test is not adequate to induce this defect to failure. As shown in Table 3, for the hardware we studied, the two situations described above occur with similar probability for voltage stress "kills." Specifically in three chips evidence of the same IDDQ-causing defect is present both before and after voltage stress, while in five chips, evidence of an IDDQ-causing defect is present only after the stress. These results suggest a significant number of voltage stress kills show no evidence of voltage degradation before voltage stress, which indicates they could not be detected by even very sensitive voltage testing prior to voltage stressing. Instead, voltage stress is necessary to detect them. (As described above, our analysis can’t draw conclusions on the two chips, for which there is no evidence of an IDDQ-detectable defect either before or after stress.) Table 3: Number of voltage-stress-sensitive chips exhibiting each IDDQ footprint category
After stress, but not before
Before stress, but not after
Before and after stress
Neither before nor after stress
Kills
5
0
3
2
In-situ-only fails
1
0
5
0
Chips that get better
0
6
0
0
IDDQ shifts up
35%
0%
35%
30%
IDDQ shifts down
0%
60%
30%
10%
IDDQcausing defect visible:
Paper 11.3 315
4.4 "In-situ" DVS fails The next question we look into is whether in-situ-only DVS fails are real, defect-related fails as opposed to false fails related to the circuit not being able to operate at outof-spec high-VDD. If they are defect-related we would expect to see evidence of a defect, i.e., a multi-level IDDQ-signature after voltage stress and potentially before voltage stress as well. Chip C in Figure 10 gives an example of a case where there is indeed evidence of a defect. Note that while Figure 10 (a) and (b) leave some ambiguity as to whether or not a defect (the same or different) exists before or after voltage stress, the footprint in Figure 10c shows that indeed a defect exists and apparently causes approximately 60 uA of defect-related IDDQ. Figure 11 shows another example. This time the defect-related IDDQ drops somewhat over voltage stress (from approximately 175uA to 75uA), but the footprint in Figure 11c shows clearly that the same defect exists both before and after voltage stress. Table 3 shows that this is very much the typical case. For this hardware, then, it is clear that the in-situ DVS fails are indeed defect-related and should be rejected at test.
Figure 10. Die C IDDQ
Figure 11: Die D IDDQ
4.5 Chips that get better As shown in Table 3, in the hardware studied, all the chips that “get better,” i.e., fail a voltage test before voltage stress but pass all voltage tests after voltage stress, show evidence of an IDDQ-causing defect before voltage stress but none after voltage stress. In other words, there are degraded voltages potentially detectable by a voltage test only prior to voltage stress, not after. Figure 12 shows an example. This could be caused, for example, by a metal short that “fuses” open due to DVS’s high voltage [40]. Note that for this hardware we were able to confirm that even through burn-in no evidence of an IDDQ-causing Paper 11.3 316
defect became apparent for all of these chips that got better.
Figure 12. Die E IDDQ
(In other lots, we've seen cases where the defect is still present but becomes less severe. A chip illustrating that situation is shown in Figure 13. Note that the defectrelated IDDQ drops from about 300uA to 100uA. The voltage test results suggest the underlying circuit change (e.g., a defect resistance increasing) is enough to allow the circuit to pass voltage testing after voltage stress, but the fact that the same defect clearly remains and continues to affect the circuit suggests that the circuit is not “healed” and should not be shipped.)
Figure 13. Die F IDDQ
4.6 Chips with IDDQ shifts across voltage stress A significant number of chips had IDDQ that shifted either up or down with voltage stress. Comparing IDDQ before versus after voltage stress has been suggested as a test rejection criterion [40] [45]-[47]. We use IDDQ footprints to determine whether an IDDQ-causing defect exists and is visible in the IDDQ footprint for such chips. Table 3 shows the results for chips whose IDDQ increases or decreases by 15% or more. The breakdown of the chips whose IDDQ increases is similar to that for DVS kills. The fact that a significant number of these chips show clear evidence of defects that get worse with stress suggests they should be rejected at test. Moreover, as with DVS kills, the fact that a significant number show no evidence of voltage degradation before stress suggests that voltage stress (or some other stress mechanism) is necessary to get some fails to show themselves, i.e., they will be missed by even very sensitive voltage testing if voltage stress is not applied. The breakdown of chips whose IDDQ decreases is skewed toward the same breakdown seen in the voltage stress
“heal” population – evidence of an IDDQ-causing defect is present before voltage stress, but is no longer present after voltage stress. On a significant additional population, however, evidence of the pre-stress defect remains poststress, even if its effect on the circuit has diminished. 4.7 Discussion of voltage stress results This subsection gives answers to the questions asked in the introduction to Section 4 based on the hardware we studied. • First, we conclude a significant number of voltage stress kills show no evidence of voltage degradation before voltage stress, which indicates they could not be detected by even very sensitive voltage testing prior to voltage stressing. Instead, voltage stress is indeed necessary to detect them. • Next, our in-situ-only fails do show evidence of being caused by defects which suggests in-situ application of DVS enhances quality versus non-in-situ application. • Third, in a significant number of chips, there is no evidence of degraded voltages after voltage stress, which suggests it is indeed important to apply voltage stress after other tests to ensure symptoms of defectexistence are available to be detected on chips subject to the “healing” phenomenon. • Finally, the majority of the IDDQ-shifting population of our hardware was indeed affected by IDDQ-causing defects.
5 Summary This work illustrates the fact that IDDQ testing provides a rich source of information about defect types and behaviors. It demonstrates IDDQ’s effectiveness for understanding both aggregate and individual defect characteristics for both random and systematic defects. It also demonstrates how such understanding can be used to guide important test decisions, such as how to apply voltage stressing and disposition chips based on the results. Even as normal background levels of IDDQ increase to the point of making IDDQ ineffective for production testing, IDDQ testing will continue to be used for analysis and characterization.
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