Read circuit on nonvolatile semiconductor memory
US006674668B2
(12)
(54)
United States Patent
(10) Patent N0.:
Ikehashi et al.
(45) Date of Patent:
5,703,809 A
* 12/1997 Hull et al. ........... .. 365/185.28
SEMICONDUCTOR MEMORY
5,812,456 A
*
(75) Inventors: Tamio Ikehashi, Kamakura (JP);
Kenichi Imamiya, Tokyo (JP); .
,
.
.
.
.
.
gallghilya et a1‘
,
015
6,118,699 A
*
6,166,990 A
AsslgneeZ Kabushlk' Kalsha Toshlba, Kawasakl
Notice:
10/1999 Nagaoka
2
.
.
9/1998 Hull et al. ........... .. 365/185.16
1/1999 Sato
59737984 A
Jumchm) Noda’ Yokohama (JP)
(*)
Jan. 6, 2004
READ CIRCUIT ON NONVOLATILE
5,864,511 A
(73)
US 6,674,668 B2
1
9/2000 Tatsumi et a1. ...... .. 365/185.18 12/2000
Ooishi et al.
6,438,038 B2 *
8/2002 Ikehashi et a1. ..... .. 365/185.24
(JP)
2001/0006479 A1 * 2002/0027803 A1 *
7/2001 Ikehashi et al. ..... .. 365/18524 3/2002
Subject to any disclaimer, the term of this
2002/0196667 A1 * 12/2002 Ikehashi et a1. ..... .. 365/185.24
patent is extended or adjusted under 35
USC' 154(k)) by 0 days_
FOREIGN PATENT DOCUMENTS
(21) Appl. No.: 10/188,148 _
(22)
P116011
J ul- 3, 2002
(65)
JP
40-3154287 A
7/1991
JP
40-5325583 A
12/1993
JP
2000-090685 A
3/2000
JP
2000-149581
5/2000
Prior Publication Data
OTHER PUBLICATIONS
Us 2002/0196667 A1 D60 26, 2002
R l t dUS A eae
..
l_
t_
Raul—Adrian Cernea, et al., “ A 1Mb Flash EEPROM”,
D t
pplcalon
IEEE ISSCC Dig. Tech. Paper, pp. 331—333, 1989.
aa
* cited by examiner (62)
Division of application No. 09/745,666, ?led on Dec. 26,
2000, now Pat. No. 6,438,038.
(30)
Foreign Application Priority Data
Dec. 28, 1999
(JP) ......................................... .. 11-373069
US. Cl. .......................... .. 365/185.24; 365/189.01;
( ) 58
( )
365/205 365/185 18 365/189 09_ 365/227 F. M f S
1e
0
h ’
'
’ 365/185 01’ 185 24
earc36
185 18 '
’
’
'
89’ 09
_
’
'
(57)
ABSTRACT
An tllNvsélg?node indfal 51211559096 mt gelift’lfsly prec arge '
. Grape en la Ona
me 15 I656 ’
e
1
me
(BLS node) is precharged. In this event, a clamp MOS transistor in a sense ampli?er is in ON state, and an SAnode
is also precharged simultaneously. Aprecharge level is set to ’
.
(56)
_
(74) Attorney, Agent, or Firm—Banner & Witcoff, Ltd.
(51) Int. c1.7 ................................................ .. G11C 7/00 52
_
Primary Examzner—V1et Q. Nguyen
a value loWer than
a threshold voltage
of an inverter.
Subsequently, When SAEN transitions to “H,” a sense opera
References Clted US. PATENT DOCUMENTS * b d
tion is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node sloWly approaches to Vss. Achange in the potential at the SA
2
IP03 :11 ................... .. 327/37
node is detected by the inverter'
5,587,952 A
* 12/1996 Kitsukawa et al. ....... .. 365/207
5,604,707 A
2/1997 Kuge et a1.
15 Claims, 16 Drawing Sheets
INVSRC
SAREF
20; VCLAMP GENERATING CIRCUIT
W: CHANNEL W1DTH
U.S. Patent
Jan. 6, 2004
Sheet 4 0f 16
SELECT GATE LINE (SGDi) —--—~
wono LINE (Wi)—|
US 6,674,668 B2
"
P/ M2
SELECT GATE LINE (SGSi) —— ,__/ M3
Vss ~BLj
F I G. 4
__1 N M4
V¢gref____H ,_/M5 (REFERENCE CELL) Vsg=3.5V——~—-I N M6
Vss
F|G.5
U.S. Patent
Jan. 6, 2004
Sheet 8 0f 16
US 6,674,668 B2
(1)“ Nsv
VCLAMP
MI4~ BLREF MN1~
EN —1 ~MN9 Vss
F I (3.9
Vdd
ENn-l
VBGR -
+
Vdd
MpA
, 1
I
Fl
MPB
vssJ 1 I
H _ _
® 'Ns
Ns
F|G.10
U.S. Patent
Jan. 6, 2004
Sheet 9 0f 16
US 6,674,668 B2
518: GENERATING INVSRC CIRCUIT
,
i 5
21: SAREF PRECHARGE CIRCUIT
-’
(‘NATE/ea“, EN '
~LMP10
SAEN;
{
;
LI »——§/MP11
m 5 E
5
g
»~;MN12 DUMMY 22 ~
I______ __V§§__j
COLUMN GATE
I, _____
H
“ (PT (Es/1A) 23m REFERENCE CELL
;
~§~Ml4
—E-
6+’ MN1
:
EN
g
HEJMNQ VCLAMP 2o; GENERATING CIRCUlT
U.S. Patent
Jan. 6, 2004
Sheet 10 0f 16
US 6,674,668 B2
- VBGR=1.23V - VBGR2=0.5V
- Vcgref=1.0V~2.5V
(REGULATE AT 0.1V INTERVALS) ' Vdd
\R3 (VARIABLE RESISTOR) \R4 Vss
F|G.12 Na
Na
JR3 =
‘LE’ JRS
Nb
i T16 1R6 J. Nb
\
'
Y
J
U.S. Patent
Jan. 6, 2004
Sheet 13 0f 16
US 6,674,668 B2
w S/Ai
(1 UNIT)
.3
12
,VCLAMP 3
‘.17
W: CAHNNEL WIDTH
COLUMN GATE-“15
| ~M2 (SELECTED cm) —4
U.S. Patent
(
Jan. 6, 2004
Sheet 15 0f 16
US 6,674,668 B2
U.S. Patent
Jan. 6,2004
Sheet 16 0f 16
US 6,674,668 B2 N S/Ai
Vdd
INVSRC GENERATING
l .- I RBL"
DUMMY COLUMN GATE
Icell l a BL COLUMN GATE DUMMY
_4,L[___WCRD LINE
WORD LINE
v CELL
REFERENCE
\MEMORY
V55
/
CELL
w; CHANNEL WIDTH
FIG.19
Vss
US 6,674,668 B2 1
2 This read circuit has a so-called double-ended type Which
READ CIRCUIT ON NONVOLATILE SEMICONDUCTOR MEMORY
compares a current Iref ?oWing into a reference cell With a current ?oWing into a selected memory cell to determine
CROSS-REFERENCE TO RELATED APPLICATIONS
data in the memory cell (“1” or “0”). S/Ai indicates one sense ampli?er. Generally, a plurality
This application is a divisional of prior US. application
of sense ampli?ers are disposed in a memory chip. Also, a
Ser. No. 09/745,666, ?led Dec. 26, 2000, now US. Pat. No. 6,438,038, Which is based upon and claims the bene?t of
plurality of bit lines BL1, . . . , BLn are connected to a single
sense ampli?er S/Ai through a column gate. Further, a read control signal generating circuit is connected to the sense
priority from the prior Japanese Patent Application No. 11-373069, ?led Dec. 28, 1999, the entire contents of Which are incorporated herein by reference.
10
BACKGROUND OF THE INVENTION The present invention relates to a read circuit of a non
volatile semiconductor memory. 1. Types of Fast Random Accessible Nonvolatile Semicon ductor Memories: As fast random accessible nonvolatile semiconductor
memories, EEPROM, NOR cell type ?ash memory, and the like are knoWn. In recent years, neW types of memories based on a NAND cell type ?ash memory have been devised
15
memory cell is identical in structure to the reference cell, the reference cell is set to “1”—programming state (negative
threshold voltage state). 20
As a read potential (ground potential) is provided to a selected Word line and a dummy Word line, and the cell current Iref ?oWs through the reference cell, a current ?oWing into an RSA node 33 (RBL) is set to Iref/2 (=Icell/2) by current mirror circuits MR1, MR2. Reference letter W
25
represents the siZe of a transistor (channel Width). When a selected memory cell stores “1” data (in the case
of “1”—programming cell), Icell ?oWs into an SA node 33 (BL), so that the potential at the SA node 33 becomes loWer than the potential at the RSA node 33.
select transistors sandWiching the memory cell, and has the folloWing characteristics as compared With the EEPROM or ?ash memory:
(1) ability of fast read in units of 16 bits (=Word);
30
On the other hand, When a selected memory cell stores
“0” data (in the case of “0”—programming cell), little
(2) a small erasure unit of 32 Words;
(3) ability of performing a read operation at loW poWer
consumption; and (4) relatively small memory cell siZe. Speci?cally, the 3Tr-NAND is, for example, smaller in
generating circuit includes a reference cell. Then, upon reading, the cell current Iref of the reference cell is set to be substantially equal to a cell current Icell ?oWing into a memory cell Which stores “1” data (“1”—
programming cell). In other Words, assuming that the
as a memory having a fast random access characteristic in
parallel With these memories. One of such memories is a so-called “3Tr-NAND.” The 3Tr-NAND is a memory Which has each cell unit composed of three transistors, i.e., one memory cell and tWo
ampli?er S/Ai, and provides a read control signal to the sense ampli?er S/Ai upon reading. The read control signal
35
current ?oWs into the SA node 33 (BL), so that the potential at the SA node 33 becomes higher than the potential at the RSA node 33. Therefore, data in a selected memory cell (“1” or “0”) can
be discriminated by detecting a potential difference betWeen
memory cell siZe as compared With the EEPROM, and can therefore accomplish a reduction in chip siZe, a reduction in
the SA node 33 and the RSA node 33 using a differential
manufacturing cost, and the like. Also, the 3Tr-NAND requires loWer poWer consumption and provides a smaller
2.2. Consumed Current during Read In the NOR cell type ?ash memory, When the read circuit as described above is used, for eXample, it can be thought
ampli?er DA. 40
erasure unit as compared With a NOR cell type ?ash memory
(for further details on 3Tr-NAND, see for eXample Japanese Patent Application No. 11-10676 (?led on Jan. 19, 1999)). 2. Read Circuit of NOR Cell Type Flash Memory
that a consumed current during a read mainly consists of the
folloWing three currents: cell current: Icell
As to an access time upon reading, the 3Tr-NAND is 45
equivalent to the NOR cell type ?ash memory. Speci?cally, the tWo memories require approximately 100 nsec. As such, the folloWing description Will be made on a read circuit of a NOR cell type ?ash memory as a conventional read circuit.
Also, for facilitating the understanding of the folloWing
50
description, de?nitions are made as folloWs beforehand
In this event, since 16 sets of read circuits are required, a
a memory cell With a negative threshold voltage is a memory cell Which stores “1” data (or “1”—programming cell or a erasure cell). It should be noted that the threshold voltage of a memory cell, for eXample, a memory cell of a stacked gate structure
55
having a ?oating gate electrode, is determined by the quan tity of electrons in the ?oating gate electrode. Also, the quantity of electrons in the ?oating gate electrode is controlled, for eXample, by applying an F-N tunnel current
60
total value Itot of consumed currents during the read is calculated as: 3
1:01:16 >
(12)
(54)
United States Patent
(10) Patent N0.:
Ikehashi et al.
(45) Date of Patent:
5,703,809 A
* 12/1997 Hull et al. ........... .. 365/185.28
SEMICONDUCTOR MEMORY
5,812,456 A
*
(75) Inventors: Tamio Ikehashi, Kamakura (JP);
Kenichi Imamiya, Tokyo (JP); .
,
.
.
.
.
.
gallghilya et a1‘
,
015
6,118,699 A
*
6,166,990 A
AsslgneeZ Kabushlk' Kalsha Toshlba, Kawasakl
Notice:
10/1999 Nagaoka
2
.
.
9/1998 Hull et al. ........... .. 365/185.16
1/1999 Sato
59737984 A
Jumchm) Noda’ Yokohama (JP)
(*)
Jan. 6, 2004
READ CIRCUIT ON NONVOLATILE
5,864,511 A
(73)
US 6,674,668 B2
1
9/2000 Tatsumi et a1. ...... .. 365/185.18 12/2000
Ooishi et al.
6,438,038 B2 *
8/2002 Ikehashi et a1. ..... .. 365/185.24
(JP)
2001/0006479 A1 * 2002/0027803 A1 *
7/2001 Ikehashi et al. ..... .. 365/18524 3/2002
Subject to any disclaimer, the term of this
2002/0196667 A1 * 12/2002 Ikehashi et a1. ..... .. 365/185.24
patent is extended or adjusted under 35
USC' 154(k)) by 0 days_
FOREIGN PATENT DOCUMENTS
(21) Appl. No.: 10/188,148 _
(22)
P116011
J ul- 3, 2002
(65)
JP
40-3154287 A
7/1991
JP
40-5325583 A
12/1993
JP
2000-090685 A
3/2000
JP
2000-149581
5/2000
Prior Publication Data
OTHER PUBLICATIONS
Us 2002/0196667 A1 D60 26, 2002
R l t dUS A eae
..
l_
t_
Raul—Adrian Cernea, et al., “ A 1Mb Flash EEPROM”,
D t
pplcalon
IEEE ISSCC Dig. Tech. Paper, pp. 331—333, 1989.
aa
* cited by examiner (62)
Division of application No. 09/745,666, ?led on Dec. 26,
2000, now Pat. No. 6,438,038.
(30)
Foreign Application Priority Data
Dec. 28, 1999
(JP) ......................................... .. 11-373069
US. Cl. .......................... .. 365/185.24; 365/189.01;
( ) 58
( )
365/205 365/185 18 365/189 09_ 365/227 F. M f S
1e
0
h ’
'
’ 365/185 01’ 185 24
earc36
185 18 '
’
’
'
89’ 09
_
’
'
(57)
ABSTRACT
An tllNvsélg?node indfal 51211559096 mt gelift’lfsly prec arge '
. Grape en la Ona
me 15 I656 ’
e
1
me
(BLS node) is precharged. In this event, a clamp MOS transistor in a sense ampli?er is in ON state, and an SAnode
is also precharged simultaneously. Aprecharge level is set to ’
.
(56)
_
(74) Attorney, Agent, or Firm—Banner & Witcoff, Ltd.
(51) Int. c1.7 ................................................ .. G11C 7/00 52
_
Primary Examzner—V1et Q. Nguyen
a value loWer than
a threshold voltage
of an inverter.
Subsequently, When SAEN transitions to “H,” a sense opera
References Clted US. PATENT DOCUMENTS * b d
tion is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node sloWly approaches to Vss. Achange in the potential at the SA
2
IP03 :11 ................... .. 327/37
node is detected by the inverter'
5,587,952 A
* 12/1996 Kitsukawa et al. ....... .. 365/207
5,604,707 A
2/1997 Kuge et a1.
15 Claims, 16 Drawing Sheets
INVSRC
SAREF
20; VCLAMP GENERATING CIRCUIT
W: CHANNEL W1DTH
U.S. Patent
Jan. 6, 2004
Sheet 4 0f 16
SELECT GATE LINE (SGDi) —--—~
wono LINE (Wi)—|
US 6,674,668 B2
"
P/ M2
SELECT GATE LINE (SGSi) —— ,__/ M3
Vss ~BLj
F I G. 4
__1 N M4
V¢gref____H ,_/M5 (REFERENCE CELL) Vsg=3.5V——~—-I N M6
Vss
F|G.5
U.S. Patent
Jan. 6, 2004
Sheet 8 0f 16
US 6,674,668 B2
(1)“ Nsv
VCLAMP
MI4~ BLREF MN1~
EN —1 ~MN9 Vss
F I (3.9
Vdd
ENn-l
VBGR -
+
Vdd
MpA
, 1
I
Fl
MPB
vssJ 1 I
H _ _
® 'Ns
Ns
F|G.10
U.S. Patent
Jan. 6, 2004
Sheet 9 0f 16
US 6,674,668 B2
518: GENERATING INVSRC CIRCUIT
,
i 5
21: SAREF PRECHARGE CIRCUIT
-’
(‘NATE/ea“, EN '
~LMP10
SAEN;
{
;
LI »——§/MP11
m 5 E
5
g
»~;MN12 DUMMY 22 ~
I______ __V§§__j
COLUMN GATE
I, _____
H
“ (PT (Es/1A) 23m REFERENCE CELL
;
~§~Ml4
—E-
6+’ MN1
:
EN
g
HEJMNQ VCLAMP 2o; GENERATING CIRCUlT
U.S. Patent
Jan. 6, 2004
Sheet 10 0f 16
US 6,674,668 B2
- VBGR=1.23V - VBGR2=0.5V
- Vcgref=1.0V~2.5V
(REGULATE AT 0.1V INTERVALS) ' Vdd
\R3 (VARIABLE RESISTOR) \R4 Vss
F|G.12 Na
Na
JR3 =
‘LE’ JRS
Nb
i T16 1R6 J. Nb
\
'
Y
J
U.S. Patent
Jan. 6, 2004
Sheet 13 0f 16
US 6,674,668 B2
w S/Ai
(1 UNIT)
.3
12
,VCLAMP 3
‘.17
W: CAHNNEL WIDTH
COLUMN GATE-“15
| ~M2 (SELECTED cm) —4
U.S. Patent
(
Jan. 6, 2004
Sheet 15 0f 16
US 6,674,668 B2
U.S. Patent
Jan. 6,2004
Sheet 16 0f 16
US 6,674,668 B2 N S/Ai
Vdd
INVSRC GENERATING
l .- I RBL"
DUMMY COLUMN GATE
Icell l a BL COLUMN GATE DUMMY
_4,L[___WCRD LINE
WORD LINE
v CELL
REFERENCE
\MEMORY
V55
/
CELL
w; CHANNEL WIDTH
FIG.19
Vss
US 6,674,668 B2 1
2 This read circuit has a so-called double-ended type Which
READ CIRCUIT ON NONVOLATILE SEMICONDUCTOR MEMORY
compares a current Iref ?oWing into a reference cell With a current ?oWing into a selected memory cell to determine
CROSS-REFERENCE TO RELATED APPLICATIONS
data in the memory cell (“1” or “0”). S/Ai indicates one sense ampli?er. Generally, a plurality
This application is a divisional of prior US. application
of sense ampli?ers are disposed in a memory chip. Also, a
Ser. No. 09/745,666, ?led Dec. 26, 2000, now US. Pat. No. 6,438,038, Which is based upon and claims the bene?t of
plurality of bit lines BL1, . . . , BLn are connected to a single
sense ampli?er S/Ai through a column gate. Further, a read control signal generating circuit is connected to the sense
priority from the prior Japanese Patent Application No. 11-373069, ?led Dec. 28, 1999, the entire contents of Which are incorporated herein by reference.
10
BACKGROUND OF THE INVENTION The present invention relates to a read circuit of a non
volatile semiconductor memory. 1. Types of Fast Random Accessible Nonvolatile Semicon ductor Memories: As fast random accessible nonvolatile semiconductor
memories, EEPROM, NOR cell type ?ash memory, and the like are knoWn. In recent years, neW types of memories based on a NAND cell type ?ash memory have been devised
15
memory cell is identical in structure to the reference cell, the reference cell is set to “1”—programming state (negative
threshold voltage state). 20
As a read potential (ground potential) is provided to a selected Word line and a dummy Word line, and the cell current Iref ?oWs through the reference cell, a current ?oWing into an RSA node 33 (RBL) is set to Iref/2 (=Icell/2) by current mirror circuits MR1, MR2. Reference letter W
25
represents the siZe of a transistor (channel Width). When a selected memory cell stores “1” data (in the case
of “1”—programming cell), Icell ?oWs into an SA node 33 (BL), so that the potential at the SA node 33 becomes loWer than the potential at the RSA node 33.
select transistors sandWiching the memory cell, and has the folloWing characteristics as compared With the EEPROM or ?ash memory:
(1) ability of fast read in units of 16 bits (=Word);
30
On the other hand, When a selected memory cell stores
“0” data (in the case of “0”—programming cell), little
(2) a small erasure unit of 32 Words;
(3) ability of performing a read operation at loW poWer
consumption; and (4) relatively small memory cell siZe. Speci?cally, the 3Tr-NAND is, for example, smaller in
generating circuit includes a reference cell. Then, upon reading, the cell current Iref of the reference cell is set to be substantially equal to a cell current Icell ?oWing into a memory cell Which stores “1” data (“1”—
programming cell). In other Words, assuming that the
as a memory having a fast random access characteristic in
parallel With these memories. One of such memories is a so-called “3Tr-NAND.” The 3Tr-NAND is a memory Which has each cell unit composed of three transistors, i.e., one memory cell and tWo
ampli?er S/Ai, and provides a read control signal to the sense ampli?er S/Ai upon reading. The read control signal
35
current ?oWs into the SA node 33 (BL), so that the potential at the SA node 33 becomes higher than the potential at the RSA node 33. Therefore, data in a selected memory cell (“1” or “0”) can
be discriminated by detecting a potential difference betWeen
memory cell siZe as compared With the EEPROM, and can therefore accomplish a reduction in chip siZe, a reduction in
the SA node 33 and the RSA node 33 using a differential
manufacturing cost, and the like. Also, the 3Tr-NAND requires loWer poWer consumption and provides a smaller
2.2. Consumed Current during Read In the NOR cell type ?ash memory, When the read circuit as described above is used, for eXample, it can be thought
ampli?er DA. 40
erasure unit as compared With a NOR cell type ?ash memory
(for further details on 3Tr-NAND, see for eXample Japanese Patent Application No. 11-10676 (?led on Jan. 19, 1999)). 2. Read Circuit of NOR Cell Type Flash Memory
that a consumed current during a read mainly consists of the
folloWing three currents: cell current: Icell
As to an access time upon reading, the 3Tr-NAND is 45
equivalent to the NOR cell type ?ash memory. Speci?cally, the tWo memories require approximately 100 nsec. As such, the folloWing description Will be made on a read circuit of a NOR cell type ?ash memory as a conventional read circuit.
Also, for facilitating the understanding of the folloWing
50
description, de?nitions are made as folloWs beforehand
In this event, since 16 sets of read circuits are required, a
a memory cell With a negative threshold voltage is a memory cell Which stores “1” data (or “1”—programming cell or a erasure cell). It should be noted that the threshold voltage of a memory cell, for eXample, a memory cell of a stacked gate structure
55
having a ?oating gate electrode, is determined by the quan tity of electrons in the ?oating gate electrode. Also, the quantity of electrons in the ?oating gate electrode is controlled, for eXample, by applying an F-N tunnel current
60
total value Itot of consumed currents during the read is calculated as: 3
1:01:16 >
