rf power amplifiers for emerging wireless ... - Semantic Scholar
RF POWER AMPLIFIERS FOR EMERGING WIRELESS COMMUNICATIONS: SINGLE BRANCH VS. MULTI-BRANCH ARCHITECTURES Oualid Hammi iRadio Lab / Schulich School of Engineering University of Calgary, Calgary, AB, Canada email: [email protected]
Slim Boumaiza iRadio Lab / Schulich School of Engineering University of Calgary, Calgary, AB, Canada email: [email protected]
Jangheon Kim MMIC Lab / Dept. of Electrical Engineering POSTECH, Republic of Korea email: [email protected]
Sungchul Hong MMIC Lab / Dept. of Electrical Engineering POSTECH, Republic of Korea email: [email protected]
Ildu Kim MMIC Lab / Dept. of Electrical Engineering POSTECH, Republic of Korea email: [email protected]
Bumman Kim MMIC Lab / Dept. of Electrical Engineering POSTECH, Republic of Korea email: [email protected]
Fadhel Ghannouchi iRadio Lab / Schulich School of Engineering University of Calgary, Calgary, AB, Canada email: [email protected]
Abstract This paper proposes an experimental study of the architectures of the high power amplification stage and their influences on the system’s linearity and power efficiency with application to wireless communication infrastructures. Two architectures are investigated: the single branch power amplification stage using class A/B power amplifiers and the promising multi-branch architecture using dynamic load modulation techniques such as the Doherty amplifier. Two LDMOS based high power amplifiers line-ups operating around 2.14 GHz were designed. In order to improve their efficiency vs. linearity trade-off, a predistortion based linearization technique has been applied to the both studied amplification stages. Measurement results under multi-carriers W-CDMA signals confirm the promising potential of the multibranch approach. Indeed, the multi-branch architecture greatly improves the power efficiency of the amplification stage while maintaining good linearity performances. Keywords: Amplifier; class A; class B; class C; Doherty amplifier; efficiency; non linearity; predistortion; power; wireless communications.
1. Introduction The emerging wireless communication systems that has been recently deployed or that will be deployed in the near future use highly spectrum efficient access techniques such as Code Division Multiple Access (CDMA), Multi-Carrier CDMA (MC-CDMA), Orthogonal Frequency Division
1-4244-0038-4 2006 IEEE CCECE/CCGEI, Ottawa, May 2006
Multiplexing (OFDM), etc… These access techniques increase the network capacity and the diversity of the services offered. However, the achieved high data rate results in envelop varying signals that has high Peak to Average Power Ratio (PAPR). This PAPR issue is greatly influencing the design of the RF power amplification stages in wireless transmitters. Indeed, the power amplifier (PA) has to operate linearly at the average power level while handling high peak power levels without degrading the signal’s quality by distorting the signals’ peaks. Hence, in order to achieve linear amplification, linear PAs operated deeply in their back-off region are required. This inevitably leads to very low power efficiency performances. Thus, to further improve the achievable power efficiency while meeting the linearity requirements, continuously driven weakly non linear PAs are used along with a linearization technique such as feedback, feedforward and predistortion [1]-[3]. Among these major linearization techniques that were reported in the literature, digital predistortion has been widely adopted especially for base station implementations due to its good trade-off between implementation complexity and linearity improvement performances. Recently more power efficient operation classes such as class F have been considered [4]-[5]. In addition to such amplification stages architectures based on single branch amplifiers, other architectures based on highly non linear dynamically load-modulated multi-branch power amplifiers have been extensively investigated over the past years. In such architectures that mainly include the Doherty
1469
amplifiers [6]-[8] and the LInear amplification using Non linear Components (LINC) [9]-[11] techniques, the power amplifiers use transistors biased in class B, C and even switching mode classes such as D, and E and their subclasses for a higher power efficiency. In this paper, a comparative study of single branch versus multi-branch RF power amplification stages architectures is proposed. In the first section, an overview of the single branch architecture is presented. The Doherty based multi-branch architectures is described in section two along with its critical practical implementation issues. Finally, the comparative experimental study of the linearity and power efficiency performances of a class A/B biased single branch amplifier and a dual branch Doherty amplifier is presented.
2. Single Branch Power Amplifiers Architectures The single branch power amplifiers architectures can be classified in two categories. In the first one, the power amplifiers are operated at a fixed bias point. The performances of these power amplifiers are improved mainly by linearization using the digital predistortion technique. The second category will consist of dynamically biased power amplifiers topologies using envelope tracking [12]-[13] and Envelope Elimination and Restoration (EER) techniques [14]-[15]. However, the use in emerging wireless communication infrastructure of PA configurations that belong to this latter category is very limited. For example, the EER technique has limited dynamic range, is sensitive to delay mismatch, and its bandwidth is limited by the DC/DC converter speed and power handling requirements. Accordingly, we will focus in the remaining of this paper on power amplifiers operated at a fixed bias point. This mainly evolves class A, A/B, B and F amplifiers. For class A operation, the transistor is biased so that the voltage and the current at the drain (VDS and IDS) in the case of Field Effect Transistors (FET) have the maximum sweep ranges possible. Thus, the transistor’s conduction angle (θ) equals 2π since it will conduct over the whole cycle. The resulting class A amplifier is highly linear but has, theoretically, a maximum power efficiency of 50% at the peak output power. When the transistor is biased at lower IDS compared to the bias level corresponding to class A mode of operation, while keeping the gate voltage above the conduction threshold, the conduction angle will decrease ( π < θ < 2π ). In such conditions, the output power as well as the power efficiency will increase while the linearity decreases. When the gate bias of the FET is set at the conduction threshold, the amplifier will operate in class B and conduct during half the cycle ( θ = π ). The maximum achievable efficiency reaches 78.5%. The frequency components of the drain current versus the conduction angle are given by:
⎧ ⎪ 2 ⋅ sin θ − θ ⋅ cos θ 2 2 ⎪ I = I max ⋅ ⎪ C0 θ 2π 1 − cos 2 ⎪ ⎪ I max θ − sin (θ ) ⎪ ⋅ ⎨ I C1 = 2π 1 − cos θ ⎪ 2 ⎪ ⎪ ⎛ sin ( n − 1) ⋅ θ sin ( n + 1) ⋅ θ ⎞ I max 2 2 ⎟ ⎪I = ⎜ ⋅⎜ − ⎪ Cn ⎟ n ⋅ ( n − 1) n ⋅ ( n + 1) ⎟ π ⋅ 1 − cos θ 2 ⎜ ⎪⎩ ⎝ ⎠ Eq. 1
( )
( )
( )
( ))
(
( )
(
)
(
)
Where I C 0 and I C1 are the DC and fundamental components of the drain current. I Cn ( n ≥ 2 ) represents the harmonics components of the drain current. The corresponding curves for the DC and the fundamental components as well as the first five harmonics are plotted on figure 1. For clarity reasons, the current components are plotted versus the normalized complementary conduction angle (β) that is given by Eq. 2. Accordingly, one can observe that the maximum output power that is proportional to the fundamental frequency component of the drain current is the same for class A and class B biasing conditions. For class A/B operation, the output power increases and reaches a maximum value for θ 1.3 π . The DC current decreases whereas the non linear harmonic components increase as the conduction angle is reduced. 2π − α β= Eq. 2
π
0.6
1
0.5
0.9
I (DC) I (F ) 0
I (2F ) 0
I (3F )
0.4
0.8
0
I (4F ) 0
0.3
0.7
I (5F ) 0
Efficiency
0.2
0.6
0.1
0.5
0
0.4
-0.1
0.3 0
0.5
1
1.5
2
Angle β
Figure 1. Frequency components of the drain current and drain efficiency vs. the normalized complementary conduction angle. The maximum theoretically achievable drain efficiency is plotted on figure 1. This highlights the efficiency improvement achieved by biasing the transistor at a reduced conduction angle. To further improve this power efficiency, harmonically loaded overdriven amplifiers, also called class F amplifiers, can be used. The harmonic loading will increase the output power and thus the efficiency but at the expense of linearity performances.
1470
3. Multi-Branch Power Amplifiers Architectures
4. Comparative Experimental Results
The previously mentioned single branch power amplifiers have limited power efficiency when operated in compliance with the linearity requirements of emerging wireless communication systems. This power efficiency limitation can be overcame by using multi-branch power amplifiers architectures such as the Doherty amplifiers. The Doherty amplifier architecture is a two branch architecture that has been recently extended to a more generalized multi-branch architecture [8]. The block diagram of this amplification architecture is shown on figure 2. For low input power levels, the carrier amplifier, that is biased in class A/B to achieve a better linearity and efficiency trade-off, operates into a 2 R0 load and thus has a high power efficiency. As the input drive level increases, the peaking amplifier, biased in class C for efficiency purposes, is turned on and modulates the load seen by the carrier amplifier. Linearized Doherty amplifiers are perceived as a dazzling way to achieve high power efficiency at back-off levels with satisfactory linearity performances. This is accomplished through an active loadpulling effect seen by the carrier amplifier as an extension of its saturation point. Therefore, the efficiency of the Doherty amplifier is effectively increased in back-off zone without compromising its maximum output power. In such Doherty amplifiers, both the slow turn-on behavior of the peaking amplifier and the complex gain imbalance between the two branches greatly affect the efficiency of the system in back-off operation mode.
In this section, the measured efficiency and linearity performances of a single branch power amplification stage will be compared to those of a two-branch Doherty amplifier. Both PA line-ups were designed for 3G wireless systems operating around 2140MHz. These line-ups, shown on figure 3, consist of three stage amplifiers for which the drivers stages are the same. The devices under test (DUT) are based respectively on MRF21085 transistor for the single branch architecture and MRF6P21190 for the multi-branch architecture. Both DUT are manufactured using the same LDMOS technology. The resulting amplifiers have a small signal gain of 51dB for the single branch PA and 47 dB for the multi branch PA. First, the two power amplification stages were characterized using the input and output time domain waveforms. Figure 4 presents the resulting AM/AM characteristics that were measured under a 2-carriers W-CDMA signal having a chip rate of 3.84Mcps and a peak to average power ratio of 10.4dB. These curves were used to synthesize the look-up tables based digital predistorter corresponding to each amplifier.
RFin
MHPA 21010
RFout
MRF 21045
Drivers
DUT
Figure 3. Power amplifiers Line up. 54
Carrier PA
Input
Z0
Peaking PA
2
; λ
Gain (dB)
Z0 ; λ/4
Z0 ; λ/4
52
4
Single Branch
50
48
Multi-Branch
Load Z0 46
Figure 2. Typical Doherty amplifier configuration. As a conclusion, Doherty amplifiers are perceived as a promising technology for multi-branch amplification systems whereas other multi-branch architectures are still facing implementations problems and need to be adapted to the context of new wireless communication systems having high PAPR signals.
44 -25
-20
-15
-10
-5
0
5
10
Input Power (dBm)
Figure 4. Measured Gain for both PA line-ups. The measured spectra at the output of the two PA architectures before and after linearization are used to calculate the Adjacent Channel Power Ratio (ACPR). The ACPR for
1471
TABLE I MEASURED ACPR AT THE OUTPUT OF THE PAS
5 MHz
Two-Branch Architecture ACPR (dBc)
Single Branch Architecture ACPR (dBc)
Frequency Offset
Before After Lin. Lin.
Before Lin.
After Lin.
L
-41.38 -62.18 -29.46 -54.35
H
-41.87 -62.19 -29.42 -54.53
L
-49.54 -63.30 -36.56 -58.40
H
-49.59 -63.26 -36.88 -58.76
L
-57.48 -63.45 -45.52 -60.70
H
-57.42 -63.41 -45.58 -60.63
10 MHz
15 MHz
References
both architectures before and after linearization are presented in table 1. Accordingly, one can conclude that even though the multi-branch architecture is inherently more non linear, the linearity level achieved after digital predistortion is sufficient in both cases to meet the emission requirements of the spectrum mask. However, the power efficiency of the two considered architectures is quite different. Indeed, the drain efficiency of the single branch amplifier is about 13.5% under the previously mentioned test conditions whereas the efficiency of the two branch power amplifier reaches 32% for the same test conditions.
5. Conclusions This paper studied the power amplification stages architectures suitable for base stations implementation in emerging wireless communication systems. Mainly, the single branch architecture is compared to the multi-branch architecture. Moreover, an experimental investigation of the linearity and power efficiency performances of digitally linearized single branch class A/B amplifier and two-branch Doherty amplifier was carried. Measurement results show that while both amplifiers meet the linearity requirement, the use of dual branch Doherty amplifier increases the power efficiency by more than 100%.
Acknowledgement This work was supported by Alberta’s Informatics Circle of Research Excellence (iCORE), Natural Sciences and Engineering Research Council of Canada (NSERC), Communications Research Centre Canada (CRC), and TRLabs. The authors want to acknowledge Agilent Technologies for software donation.
[1] P. B. Kenington, HIGH-LINEARITY RF AMPLIFIER DESIGN . Boston, MA: Artech House, 2000. [2] A. Katz, “Linearization: Reducing distortion in power amplifiers,” IEEE Micro., vol. 2, pp. 37-49, Dec., 2001. [3] F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic, N. Pothecary, J. F. Sevic, and N. O. Sokal, “Power amplifiers and transmitters for RF and microwave,” IEEE Trans. Microwave Theory Tech., vol. 50, pp. 814-826, March, 2002. [4] N. Le Gallou, J.Y. Touchais, J.F. Villemazet, A. Darbandi, J.L. Cazaux, A. Mallet, and L. Lapierre, “High efficiency 45 W HPA for space application,” Digests 34th European Microwave Conference, pp. 181-184, 2004. [5] F. Lepine, A. Adahl, and H. Zirath, “A high efficient LDMOS power amplifier based on an inverse class F architecture,” Digests 34th European Microwave Conference, pp. 1181-1184, 2004. [6] W.H. Doherty, “A new high efficiency power amplifier for modulated waves,” Proc. IRE, vol. 24, pp. 1163-1182, September, 1936. [7] J. Sirois, S. Boumaiza, M. Helaoui, G. Brassard, and F. M. Ghannouchi, “A robust modeling and design approach for dynamically loaded and digitally linearized doherty amplifiers,” IEEE Trans. Microwave Theory Tech., vol. 53, pp. 2875-2883, September, 2005. [8] Y. Yang, J. Cha, B. Shin, and B. Kim, “A fully matched Nway Doherty amplifier with optimized linearity,” IEEE Trans. Microwave Theory Tech., vol. 51, pp. 986-993, March, 2003. [9] D.C. Cox, “Linear amplification with nonlinear components,” IEEE Trans. Commun., vol. COM-22, pp. 1942-1945, December, 1974. [10] H. Chireix, “High power outphasing modulation,” Proc. IRE, vol. 23, pp. 1370-1392, November, 1935. [11] A. Birafane, and A.B. Kouki, “On the linearity and efficiency of outphasing microwave amplifiers,” IEEE Trans. Microwave Theory Tech., vol. 52, pp. 1702-1708, July, 2004. [12] G. Hanington, P. Chen, P. M. Asbeck, and L. E. Larson, “High efficiency power amplifier using dynamic powersupply voltage for CDMA applications,” IEEE Trans. Microwave Theory Tech., vol. 47, pp. 1471-1476, August, 1999. [13] J. Staudinger, B. Gilsdorf, D. Newman, G. Norris, G. Sadowniczak, R. Sherman, and T. Quach, “High efficiency CDMA power amplifier using dynamic envelope tracking technique,” Digests IEEE MTT-S International Microwave Symposium, pp. 873-876, 2000. [14] L. Kahn, “Single-sided transmission by envelope elimination and restoration,” Proc. IRE, vol. 40, pp. 803806, July, 1952. [15] R. H. Raab, B. E. Sigmon, R. G. Myers, and R. M. Jackson, “L-band transmitter using Kahn EER technique,” IEEE Trans. Microwave Theory Tech., vol. 46, pp. 22202225, December, 1998.
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Slim Boumaiza iRadio Lab / Schulich School of Engineering University of Calgary, Calgary, AB, Canada email: [email protected]
Jangheon Kim MMIC Lab / Dept. of Electrical Engineering POSTECH, Republic of Korea email: [email protected]
Sungchul Hong MMIC Lab / Dept. of Electrical Engineering POSTECH, Republic of Korea email: [email protected]
Ildu Kim MMIC Lab / Dept. of Electrical Engineering POSTECH, Republic of Korea email: [email protected]
Bumman Kim MMIC Lab / Dept. of Electrical Engineering POSTECH, Republic of Korea email: [email protected]
Fadhel Ghannouchi iRadio Lab / Schulich School of Engineering University of Calgary, Calgary, AB, Canada email: [email protected]
Abstract This paper proposes an experimental study of the architectures of the high power amplification stage and their influences on the system’s linearity and power efficiency with application to wireless communication infrastructures. Two architectures are investigated: the single branch power amplification stage using class A/B power amplifiers and the promising multi-branch architecture using dynamic load modulation techniques such as the Doherty amplifier. Two LDMOS based high power amplifiers line-ups operating around 2.14 GHz were designed. In order to improve their efficiency vs. linearity trade-off, a predistortion based linearization technique has been applied to the both studied amplification stages. Measurement results under multi-carriers W-CDMA signals confirm the promising potential of the multibranch approach. Indeed, the multi-branch architecture greatly improves the power efficiency of the amplification stage while maintaining good linearity performances. Keywords: Amplifier; class A; class B; class C; Doherty amplifier; efficiency; non linearity; predistortion; power; wireless communications.
1. Introduction The emerging wireless communication systems that has been recently deployed or that will be deployed in the near future use highly spectrum efficient access techniques such as Code Division Multiple Access (CDMA), Multi-Carrier CDMA (MC-CDMA), Orthogonal Frequency Division
1-4244-0038-4 2006 IEEE CCECE/CCGEI, Ottawa, May 2006
Multiplexing (OFDM), etc… These access techniques increase the network capacity and the diversity of the services offered. However, the achieved high data rate results in envelop varying signals that has high Peak to Average Power Ratio (PAPR). This PAPR issue is greatly influencing the design of the RF power amplification stages in wireless transmitters. Indeed, the power amplifier (PA) has to operate linearly at the average power level while handling high peak power levels without degrading the signal’s quality by distorting the signals’ peaks. Hence, in order to achieve linear amplification, linear PAs operated deeply in their back-off region are required. This inevitably leads to very low power efficiency performances. Thus, to further improve the achievable power efficiency while meeting the linearity requirements, continuously driven weakly non linear PAs are used along with a linearization technique such as feedback, feedforward and predistortion [1]-[3]. Among these major linearization techniques that were reported in the literature, digital predistortion has been widely adopted especially for base station implementations due to its good trade-off between implementation complexity and linearity improvement performances. Recently more power efficient operation classes such as class F have been considered [4]-[5]. In addition to such amplification stages architectures based on single branch amplifiers, other architectures based on highly non linear dynamically load-modulated multi-branch power amplifiers have been extensively investigated over the past years. In such architectures that mainly include the Doherty
1469
amplifiers [6]-[8] and the LInear amplification using Non linear Components (LINC) [9]-[11] techniques, the power amplifiers use transistors biased in class B, C and even switching mode classes such as D, and E and their subclasses for a higher power efficiency. In this paper, a comparative study of single branch versus multi-branch RF power amplification stages architectures is proposed. In the first section, an overview of the single branch architecture is presented. The Doherty based multi-branch architectures is described in section two along with its critical practical implementation issues. Finally, the comparative experimental study of the linearity and power efficiency performances of a class A/B biased single branch amplifier and a dual branch Doherty amplifier is presented.
2. Single Branch Power Amplifiers Architectures The single branch power amplifiers architectures can be classified in two categories. In the first one, the power amplifiers are operated at a fixed bias point. The performances of these power amplifiers are improved mainly by linearization using the digital predistortion technique. The second category will consist of dynamically biased power amplifiers topologies using envelope tracking [12]-[13] and Envelope Elimination and Restoration (EER) techniques [14]-[15]. However, the use in emerging wireless communication infrastructure of PA configurations that belong to this latter category is very limited. For example, the EER technique has limited dynamic range, is sensitive to delay mismatch, and its bandwidth is limited by the DC/DC converter speed and power handling requirements. Accordingly, we will focus in the remaining of this paper on power amplifiers operated at a fixed bias point. This mainly evolves class A, A/B, B and F amplifiers. For class A operation, the transistor is biased so that the voltage and the current at the drain (VDS and IDS) in the case of Field Effect Transistors (FET) have the maximum sweep ranges possible. Thus, the transistor’s conduction angle (θ) equals 2π since it will conduct over the whole cycle. The resulting class A amplifier is highly linear but has, theoretically, a maximum power efficiency of 50% at the peak output power. When the transistor is biased at lower IDS compared to the bias level corresponding to class A mode of operation, while keeping the gate voltage above the conduction threshold, the conduction angle will decrease ( π < θ < 2π ). In such conditions, the output power as well as the power efficiency will increase while the linearity decreases. When the gate bias of the FET is set at the conduction threshold, the amplifier will operate in class B and conduct during half the cycle ( θ = π ). The maximum achievable efficiency reaches 78.5%. The frequency components of the drain current versus the conduction angle are given by:
⎧ ⎪ 2 ⋅ sin θ − θ ⋅ cos θ 2 2 ⎪ I = I max ⋅ ⎪ C0 θ 2π 1 − cos 2 ⎪ ⎪ I max θ − sin (θ ) ⎪ ⋅ ⎨ I C1 = 2π 1 − cos θ ⎪ 2 ⎪ ⎪ ⎛ sin ( n − 1) ⋅ θ sin ( n + 1) ⋅ θ ⎞ I max 2 2 ⎟ ⎪I = ⎜ ⋅⎜ − ⎪ Cn ⎟ n ⋅ ( n − 1) n ⋅ ( n + 1) ⎟ π ⋅ 1 − cos θ 2 ⎜ ⎪⎩ ⎝ ⎠ Eq. 1
( )
( )
( )
( ))
(
( )
(
)
(
)
Where I C 0 and I C1 are the DC and fundamental components of the drain current. I Cn ( n ≥ 2 ) represents the harmonics components of the drain current. The corresponding curves for the DC and the fundamental components as well as the first five harmonics are plotted on figure 1. For clarity reasons, the current components are plotted versus the normalized complementary conduction angle (β) that is given by Eq. 2. Accordingly, one can observe that the maximum output power that is proportional to the fundamental frequency component of the drain current is the same for class A and class B biasing conditions. For class A/B operation, the output power increases and reaches a maximum value for θ 1.3 π . The DC current decreases whereas the non linear harmonic components increase as the conduction angle is reduced. 2π − α β= Eq. 2
π
0.6
1
0.5
0.9
I (DC) I (F ) 0
I (2F ) 0
I (3F )
0.4
0.8
0
I (4F ) 0
0.3
0.7
I (5F ) 0
Efficiency
0.2
0.6
0.1
0.5
0
0.4
-0.1
0.3 0
0.5
1
1.5
2
Angle β
Figure 1. Frequency components of the drain current and drain efficiency vs. the normalized complementary conduction angle. The maximum theoretically achievable drain efficiency is plotted on figure 1. This highlights the efficiency improvement achieved by biasing the transistor at a reduced conduction angle. To further improve this power efficiency, harmonically loaded overdriven amplifiers, also called class F amplifiers, can be used. The harmonic loading will increase the output power and thus the efficiency but at the expense of linearity performances.
1470
3. Multi-Branch Power Amplifiers Architectures
4. Comparative Experimental Results
The previously mentioned single branch power amplifiers have limited power efficiency when operated in compliance with the linearity requirements of emerging wireless communication systems. This power efficiency limitation can be overcame by using multi-branch power amplifiers architectures such as the Doherty amplifiers. The Doherty amplifier architecture is a two branch architecture that has been recently extended to a more generalized multi-branch architecture [8]. The block diagram of this amplification architecture is shown on figure 2. For low input power levels, the carrier amplifier, that is biased in class A/B to achieve a better linearity and efficiency trade-off, operates into a 2 R0 load and thus has a high power efficiency. As the input drive level increases, the peaking amplifier, biased in class C for efficiency purposes, is turned on and modulates the load seen by the carrier amplifier. Linearized Doherty amplifiers are perceived as a dazzling way to achieve high power efficiency at back-off levels with satisfactory linearity performances. This is accomplished through an active loadpulling effect seen by the carrier amplifier as an extension of its saturation point. Therefore, the efficiency of the Doherty amplifier is effectively increased in back-off zone without compromising its maximum output power. In such Doherty amplifiers, both the slow turn-on behavior of the peaking amplifier and the complex gain imbalance between the two branches greatly affect the efficiency of the system in back-off operation mode.
In this section, the measured efficiency and linearity performances of a single branch power amplification stage will be compared to those of a two-branch Doherty amplifier. Both PA line-ups were designed for 3G wireless systems operating around 2140MHz. These line-ups, shown on figure 3, consist of three stage amplifiers for which the drivers stages are the same. The devices under test (DUT) are based respectively on MRF21085 transistor for the single branch architecture and MRF6P21190 for the multi-branch architecture. Both DUT are manufactured using the same LDMOS technology. The resulting amplifiers have a small signal gain of 51dB for the single branch PA and 47 dB for the multi branch PA. First, the two power amplification stages were characterized using the input and output time domain waveforms. Figure 4 presents the resulting AM/AM characteristics that were measured under a 2-carriers W-CDMA signal having a chip rate of 3.84Mcps and a peak to average power ratio of 10.4dB. These curves were used to synthesize the look-up tables based digital predistorter corresponding to each amplifier.
RFin
MHPA 21010
RFout
MRF 21045
Drivers
DUT
Figure 3. Power amplifiers Line up. 54
Carrier PA
Input
Z0
Peaking PA
2
; λ
Gain (dB)
Z0 ; λ/4
Z0 ; λ/4
52
4
Single Branch
50
48
Multi-Branch
Load Z0 46
Figure 2. Typical Doherty amplifier configuration. As a conclusion, Doherty amplifiers are perceived as a promising technology for multi-branch amplification systems whereas other multi-branch architectures are still facing implementations problems and need to be adapted to the context of new wireless communication systems having high PAPR signals.
44 -25
-20
-15
-10
-5
0
5
10
Input Power (dBm)
Figure 4. Measured Gain for both PA line-ups. The measured spectra at the output of the two PA architectures before and after linearization are used to calculate the Adjacent Channel Power Ratio (ACPR). The ACPR for
1471
TABLE I MEASURED ACPR AT THE OUTPUT OF THE PAS
5 MHz
Two-Branch Architecture ACPR (dBc)
Single Branch Architecture ACPR (dBc)
Frequency Offset
Before After Lin. Lin.
Before Lin.
After Lin.
L
-41.38 -62.18 -29.46 -54.35
H
-41.87 -62.19 -29.42 -54.53
L
-49.54 -63.30 -36.56 -58.40
H
-49.59 -63.26 -36.88 -58.76
L
-57.48 -63.45 -45.52 -60.70
H
-57.42 -63.41 -45.58 -60.63
10 MHz
15 MHz
References
both architectures before and after linearization are presented in table 1. Accordingly, one can conclude that even though the multi-branch architecture is inherently more non linear, the linearity level achieved after digital predistortion is sufficient in both cases to meet the emission requirements of the spectrum mask. However, the power efficiency of the two considered architectures is quite different. Indeed, the drain efficiency of the single branch amplifier is about 13.5% under the previously mentioned test conditions whereas the efficiency of the two branch power amplifier reaches 32% for the same test conditions.
5. Conclusions This paper studied the power amplification stages architectures suitable for base stations implementation in emerging wireless communication systems. Mainly, the single branch architecture is compared to the multi-branch architecture. Moreover, an experimental investigation of the linearity and power efficiency performances of digitally linearized single branch class A/B amplifier and two-branch Doherty amplifier was carried. Measurement results show that while both amplifiers meet the linearity requirement, the use of dual branch Doherty amplifier increases the power efficiency by more than 100%.
Acknowledgement This work was supported by Alberta’s Informatics Circle of Research Excellence (iCORE), Natural Sciences and Engineering Research Council of Canada (NSERC), Communications Research Centre Canada (CRC), and TRLabs. The authors want to acknowledge Agilent Technologies for software donation.
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