Supporting Information
Self-Aligned Multi-Channel Graphene Nanoribbon Transistor Arrays Fabricated at Wafer Scale Seong-Jun Jeong1†*, Sanghyun Jo1†, Jooho Lee2, Kiyeon Yang2, Hyangsook Lee2, Chang-Seok Lee1, Heesoon Park1, Seongjun Park1*
1
Device Laboratory, Device & System Research Center, Samsung Advanced Institute of
Technology, Suwon 16678, Republic of Korea 2
Platform Technology Laboratory, Device & System Research Center, Samsung Advanced
Institute of Technology, Suwon 16678, Republic of Korea
KEYWORDS: graphene nanoribbon, nanolithography, directed self-assembly, block copolymer, multi-channel transistor
Experimental Section Synthesis and Transfer of Graphene: Monolayered graphene was synthesized on a Cu film deposited by evaporation on a 6” Si wafer by the MOCVD process in the presence of a reaction gas mixture of hydrogen and methane. A poly(methyl methacrylate) (PMMA) layer was spin coated on the sample and then soft baked to improve the adhesion between the PMMA and the graphene. The Cu film was then removed from the Si wafer using a Cu etchant. Finally, the separated graphene layer was transferred onto a 6” Si wafer covered with a 100 nm thermally grown SiO2 film. Topographic Au Pre-pattern Preparation: To fabricate the back-gated FET devices at the wafer scale, 10 nm Ti/100 nm Au metal pads on graphene/SiO2/6” Si++ wafers were patterned using photolithography and a lift-off method after deposition using e-beam evaporation. Next, 20 nm Au source/drain electrodes were deposited and patterned in a manner similar to the Au metal pad process using projection lithography (including KrF and e-beam lithography). Directed Assembly of PS-b-PDMS Thin Films: A thin BCP film was spin-coated over the topographic Au pre-pattern. BCP with molecular weights of 11 kg/mol and 5 kg/mol (fPS ≈ 0.69) for PS and PDMS blocks, respectively, was spin coated from a cyclohexane solution onto patterned substrates. Thermal annealing was conducted at 280 °C for 3 min to achieve the directed assembly, after which the PDMS top layer was removed by RIE with CF4. Then the PS component was selectively removed from the assembled BCP thin film by RIE with O2 . Morphology and FET Characterization: The nanoscale morphology of the BCP thin film was analyzed using a Hitachi S-4800 SEM or 4700 SEM. The CD of the directed PDMS cylinder was characterized using Hitachi CD measurement software (Terminal PC Offline CD Measurement Software Ver.7.34). The electrical characteristics of the fabricated GNR FETs were measured using a Keithley 4200-SCS semiconductor parameter analyzer and a N2
chamber probe station. TEM Characterization: TEM samples were placed in a hot TMAH solvent bath for around 10 min and finally rinsed with isopropanol (IPA) to remove the remaining PDMS cylinders. The samples were then prepared by spin coating a 100 nm layer of PMMA polymer resist onto the densely packed GNR array/SiO2/Si substrate, which was then baked at 80 °C. The PMMA/GNRs were then lifted off in an HF solution and transferred onto a lacy film coated copper grid. After removal of the PMMA with acetone vapor, the sample was characterized using a Titan cubed TEM operating at 80 kV. Raman Characterization: The Raman spectra were obtained using a micro-Raman (Renishaw InVia) spectrometer in a dark room. The 514 nm wavelength of an Ar-ion laser was used as the excitation source. The incident power was limited to ≤ 2 mW, in order to avoid heating effects. The typical spatial resolution was lower than 1 cm-1. Finally, peak analyses were performed using the software WiRE 3.3.
Figure S1. Quality and uniformity of the transferred graphene on a 6″ SiO2/Si wafer. a. 2D map of I(D)/I(G) where the standard deviation was only 0.049 over the 6ʺ wafer. b. Raman spectra of transferred graphene randomly measured on a 6ʺ wafer. The main graphene features include the D (~1344 cm-1), G (~1587 cm-1), and 2D (~2679 cm-1) peaks. Both the shape of the 2D peak and its higher intensity (I2D) than the G peak (IG) with a low intensity D peak (I(D)/I(G)) confirm that the synthesized graphene was a monolayer and of high quality50.
Figure S2. Orientation uniformity of the densely stacked DSA nanopatterns on a 6ʺ SiO2/Si wafer. a. OM and SEM images of the individual/integrated multi-channel GNR FETs. b. High magnification SEM images and 2D orientation maps. Nine DSA patterns were randomly extracted at each numbered location shown in image (a). The uniform false color orientation maps illustrate a high degree of alignment c. The integral of the orientation distribution intensity yielded an orientation parameter S(3σ) of ~0.92. The orientation
parameter for a 2D map was carefully calculated, as demonstrated in ACS Nano 2016, 10, 3435−3442. d, e. High magnification SEM images and 2D orientation maps of the randomly oriented and parallel-ordered DSA nanopatterns
Figure S3. Top-view HRTEM image of densely packed GNR arrays. The diameter of the PDMS cylinders was ~ 8 nm, which is consistent with the results obtained from the SEM analysis (Figure 2c). Note that a PMMA supporting layer was used to prevent the spreading of GNRs in the HF solution.