Semiconductor device replica circuit for monitoring critical path and ...
US006414527B1
(12) United States Patent
(10) Patent N0.:
Seno et al.
(54)
US 6,414,527 B1
(45) Date of Patent:
SEMICONDUCTOR DEVICE REPLICA CIRCUIT FOR MONITORING CRITICAL PATH ANT) CONSTRUCTION METHOD OF
5,537,069 A 5,585,754 A 5,900,752 A
THE SAME
5,939,913 A * 6,005,421 A
(75) Inventors: Katsunori Seno; Takahiro Seki, both of KanagaWa; Tetsuo Kondo, Tokyo, all of (JP)
Jul. 2, 2002
* 7/1996 Volk ......................... .. 327/149 * 12/1996 Yamashina et a1. ....... .. 327/158 * 5/1999 Mar ......................... .. 327/143
8/1999 Tomita
* 12/1999
327/158
Saeki ....................... .. 327/119
* cited by examiner
Primary Examiner—Terry D. Cunningham
(73) Assignee: Sony Corporation (JP)
Assistant Examiner—Quan Tra
*
N' ot1ce:
Sbj u ect to an yd'l' Isc aImer, t h e term 0 fh' t is patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days.
(74) Attorney, Agent, or Firm—Rader, Fishman & Grauer PLLC; Ronald P. Kananen, Esq.
(57)
ABSTRACT
(21) Appl. No.: 09/484,240
A semiconductor device provided With a replica circuit
(22) Filed:
functioning as an equivalent circuit to that of a path con ?guration selected as a critical path in the semiconductor
(30)
Jan. 18, 2000
Foreign Application Priority Data
Jan. 20, 1999 Nov. 18, 1999
circuit and an adjustable delay device for example betWeen an output side of the replica circuit and a phase comparator,
(JP)
......................................... .. 11-012381
(JP)
......................................... .. 11-328832
(51)
Int. Cl.7 ................................................ .. H03L 7/06
(52) (58)
US. Cl. .............. .. 327/158; 327/270 Field of Search ............................... .. 327/102, 149,
327/156, 158, 161, 540 (56)
the delay value of the delay device being adjustable after production of the chip to a value enabling the replica system including the replica circuit to reliably operate With a margin from the critical path delay of the semiconductor circuit, Whereby it becomes possible to prevent setting of an exces
sive margin and becomes possible to increase the margin When the margin ends up smaller than expected and there
fore it becomes possible to ?exibly and ef?ciently con?gure
References Cited
the replica circuit, and a method of constitution of the same.
U.S. PATENT DOCUMENTS 4,922,141 A
*
42 Claims, 19 Drawing Sheets
5/1990 Lofgren et a1. ........... .. 327/158
UP
PHASE COMPARATO
REPLICA
CIRCUIT 1
12
I 12 A
13
CHARGE PUMP
D"
I
DC-DC CONVERTER
I
VDD
v L81
l 11
U.S. Patent
Jul. 2, 2002
US 6,414,527 B1
Sheet 1 0f 19
F|G.1 1
f
2
REPLICA CIRCUIT
F|G.2 (D : TRANSISTOR DELAY
DELAY
\Q) : RC DELAY VOLTAGE
U.S. Patent
Jul. 2, 2002
Sheet 3 0f 19
A
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US 6,414,527 B1
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U.S. Patent
Jul. 2, 2002
Sheet 4 0f 19
US 6,414,527 B1
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US 6,414,527 B1
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U.S. Patent
Jul. 2, 2002
Sheet 19 0f 19
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US 6,414,527 B1
(12) United States Patent
(10) Patent N0.:
Seno et al.
(54)
US 6,414,527 B1
(45) Date of Patent:
SEMICONDUCTOR DEVICE REPLICA CIRCUIT FOR MONITORING CRITICAL PATH ANT) CONSTRUCTION METHOD OF
5,537,069 A 5,585,754 A 5,900,752 A
THE SAME
5,939,913 A * 6,005,421 A
(75) Inventors: Katsunori Seno; Takahiro Seki, both of KanagaWa; Tetsuo Kondo, Tokyo, all of (JP)
Jul. 2, 2002
* 7/1996 Volk ......................... .. 327/149 * 12/1996 Yamashina et a1. ....... .. 327/158 * 5/1999 Mar ......................... .. 327/143
8/1999 Tomita
* 12/1999
327/158
Saeki ....................... .. 327/119
* cited by examiner
Primary Examiner—Terry D. Cunningham
(73) Assignee: Sony Corporation (JP)
Assistant Examiner—Quan Tra
*
N' ot1ce:
Sbj u ect to an yd'l' Isc aImer, t h e term 0 fh' t is patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days.
(74) Attorney, Agent, or Firm—Rader, Fishman & Grauer PLLC; Ronald P. Kananen, Esq.
(57)
ABSTRACT
(21) Appl. No.: 09/484,240
A semiconductor device provided With a replica circuit
(22) Filed:
functioning as an equivalent circuit to that of a path con ?guration selected as a critical path in the semiconductor
(30)
Jan. 18, 2000
Foreign Application Priority Data
Jan. 20, 1999 Nov. 18, 1999
circuit and an adjustable delay device for example betWeen an output side of the replica circuit and a phase comparator,
(JP)
......................................... .. 11-012381
(JP)
......................................... .. 11-328832
(51)
Int. Cl.7 ................................................ .. H03L 7/06
(52) (58)
US. Cl. .............. .. 327/158; 327/270 Field of Search ............................... .. 327/102, 149,
327/156, 158, 161, 540 (56)
the delay value of the delay device being adjustable after production of the chip to a value enabling the replica system including the replica circuit to reliably operate With a margin from the critical path delay of the semiconductor circuit, Whereby it becomes possible to prevent setting of an exces
sive margin and becomes possible to increase the margin When the margin ends up smaller than expected and there
fore it becomes possible to ?exibly and ef?ciently con?gure
References Cited
the replica circuit, and a method of constitution of the same.
U.S. PATENT DOCUMENTS 4,922,141 A
*
42 Claims, 19 Drawing Sheets
5/1990 Lofgren et a1. ........... .. 327/158
UP
PHASE COMPARATO
REPLICA
CIRCUIT 1
12
I 12 A
13
CHARGE PUMP
D"
I
DC-DC CONVERTER
I
VDD
v L81
l 11
U.S. Patent
Jul. 2, 2002
US 6,414,527 B1
Sheet 1 0f 19
F|G.1 1
f
2
REPLICA CIRCUIT
F|G.2 (D : TRANSISTOR DELAY
DELAY
\Q) : RC DELAY VOLTAGE
U.S. Patent
Jul. 2, 2002
Sheet 3 0f 19
A
j
T927;
TIN_:T.m|ulwP:
W A N W N mm: m:
US 6,414,527 B1
Tm:T27;
TN:mlwww:iNE W A “ A 3_ N N
TN:mElmw: ~m:m :
w “mt
“ &&
|Tm:|
A
U.S. Patent
Jul. 2, 2002
Sheet 4 0f 19
US 6,414,527 B1
mosdm Ebm5m6Cw
mmvE,
NP
C6Rz8EmQ:G
9mm5.ON2W W am 2 M “ >
W W W H52
www 23w2w
US 6,414,527 B1
5
U.S. Patent
Jul. 2, 2002
Sheet 19 0f 19
W8.83E:w5Eu5zwmu%a a
9mm8ON9W mm w W W A 2
5W8A“ \W 1% m5$%:2=“3>658zm.5: 258wm5
H
US 6,414,527 B1
