Si Tunneling Transistors with High on-Currents and Slopes of 50 mV ...
Si Tunneling Transistors with High On-Currents and Slopes of 50 mV/dec Using Segregation Doped NiSi2 Tunnel Junctions L. Knoll, Q.T. Zhao, S. Trellenkamp, A. Schäfer, K. K. Bourdelle* and S. Mantl Peter Grünberg Institut 9 (PGI-9/IT), JARA-FIT, Forschungszentrum Jülich, 52425 Jülich, Germany * SOITEC, Parc Technologique des Fontaines, 38190 Bernin, France. [email protected]
Abstract—Planar and nanowire (NW) tunneling field effect transistors (TFETs) have been fabricated on ultra thin strained and unstrained SOI with shallow doped Nickel disilicide (NiSi2) source and drain (S/D) contacts. We developed a novel, self-aligned process to form the p-i-n TFETs which greatly easies their fabrication by tilted dopant implantation using the high-k/metal gate as a shadow mask and dopant segregation. Two methods of dopant segregation are compared: Dopant segregation based on the “snowplough” effect of dopants during silicidation and implantation into the silicide (IIS) followed by thermal outdiffusion. High drive currents of up to 60 µA/µm of planar p-TFETs were achieved indicating good silicide/silicon tunneling junctions. The non linear temperature dependence of the inverse subthreshold slope S indicates typical TFET behavior. Strained Si NW array n-TFETs with omega shaped HfO2/TiN gates showed high drive currents of 7 µA/µm @ 1V Vdd and steep inverse subthreshold slopes with minimum values of 50mV/dec due to the smaller band gap of strained Si and optimized electrostatics. I.
INTRODUCTION
Band-to-band tunneling field effect transistors (TFET) are most promising for ultralow power applications. Due to the enhanced switching performance and low power consumption TFETs show distinct advantages as compared to standard CMOS [1]. However, silicon TFETs suffer from very low oncurrents, mainly due to the relatively large band gap of
~1.1 eV. A lower band-gap material like strained Si or SiGe enhances the band-to-band tunneling probability and thus the on-currents. Also the doping profile of the tunnel junction affects sensitively the tunneling probability. The advantage of silicon based materials is the availability of the highly advanced Si technology which helps to meet the critical requirements for high-k/metal gate stack and S/D junction formation. In this paper we make use of this by studying TFETs with silicon and strained Si, which offers a lower band gap than unstrained Si. Along this line we investigated two dopant segregation methods to form the silicide tunnel junctions with abrupt doping profiles at S/D at low temperatures. We investigated planar and nanowire array TFETs on ultrathin SOI and strained SOI. II.
Planar TFETs were fabricated on SOI substrates with top silicon thicknesses of 15 nm and 6 nm, respectively. A simple process without additional implantation masks was developed as sketched in Fig.1. Using the TiN/HfO2 gate stack as a shadow mask tilted B+ and As+ implantations at an angle of 45° and 135° allow the formation of aligned n+ and p+ regions self-aligned at the gate edges. For B an implantation energy of 1 keV and a dose of 2×1015/cm2 and for As 5 keV and a dose of 2×1015/cm2 were used. Silicidation was performed at 700°C to form epitaxial NiSi2 layers for S/D. Simultaneously dopant segregation (DS) occured and formed shallow highly doped pockets at the edge of the silicide, producing p+-pocket on the right side and n+-pocket on the right side of the gate. We assume that only the dopants of the “shadow” regions form the junctions, while the other dopants are incorporated in the metallic silicide and have no electrical effects. This process is labeled “DS” in Fig. 1. Alternatively, epitaxial NiSi2 was formed first, than implanted at tilt angles as stated above and RTP annealed at 700°C to drive-out and activate the implanted dopants and recover the crystal structure. This process is known as “Implantation Into Silicide” (IIS). The silicide is epitaxial NiSi2 formed with only 3 nm Ni [2]. All the processes were performed at fairly low temperatures with Tmax = 700°C. Planar and nanowire devices were fabricated. Fig. 2 shows a TEM image of the source part of a planar device on 15 nm SOI (left), and an SEM image of an -gated nanowire array device (right). These Si nanowires have a width of 30 nm and a thickness of ~6 nm made from ultrathin
This work was partially supported by the EU project STEEPER.
978-1-4673-1708-5/12/$31.00 ©2012 IEEE
FABRICATION
153
SOI with electron beam lithography and dry etching. The HfO2 with a thickness of 3 nm was deposited conformally by atomic layer deposition and TiN by vapor deposition.
Abrupt dopant profiles are needed for this purpose. A great advantage of DS is that very steep dopant profiles can be achieved at low T process [3,4]. In a p-type TFET minority carriers, holes, tunnel into the channel and electrons from the channel into the reservoir. Only at appropriate gate and drain bias a narrow energy window opens to enable BTBT as in Fig. 3.
Fig. 1: TFET fabrication process using tilted B+ and As+ ion implants into Si (DS process) or into epitaxial NiSi2 (IIS process) as S/D contacts. Highly doped pockets at the silicide edges are formed by dopant segregation.
Fig. 3: Schematic band diagram of a TFET with dopant segregation at the NiSi2 Schottky source/drain contacts under reverse bias. Band to band tunneling is indicated beween the n+ Source region and the intrinsic
Fig. 2: Cross sectional TEM image of a planar device with epitaxial NiSi2 source after IIS perfectly aligned with the HfO2/TiN gate (left) and an SEM image of a NW-array TFET with a 200 nm HfO2/TiN gate (right)
III.
RESULTS AND DISCUSSION
A TFET consists of a gated p-i-n diode which allows under appropriate reverse bias conditions band to band tunneling. A schematic band structure of a TFET with silicide Schottky contacts and highly doped pockets under reverse bias is shown in Fig. 3. Dopant segregation produces highly doped regions close to the NiSi2 contacts leading to strong band bending. As a consequence, the effective Schottky barrier is lowered to very small values (< 0.2 eV). With other words, the ultrathin barrier becomes transparent via carrier tunneling. By applying this method we have fabricated Schottky-Barrier MOSFETs with output currents exceeding 1mA/µm and remarkable RF performance [3]. Here, we make use of this method for TFETs. As compared to a standard TFET, a Schottky barrier controls the carrier injection from the silicide into the (electron) reservoir formed behind the Schottky barrier. Band to band tunneling is expected between the source reservoir and the channel when an energy window between the source Fermi energy and the valence band edge of the channels opens at appropriate gate and drain bias. For efficient BTBT the tunneling junction should be aligned with the fringing field of the gate edge to obtain a large electric field and the conduction and valence bands should come sufficently close to minimize the tunneling path (see arrow in Fig 3).
Fig.4 shows the output characteristics measured at 300 K of a planar p-TFET, which was fabricated with the DS process. The 400nm gate length device shows perfect saturation. The corresponding transfer characteristics are presented in Fig.5. It has to be mentioned that the noise in the off-state stems from the measurement setup and not from gate leakage. The subthreshold regime shows two different slopes labeled as regions I and II with inverse subthreshold slopes (SS) of 94 mV/dec and 190 mV/dec, respectively. Region II indicates a voltage dependent slope, typical for TFETs. Fig. 6 shows the Id-Vg characteristics measured from 100 K to 350 K at Vd = -0.1 V. Region I extends from about 200 K 350 K. We assume that trap assisted tunneling (TAT) occurs in this region as reported in [5] and [6], while in region II BTBT may dominate. This is further substantiated, by the results of Fig. 7, showing SS(T) of region II. For T > 200 K, SS(T) decreases rapidly, when, as we assume, TAT and BTBT occur simultaneously. At T < 200 K, SS(T) changes less rapidly and becomes even constant at T < 100 K which indicates BTBT. For comparison, the linear SS(T) dependence of a conventional MOSFET fabricated with the same process is presented. We conclude that remaining end of range defects, steming from the ion implantation before the silicidation, cause TAT in the tunneling junction which degrades the TFET performance drastically. Therefore, we investigated also IIS for tunnel junction formation. The IIS process has the advantage that the dopant implantation occurs into the metallic silicide and not into the Si channel material and the dopants are driven out by thermal annealing. Residual defects in the metallic contacts will have no effect on the tunnel junction behavior. In addition, we further improved the electrostatic gate control by reducing the silicon thickness to 6nm and the formation of nanowire array transistors. These measures improve significantly the natural
154
length , a measure for good gate control [7]. The IIS process is also advantageous for doping of nanowires which is anyway a complex issue due to dopant deactivation [8].
devices of Fig. 4 the improvement may come partly from a higher dopant concentration in the junction since we used the same implant parameters as for the somewhat thicker films
Fig. 4: Output characteristics of a 400 nm planar p-TFET at 300 K
Fig. 6: Id-Vgs characteristics of a planar p-TFET measured between 350 K and 100 K
Fig. 5: Transfer characteristics of a p-TFET at 300 K
The TFET performance was further improved by using nanowire structures fabricated with 6nm SOI substrates. Fig.8 shows the transfer characteristics of a nanowire array p-TFET with a 200 nm HfO2/TiN gate at 300 K. The nanowire has a cross section of 30×6 nm2. In this case the IIS process was employed with an activation temperature of 700°C after tilted ion implantations into the single crystalline NiSi2 layers. The average slope in the Id range, 10-7 to 10-4 µA/µm, amounts to ~90 mV/dec. In contrast to Fig. 6, no kink of the transfer curve appeared, which indicates a more perfect tunnel junction due to the IIS process. Compared to DS devices of Fig. 4 and Fig. 5, IIS generates obviously less or no damage to the silicon. We assume that the absence of implantation induced damage in the silicon led also to a better silicide-gate alignment which helps to enhance the tunneling current as explained above. The on-current reaches a record value of 60 µA/µm at Vd = -0.7 V and Vg = -1.5 V for Si NW TFETs. As compared to the
Fig. 7: Temperature dependence of SS extracted from region II of a planar TFET in comparision with aconventional p-MOSFET.
Even better performance was achieved by using strained SOI (SSOI). The strained Si of SSOI wafers, supplied by SOITEC has a tensile strain of 1%, corresponding to a stress of 1.4 GPa. Previously, we have shown that patterning of the layer into nanowires transforms the biaxial strain into uniaxial strain since the strain across the narrow wire relaxes while the strain along the wire fully maintains. This leads to an enhancement of the electron mobility and the output current of about a factor of two [8]. Since the BTBT transmission probability in a TFET decreases exponentially with band gap of the junction material, a small reduction of the band gap as in the strained Si nanowires will lead to a further improvement of the TFET. Due to the high resistance of the tunnel junction the enhancement of the mobility will have less effect than in a normal MOSFET.
155
IV.
CONCLUSIONS
A simple, low temperature process for TFET fabrication has been developed using tilted implantation to from the junctions at S/D. Since no implantation masks are needed further scaling should be easily possible. While the DS process gives rise to TAT, IIS seems much more appropriate to form silicided tunnel junctions providing with very large on currents for Si TFETs. For both, DS and IIS, a maximum T of only 700°C is sufficient to activate the dopants. As compared with planar devices Si nanowire array TFETs showed better slopes and very high on-currents up to 60 µA/µm at Vdd=0.7 V. A remarkable improvement was achieved with 30x10 nm2 NW array TFETs with uniaxial strained Si nanowires delivering a minimum slope of 50 mV/dec over 3 orders of magnitude of Id at 300K. Acknowledgement
Fig. 8: Id- Id-Vgs characteristics of a 200 nm gate length nanowire array p-TFET measured at 300K
This work is supported by European project STEEPER.
The uniaxial strained Si (sSi) nanowires have a smaller band gap, around 0.8 eV as compared to 1.1 eV of Si, which is beneficial for BTBT. Fig. 9 shows the transfer characteristics of sSi nanowire array n-TFETs with a nanowire dimensions of 30x10 nm2. In addition, the gate leakage current Ig is also shown. The minimum slope measured at Vd = 0.18 V amounts to 50 mV/dec, clearly below values attainable in a normal MOSFET. The on-current at Vd = 0.5 V reaches 7 µA/µm which is also high compared with published values. Interestingly the n-type TFET, shown in Fig. 9, improved significantly. The out-diffusion was performed at 450°C instead of 700°C to minimize Boron diffusion. Thus, we assume that the slower Boron diffusion in strained silicon is beneficial for n-type TFETs. The IIS process may also be more suited to maintain the strain in the wires, since no ion implantation occurs in the Si channel region of the device.
Vd=0.5V
1
10
-1
I d /I g (µA/µm)
10
-3
10
REFERENCES [1]
[2]
[3]
[4]
[5] [6]
[7]
Vd=0.18V
[8]
50mV/dec
Ig
-5
10
[9]
-7
10
-9
10
-0.5
0.0
0.5
1.0
1.5
Vgs(V) Fig. 9: Id- Id-Vgs characteristics of strained Si nanowire array nTFET with a gate length of 200 nm measured at 300K.
156
Adrian M. Ionescu and Heike Riel, “Tunnel field-effect transistors as energy-efficient electronic switches”, Nature 16;479(7373):329-37, 2011 L. Knoll, Q.T. Zhao, S. Habicht, C. Urban, B. Ghyselen and S. Mantl, “Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained Silicon”, IEEE Electron Device Lett., 31(2010)350 C. Urban, C. Sandow, Q.T. Zhao, J. Knoch , S. Lenk and S. Mantl, “Systematic study of Schottky barrier MOSFETs with dopant segregation on thin-body SOI”, Solid-State Electronics 54 (2010) 185– 190, 2010 S. F. Feste et al,” Formation of steep, low Schottky-barrier contacts by dopant segregation during nickel silicidation”, J. Appl. Phys. 107, 044510, 2010 D. Leonelli et al, “Silicide Engineering to Boost Si Tunnel Transistor Drive Current”, J. J. Appl. Phys. 50, 04DC05, 2011 E. Simoen, F. De Stefano, G. Eneman, B. De Jaeger, C. Claeys and F. Crupi, “On the Temperature and Field Dependence of Trap-Assisted Tunneling Current in Ge p+n Junctions”., IEEE Electron Device Lett., 30(2009)562 J. Knoch, “Optimizing tunnel FET performance – Impact of device structure, transistor dimensions and choice of material”, VLSI-TSA, 2009 Z. Zhang, Z. Qiu, R. Liu, M. Östling and S.-L. Zhang, “SchottkyBarrier Height Tuning by Means of Ion Implantation Into Preformed Silicide Films Followed by Drive-In Anneal”, IEEE Electron Device Lett., 28, no. 7, 2007 S. Habicht, S. Feste, Q.-T. Zhao, Dan buca and S. Mantl, „ Electrical characterization of Ω-gated uniaxial tensile strained Si nanowire-array metal-oxide-semiconductor field effect transistors with - and channel orientations“, Thin Solid Films Vol. 520, Issue 8, 2012
Abstract—Planar and nanowire (NW) tunneling field effect transistors (TFETs) have been fabricated on ultra thin strained and unstrained SOI with shallow doped Nickel disilicide (NiSi2) source and drain (S/D) contacts. We developed a novel, self-aligned process to form the p-i-n TFETs which greatly easies their fabrication by tilted dopant implantation using the high-k/metal gate as a shadow mask and dopant segregation. Two methods of dopant segregation are compared: Dopant segregation based on the “snowplough” effect of dopants during silicidation and implantation into the silicide (IIS) followed by thermal outdiffusion. High drive currents of up to 60 µA/µm of planar p-TFETs were achieved indicating good silicide/silicon tunneling junctions. The non linear temperature dependence of the inverse subthreshold slope S indicates typical TFET behavior. Strained Si NW array n-TFETs with omega shaped HfO2/TiN gates showed high drive currents of 7 µA/µm @ 1V Vdd and steep inverse subthreshold slopes with minimum values of 50mV/dec due to the smaller band gap of strained Si and optimized electrostatics. I.
INTRODUCTION
Band-to-band tunneling field effect transistors (TFET) are most promising for ultralow power applications. Due to the enhanced switching performance and low power consumption TFETs show distinct advantages as compared to standard CMOS [1]. However, silicon TFETs suffer from very low oncurrents, mainly due to the relatively large band gap of
~1.1 eV. A lower band-gap material like strained Si or SiGe enhances the band-to-band tunneling probability and thus the on-currents. Also the doping profile of the tunnel junction affects sensitively the tunneling probability. The advantage of silicon based materials is the availability of the highly advanced Si technology which helps to meet the critical requirements for high-k/metal gate stack and S/D junction formation. In this paper we make use of this by studying TFETs with silicon and strained Si, which offers a lower band gap than unstrained Si. Along this line we investigated two dopant segregation methods to form the silicide tunnel junctions with abrupt doping profiles at S/D at low temperatures. We investigated planar and nanowire array TFETs on ultrathin SOI and strained SOI. II.
Planar TFETs were fabricated on SOI substrates with top silicon thicknesses of 15 nm and 6 nm, respectively. A simple process without additional implantation masks was developed as sketched in Fig.1. Using the TiN/HfO2 gate stack as a shadow mask tilted B+ and As+ implantations at an angle of 45° and 135° allow the formation of aligned n+ and p+ regions self-aligned at the gate edges. For B an implantation energy of 1 keV and a dose of 2×1015/cm2 and for As 5 keV and a dose of 2×1015/cm2 were used. Silicidation was performed at 700°C to form epitaxial NiSi2 layers for S/D. Simultaneously dopant segregation (DS) occured and formed shallow highly doped pockets at the edge of the silicide, producing p+-pocket on the right side and n+-pocket on the right side of the gate. We assume that only the dopants of the “shadow” regions form the junctions, while the other dopants are incorporated in the metallic silicide and have no electrical effects. This process is labeled “DS” in Fig. 1. Alternatively, epitaxial NiSi2 was formed first, than implanted at tilt angles as stated above and RTP annealed at 700°C to drive-out and activate the implanted dopants and recover the crystal structure. This process is known as “Implantation Into Silicide” (IIS). The silicide is epitaxial NiSi2 formed with only 3 nm Ni [2]. All the processes were performed at fairly low temperatures with Tmax = 700°C. Planar and nanowire devices were fabricated. Fig. 2 shows a TEM image of the source part of a planar device on 15 nm SOI (left), and an SEM image of an -gated nanowire array device (right). These Si nanowires have a width of 30 nm and a thickness of ~6 nm made from ultrathin
This work was partially supported by the EU project STEEPER.
978-1-4673-1708-5/12/$31.00 ©2012 IEEE
FABRICATION
153
SOI with electron beam lithography and dry etching. The HfO2 with a thickness of 3 nm was deposited conformally by atomic layer deposition and TiN by vapor deposition.
Abrupt dopant profiles are needed for this purpose. A great advantage of DS is that very steep dopant profiles can be achieved at low T process [3,4]. In a p-type TFET minority carriers, holes, tunnel into the channel and electrons from the channel into the reservoir. Only at appropriate gate and drain bias a narrow energy window opens to enable BTBT as in Fig. 3.
Fig. 1: TFET fabrication process using tilted B+ and As+ ion implants into Si (DS process) or into epitaxial NiSi2 (IIS process) as S/D contacts. Highly doped pockets at the silicide edges are formed by dopant segregation.
Fig. 3: Schematic band diagram of a TFET with dopant segregation at the NiSi2 Schottky source/drain contacts under reverse bias. Band to band tunneling is indicated beween the n+ Source region and the intrinsic
Fig. 2: Cross sectional TEM image of a planar device with epitaxial NiSi2 source after IIS perfectly aligned with the HfO2/TiN gate (left) and an SEM image of a NW-array TFET with a 200 nm HfO2/TiN gate (right)
III.
RESULTS AND DISCUSSION
A TFET consists of a gated p-i-n diode which allows under appropriate reverse bias conditions band to band tunneling. A schematic band structure of a TFET with silicide Schottky contacts and highly doped pockets under reverse bias is shown in Fig. 3. Dopant segregation produces highly doped regions close to the NiSi2 contacts leading to strong band bending. As a consequence, the effective Schottky barrier is lowered to very small values (< 0.2 eV). With other words, the ultrathin barrier becomes transparent via carrier tunneling. By applying this method we have fabricated Schottky-Barrier MOSFETs with output currents exceeding 1mA/µm and remarkable RF performance [3]. Here, we make use of this method for TFETs. As compared to a standard TFET, a Schottky barrier controls the carrier injection from the silicide into the (electron) reservoir formed behind the Schottky barrier. Band to band tunneling is expected between the source reservoir and the channel when an energy window between the source Fermi energy and the valence band edge of the channels opens at appropriate gate and drain bias. For efficient BTBT the tunneling junction should be aligned with the fringing field of the gate edge to obtain a large electric field and the conduction and valence bands should come sufficently close to minimize the tunneling path (see arrow in Fig 3).
Fig.4 shows the output characteristics measured at 300 K of a planar p-TFET, which was fabricated with the DS process. The 400nm gate length device shows perfect saturation. The corresponding transfer characteristics are presented in Fig.5. It has to be mentioned that the noise in the off-state stems from the measurement setup and not from gate leakage. The subthreshold regime shows two different slopes labeled as regions I and II with inverse subthreshold slopes (SS) of 94 mV/dec and 190 mV/dec, respectively. Region II indicates a voltage dependent slope, typical for TFETs. Fig. 6 shows the Id-Vg characteristics measured from 100 K to 350 K at Vd = -0.1 V. Region I extends from about 200 K 350 K. We assume that trap assisted tunneling (TAT) occurs in this region as reported in [5] and [6], while in region II BTBT may dominate. This is further substantiated, by the results of Fig. 7, showing SS(T) of region II. For T > 200 K, SS(T) decreases rapidly, when, as we assume, TAT and BTBT occur simultaneously. At T < 200 K, SS(T) changes less rapidly and becomes even constant at T < 100 K which indicates BTBT. For comparison, the linear SS(T) dependence of a conventional MOSFET fabricated with the same process is presented. We conclude that remaining end of range defects, steming from the ion implantation before the silicidation, cause TAT in the tunneling junction which degrades the TFET performance drastically. Therefore, we investigated also IIS for tunnel junction formation. The IIS process has the advantage that the dopant implantation occurs into the metallic silicide and not into the Si channel material and the dopants are driven out by thermal annealing. Residual defects in the metallic contacts will have no effect on the tunnel junction behavior. In addition, we further improved the electrostatic gate control by reducing the silicon thickness to 6nm and the formation of nanowire array transistors. These measures improve significantly the natural
154
length , a measure for good gate control [7]. The IIS process is also advantageous for doping of nanowires which is anyway a complex issue due to dopant deactivation [8].
devices of Fig. 4 the improvement may come partly from a higher dopant concentration in the junction since we used the same implant parameters as for the somewhat thicker films
Fig. 4: Output characteristics of a 400 nm planar p-TFET at 300 K
Fig. 6: Id-Vgs characteristics of a planar p-TFET measured between 350 K and 100 K
Fig. 5: Transfer characteristics of a p-TFET at 300 K
The TFET performance was further improved by using nanowire structures fabricated with 6nm SOI substrates. Fig.8 shows the transfer characteristics of a nanowire array p-TFET with a 200 nm HfO2/TiN gate at 300 K. The nanowire has a cross section of 30×6 nm2. In this case the IIS process was employed with an activation temperature of 700°C after tilted ion implantations into the single crystalline NiSi2 layers. The average slope in the Id range, 10-7 to 10-4 µA/µm, amounts to ~90 mV/dec. In contrast to Fig. 6, no kink of the transfer curve appeared, which indicates a more perfect tunnel junction due to the IIS process. Compared to DS devices of Fig. 4 and Fig. 5, IIS generates obviously less or no damage to the silicon. We assume that the absence of implantation induced damage in the silicon led also to a better silicide-gate alignment which helps to enhance the tunneling current as explained above. The on-current reaches a record value of 60 µA/µm at Vd = -0.7 V and Vg = -1.5 V for Si NW TFETs. As compared to the
Fig. 7: Temperature dependence of SS extracted from region II of a planar TFET in comparision with aconventional p-MOSFET.
Even better performance was achieved by using strained SOI (SSOI). The strained Si of SSOI wafers, supplied by SOITEC has a tensile strain of 1%, corresponding to a stress of 1.4 GPa. Previously, we have shown that patterning of the layer into nanowires transforms the biaxial strain into uniaxial strain since the strain across the narrow wire relaxes while the strain along the wire fully maintains. This leads to an enhancement of the electron mobility and the output current of about a factor of two [8]. Since the BTBT transmission probability in a TFET decreases exponentially with band gap of the junction material, a small reduction of the band gap as in the strained Si nanowires will lead to a further improvement of the TFET. Due to the high resistance of the tunnel junction the enhancement of the mobility will have less effect than in a normal MOSFET.
155
IV.
CONCLUSIONS
A simple, low temperature process for TFET fabrication has been developed using tilted implantation to from the junctions at S/D. Since no implantation masks are needed further scaling should be easily possible. While the DS process gives rise to TAT, IIS seems much more appropriate to form silicided tunnel junctions providing with very large on currents for Si TFETs. For both, DS and IIS, a maximum T of only 700°C is sufficient to activate the dopants. As compared with planar devices Si nanowire array TFETs showed better slopes and very high on-currents up to 60 µA/µm at Vdd=0.7 V. A remarkable improvement was achieved with 30x10 nm2 NW array TFETs with uniaxial strained Si nanowires delivering a minimum slope of 50 mV/dec over 3 orders of magnitude of Id at 300K. Acknowledgement
Fig. 8: Id- Id-Vgs characteristics of a 200 nm gate length nanowire array p-TFET measured at 300K
This work is supported by European project STEEPER.
The uniaxial strained Si (sSi) nanowires have a smaller band gap, around 0.8 eV as compared to 1.1 eV of Si, which is beneficial for BTBT. Fig. 9 shows the transfer characteristics of sSi nanowire array n-TFETs with a nanowire dimensions of 30x10 nm2. In addition, the gate leakage current Ig is also shown. The minimum slope measured at Vd = 0.18 V amounts to 50 mV/dec, clearly below values attainable in a normal MOSFET. The on-current at Vd = 0.5 V reaches 7 µA/µm which is also high compared with published values. Interestingly the n-type TFET, shown in Fig. 9, improved significantly. The out-diffusion was performed at 450°C instead of 700°C to minimize Boron diffusion. Thus, we assume that the slower Boron diffusion in strained silicon is beneficial for n-type TFETs. The IIS process may also be more suited to maintain the strain in the wires, since no ion implantation occurs in the Si channel region of the device.
Vd=0.5V
1
10
-1
I d /I g (µA/µm)
10
-3
10
REFERENCES [1]
[2]
[3]
[4]
[5] [6]
[7]
Vd=0.18V
[8]
50mV/dec
Ig
-5
10
[9]
-7
10
-9
10
-0.5
0.0
0.5
1.0
1.5
Vgs(V) Fig. 9: Id- Id-Vgs characteristics of strained Si nanowire array nTFET with a gate length of 200 nm measured at 300K.
156
Adrian M. Ionescu and Heike Riel, “Tunnel field-effect transistors as energy-efficient electronic switches”, Nature 16;479(7373):329-37, 2011 L. Knoll, Q.T. Zhao, S. Habicht, C. Urban, B. Ghyselen and S. Mantl, “Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained Silicon”, IEEE Electron Device Lett., 31(2010)350 C. Urban, C. Sandow, Q.T. Zhao, J. Knoch , S. Lenk and S. Mantl, “Systematic study of Schottky barrier MOSFETs with dopant segregation on thin-body SOI”, Solid-State Electronics 54 (2010) 185– 190, 2010 S. F. Feste et al,” Formation of steep, low Schottky-barrier contacts by dopant segregation during nickel silicidation”, J. Appl. Phys. 107, 044510, 2010 D. Leonelli et al, “Silicide Engineering to Boost Si Tunnel Transistor Drive Current”, J. J. Appl. Phys. 50, 04DC05, 2011 E. Simoen, F. De Stefano, G. Eneman, B. De Jaeger, C. Claeys and F. Crupi, “On the Temperature and Field Dependence of Trap-Assisted Tunneling Current in Ge p+n Junctions”., IEEE Electron Device Lett., 30(2009)562 J. Knoch, “Optimizing tunnel FET performance – Impact of device structure, transistor dimensions and choice of material”, VLSI-TSA, 2009 Z. Zhang, Z. Qiu, R. Liu, M. Östling and S.-L. Zhang, “SchottkyBarrier Height Tuning by Means of Ion Implantation Into Preformed Silicide Films Followed by Drive-In Anneal”, IEEE Electron Device Lett., 28, no. 7, 2007 S. Habicht, S. Feste, Q.-T. Zhao, Dan buca and S. Mantl, „ Electrical characterization of Ω-gated uniaxial tensile strained Si nanowire-array metal-oxide-semiconductor field effect transistors with - and channel orientations“, Thin Solid Films Vol. 520, Issue 8, 2012
