Simplified Low-Voltage CMOS Syllabic Companding Log Domain Filter
Simplified Low-Voltage CMOS Syllabic Companding Log Domain Filter Ippei Akita, Kazuyuki Wada, and Yoshiaki Tadokoro Graduate School of Engineering, Toyohashi University of Technology, Toyohashi, 441–8580, Japan Email: [email protected] Abstract— This paper proposes a low-voltage syllabic companding log domain filter without state variable correction circuits, which is needed for externally linear and time-invariant operation of conventional filters. The proposed filter is simplified and has wide input range under low-supply voltage by varying a nodal voltage adaptively. The simulation results show 60-dB input range for over 40-dB signal to noise plus distortion ratio at a power supply of 0.6 V in a 0.18-µm CMOS process.
I. I NTRODUCTION The technique of low-voltage CMOS analog integrated circuit design is indispensable for implementing several portable applications such as sensing and telecommunication circuits because of requirement of low power consumption and degradation of device breakdown voltage. In the design of low voltage analog circuits, low headroom of an internal voltage makes difficult to achieve a required specification of dynamic rage. Syllabic companding technique, especially dynamically adjustable biasing (DAB) technique combining with log domain circuits, is useful to realize wide dynamic range characteristic [1,2]. Although the DAB technique is modified for low voltage operation in Ref. [3], the complexity of the circuit increases compared with a filter based on the DAB technique of Ref. [2] because a state variable correction (SVC) circuit is needed to keep externally liner, time-invariant (ELTI) operation in the low-voltage version. In this paper a novel syllabic companding log domain filter with no SVC circuit is proposed. Although an SVC circuit is not used, ELTI characteristic of the proposed filter is kept. Its circuit scale is comparable to that of the conventional DAB filter, while the dynamic range is higher than the DAB one at low supply voltage. Simulation results show the proposed filter is effective for dynamic range at low supply voltage. II. L OW-VOLTAGE I NTEGRATOR WITH N O S TATE VARIABLE C ORRECTION C IRCUIT A schematic of an integrator based on the DAB technique is shown in Fig. 1(a). In this circuit it is assumed that all MOSFETs are in weak inversion region where a drain current Id is expressed as an exponential function of its gate-to-source voltage Vgs ; Id = IS exp(Vgs /nUT ). A current IS is dependent on a fabrication process and proportional to the aspect ratio of the MOSFET, and n and UT are a slope factor and the thermal voltage, respectively. The diode-connected MOSFETs 1-4244-0921-7/07 $25.00 © 2007 IEEE.
Minp and Minm logarithmically convert input currents Iinp and Iinm into voltages Vip and Vim , respectively, which are inputs of a log-domain integrator core composed of a logdomain operational transconductance amplifier (OTA) shown in Fig. 1(b) and a capacitor C. An output voltage Vo of the logdomain integrator core is exponentially converted to an output current Iout through Mout as an expander. Since a bias current Ibias and a bias voltage Vb are constant, a source potential VC of Ms is also fixed. A control current Ig is dynamically varied according to an envelop of the input current to achieve wide-dynamic range characteristic [1–3]. Furthermore, since Ig is a common-mode current of Iinp and Iinm , the differential structure eliminates the influence of this current for Iout [2]. In Fig. 1(a), nevertheless, changing the bias current of Minp and Minm with Ig , the common-mode voltages of Vip and Vim also change, leading to narrower dynamic range under low supply voltage because the input range of the log-domain OTA is limited. Figure 1(c) shows a modified version of a DAB-based integrator for low voltage operation [3]. In this configuration, since the common-mode voltages of Vip and Vim is kept constant by varying the source potential VC of Ms with Ig , a required input range of the log-domain OTA may be narrower than that of the previous DAB-based integrator. Therefore, the schematic of Fig. 1(c) is suitable for low-voltage circumstances. However, a current nUT CIg0 /Ig , which is generated by an SVC circuit, is required in parallel with a capacitor C in order to ensure ELTI relation between Iin and Iout . In Ref. [3], the device size of two MOSFETs in an SVC circuit should be large due to limitation of its topology at a low supply voltage. Parasitic components of large devices in an SVC circuit make difficult to accurately obtain a required SVC current and then an output error arises. On the other hand, the integrator shown in Fig. 1(a) needs no SVC circuit. Therefore, the schematic of Fig. 1(a) is suitable from the viewpoint of complexity of circuits. For the problem discussed above about both of low voltage and small circuit, a solution is proposed in Fig. 1(d). The proposed configuration is also a modified version of a DABbased one in Fig. 1(a) where a terminal of C is connected with the source terminal of Ms and Ibias in Fig. 1(a) is replaced with Ig . ELTI relation between Iin and Iout can be proved as follows. First, log-compression function of Iinp at Minp and
2244
Iinp
I bias
Ig
Ig Vip
Minp Iinm Ms
I1
Log-domain OTA
VC = nUT ln
Vo
Vim
Minm
Vb
Substituting Eqs. (1), (2), and
Iout
Mout
C
Mp2 I1
M2
Vip
Vim
M1
I1
Vim
M3
M4
Vo
Vo
Vip
+ Vb
(5)
dIout (6) dt is obtained where Ω = I0 /(nUT C) and Iin = Iinp − Iinm . It is known that the proposed circuit of Fig. 1(d) is an ELTI integrator and does not require an SVC current. Furthermore, the common-mode voltages of Vip and Vim , which are input voltages of the log-domain OTA, can be kept constant by appropriately biasing Minp , Minm , and MS with Ig . Therefore, the proposed integrator in Fig. 1(d) can operate at low supply voltage.
(a)
I0
ΩIin =
VDD Mp1
IS Ig
into Eq. (4), a differential equation
Vc
M0
(b)
Ig
Iinp
Ig
Iinm
Ig
SVC current : Vip
Minp
nUTC
I1
I g’ Ig Vo
Vim
Minm
Mout
C
Vb Ms
III. F ILTER I MPLEMENTATION
Iout
Vc
M0
(c)
Iinp
Ig
Ig
Ig
Iout Vip
Minp Iinm Vb
I1
Vim
Minm
C
Ms M0
Vo
Mout
Vc (d)
Fig. 1. Syllabic companding log domain integrators; (a) the DAB-based integrator [2], (b) the log-domain operational transconductance amplifier (OTA), (c) the modified version of (a) for low voltage operation [3], and (d) proposed schema with no state variable correction (SVC) circuit.
expansion function of Vo at Mout can be expressed as Iinp + Vb Vip = nUT ln 1 + Ig and Vo = nUT ln
Ioutp Ig
+ Vb ,
(1)
(2)
respectively. An output current I1 of the log-domain OTA in Fig. 1(b) is given as V −Vo Vim −Vo ip nUT nUT I1 = I 0 e −e . (3) Hence, Kirchhoff’s current law at the gate terminal of Mout gives V −Vo Vim −Vo ip d nUT nUT −e = C (Vo − VC ) . (4) I0 e dt
The modification for simple low-voltage log-domain integrators is applicable to the log-domain filters. As an example of this proposed modification, the third-order Butterworth lowpass filter with a 100-kHz cutoff frequency is designed. In this example, a pseudo differential form of log-domain filter cores is employed to eliminate an influence of Ig biasing Minp and Minm [2]. A half pseudo differential log-domain filter core is synthesized in the log domain by leap frog simulation as shown in Fig. 2(b) [4]. The bottom terminals of the capacitors C1 , C2 , and C3 are connected with the source terminal of Ms to keep ELTI relation between Iin and Iout as expressed in the previous section. Letting all bias current I1 , I2 , and I3 be 1.0 µA, the capacitances are set as C1 = C3 = 50 pF and C2 = 100 pF for the desired cutoff frequency. All aspect ratios (width/length) of Minp , Minm , Moutp , Moutm and MS are set as 384 µm/0.42 µm, and that of M0 is as 300 µm/0.18 µm. This filter is designed using a 0.18-µm CMOS process and a 0.6-V supply voltage VDD . A control circuit in Fig. 2(a) generates Ig which determines dynamic range of the filter and must be designed for a wide dynamic range. A control circuit shown in Fig. 3 is used here [3] and Ig takes any one of three discrete values Iref 1 , Iref 2 , or Iref 3 at a time by switching S1 to S3 according to an amplitude of input signal [5]. If Iref 1 < Iref 2 < Iref 3 is satisfied, for example, Ig is set to Iref i (i = 1, 2, or 3) when the amplitude |Iin | of an input current is in the region as Iref (i−1) < |Iin | ≤ Iref i where Iref 0 = 0. A circuit controlling the switches can be implemented by use of a peak detector, several comparators, and some reference current sources as described in Ref. [3]. The number of current sources in the control circuit is not limited to only three and this circuit can be easily extended according to a filter specification. A resistor RL and a capacitor CL compose a simple low-pass filter to avoid large disturbance at the input stage comprised of Minp , Minm , and MS . Here those values are chosen as RL = 100 kΩ and CL = 50 pF. The number of current sources and their values are determined as follows. Figure 4 shows simulation results of
2245
Control Circuit
Ig
Ig Iinp
Ig Vinp
Minp
Iinm Vb
Moutm
Ms
VC
M0
(a)
Mp2
I1
Mp3
M2
2
M4 Mf
M1
Ioutm
Moutp
Voutm
VDD
Vinp
Iout
Ioutp
Voutp
Vinm
Minm
Mp1
VDD
Pseudo Differential Log-Domain Filter Core
Mp4
I2
Mp5
M5
M7
M3
M8
M6
Ms1
Voutp
M9
Ms2
C1
Mp6
I3
Ms3
C2
C3
VC (b)
Fig. 2. The overall third-order Butterworth syllabic-companding log domain filter; (a) the proposed schema with no state variable correction (SVC) circuit, and (b) the third-order Butterworth log-domain filter core.
VDD
Ig=4uA
Ig=400nA
S1
I ref 2
S2
I ref 3
0
S3
gain [dB]
I ref 1
Ig
RL CL Fig. 3.
Ig=50uA
20 -20 -40
6 4 2 0
-60 -80
100k
-100 -120
Control circuit.
1k
10k
100k
1M
10M
frequency [Hz]
Fig. 5. Ig=400nA
70
Ig=3.2uA
Frequency Responses in case for each Ig .
Ig=51.2uA
SNDR [dB]
60 50 40
IV. S IMULATION R ESULTS
SNDRSpec.
30 20
DR = 60 dB
10 0
1n
10n
100n
1u
10u
100u
input curret [A]
Fig. 4. Signal to noise plus distortion ratios (SNDRs) in multiples from 100-nA to 208-µA Ig .
signal to noise plus distortion ratios (SNDRs) corresponding to various Ig from 100 nA to 208.4 µA in multiples of two where a distortion is calculated by summing from the 2nd to the 9th harmonic components of output current Iout for a 100-kHz sinusoidal input current and noise means the RMS output current noise integrated over the bandwidth of 400 kHz during one period. Considering a specification of a 60-dB input range for over 40-dB SNDR as an example, the bias currents of Fig. 3 are chosen as Iref 1 = 400 nA, Iref 2 = 4.0 µA, and Iref 3 = 50 µA. Their current values are determined for a current consumption to be as small as possible.
The proposed syllabic-companding log domain filter is simulated to confirm the characteristics. The parameters determined in the previous section are used in this simulation. First of all, frequency response of the proposed filter is verified. Figure 5 shows the simulation results where a control circuit used in Fig. 2(a) is replaced with a 3-output constant current source of fig. 3. The filter has a 96.5-kHz cutoff frequency each Ig as seen from Fig. 5. Figure 6(a) shows the fundamental component of Iout , total harmonic distortion, and an RMS output current noise from DC to 400 kHz during one period, versus amplitude of a 100kHz sinusoidal input current Iin . In Fig. 6(a), the fundamental output current increases in proportion to an input current, while output noise does stepwise. Figure 6(b) shows an SNDR characteristic obtained from results of Fig. 6(a). As seen from Fig. 6(b) the proposed filter can satisfy the specification of a 60-dB input range over 40-dB SNDR. Figure 7(a) shows a 100-kHz sinusoidal input current Iin with an envelope changed, and a control current Ig . In Fig. 7(b) waveform of the log-compressed voltage Vinp of the proposed
2246
50u 40u Iout
current [A]
RMS output current [A]
100u 10u 1u 100n 10n 1n 100p 10p 1p
noise : DC - 400 kHz harmonics : 2nd - 9th 10n
100n 1u input curret [A] (a)
Ig
30u 20u Iin
10u 0 -10u
10u
0
100u 200u 300u 400u 500u 600u 700u 800u time [sec] (a)
70
420m 410m
50 40
SNDRSpec. DR = 60 dB
30 20
voltage [V]
SNDR [dB]
60
10n
100n 1u input curret [A] (b)
380m
360m
Vinp
current [A]
FILTER CHARACTERISTICS .
3rd -order Butterworth 0.18-µm standard CMOS 96.5 kHz 0.6 V 100 dB 400 nA 4 µA 50 µA 45 µW 59.6 µW 198 µW 912 nA 9.6 µA 88.4 µA 351 pArms 2.19 nArms 19.4 nArms
0
100u 200u 300u 400u 500u 600u 700u 800u time [sec] (b)
TABLE I S UMMARY OF THE
390m
370m
10u
Fig. 6. Dynamic Range characteristics at a 100-kHz sinusoidal input current; (a) the rms fundamental Iout , the total harmonic distortion components in rms, and the rms output current noise for one period, and (b) Signal to noise plus distortion ratio (SNDR) versus Iin .
Order and type Technology Cutoff frequency Supply voltage Dynamic range Control current Ig Power Dissipation Input-referred IP3 Output current noise
400m
10u 8u 6u 4u 2u 0 -2u -4u -6u -8u -10u
Iout
0
100u 200u 300u 400u 500u 600u 700u 800u time [sec] (c)
Fig. 7. Transient responses; (a) Iin and Ig , (b) log-compressed voltage Vinp , and (c) the output current Iout .
filter is depicted. It is verified that the bias voltage of Vinp keeps almost constant. Figure 7(c) shows the output current Iout of the proposed filter. Table I shows summary of the filter characteristics. The proposed filter operates well for low voltage such as a 0.6-V VDD . In addition, when Ig changes from 400 nA to 50 µA, the current consumption is observed as 75 to 330 µA which corresponds to 45- to 198-µW power consumption. Finally, the proposed filter has 100-dB dynamic range, which is calculated from the ratio of the input current over 40-dB SNDR to minimum noise floor. V. C ONCLUSION A low-voltage syllabic-companding log domain filter with no state variable correction circuits has been proposed. The proposed filter is easily simplified by varying a terminal voltage of capacitors adaptively and still has wide dynamic range even at a low supply voltage. Simulation results show 60-dB input range and an over 40-dB signal to noise plus distortion ratio at a power supply of 0.6 V in a 0.18-µm CMOS process. Future works are fabrication and measurement.
ACKNOWLEDGMENT This study was supported by the 21st Century COE Program “Intelligent Human Sensing” from the ministry of Education, Culture, Sports Science and Technology of Japan and VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc. R EFERENCES [1] Y.Tsividis, “Externally linear time-invariant systems and their applications to companding signal processors, ” IEEE Trans. Circuits and Systems II, vol.44, pp.65-85, Feb. 1997. [2] N.Krishnapura and Y.Tsividis, “Noise and power reduction in filters through the use of adjustable biasing, ” IEEE J. Solid-State Circuits, vol.36, pp.1912-1920, Dec. 2001. [3] I. Akita, K. Wada, and Y. Tadokoro, “Low-voltage CMOS syllabiccompanding log domain filter, ” in Proc. 2006 IEEE Int. Symp. Circuits and Systems, pp.3337-3340, 2006. [4] D. Python and C. C. Enz, “A micropower class-AB log-domain filter for DECT applications, ” IEEE J. Solid-State Circuits, vol.36, pp.1067-1075, July 2001. [5] Y. Palaskas, Y. Tsividis, V. Prodanov, and V. Boccuzzi, “A “divide and conquer” technique for implementing wide dynamic range continuoustime filters, ” IEEE J. Solid-State Circuits, vol.39, pp.297-307, Feb. 2004.
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I. I NTRODUCTION The technique of low-voltage CMOS analog integrated circuit design is indispensable for implementing several portable applications such as sensing and telecommunication circuits because of requirement of low power consumption and degradation of device breakdown voltage. In the design of low voltage analog circuits, low headroom of an internal voltage makes difficult to achieve a required specification of dynamic rage. Syllabic companding technique, especially dynamically adjustable biasing (DAB) technique combining with log domain circuits, is useful to realize wide dynamic range characteristic [1,2]. Although the DAB technique is modified for low voltage operation in Ref. [3], the complexity of the circuit increases compared with a filter based on the DAB technique of Ref. [2] because a state variable correction (SVC) circuit is needed to keep externally liner, time-invariant (ELTI) operation in the low-voltage version. In this paper a novel syllabic companding log domain filter with no SVC circuit is proposed. Although an SVC circuit is not used, ELTI characteristic of the proposed filter is kept. Its circuit scale is comparable to that of the conventional DAB filter, while the dynamic range is higher than the DAB one at low supply voltage. Simulation results show the proposed filter is effective for dynamic range at low supply voltage. II. L OW-VOLTAGE I NTEGRATOR WITH N O S TATE VARIABLE C ORRECTION C IRCUIT A schematic of an integrator based on the DAB technique is shown in Fig. 1(a). In this circuit it is assumed that all MOSFETs are in weak inversion region where a drain current Id is expressed as an exponential function of its gate-to-source voltage Vgs ; Id = IS exp(Vgs /nUT ). A current IS is dependent on a fabrication process and proportional to the aspect ratio of the MOSFET, and n and UT are a slope factor and the thermal voltage, respectively. The diode-connected MOSFETs 1-4244-0921-7/07 $25.00 © 2007 IEEE.
Minp and Minm logarithmically convert input currents Iinp and Iinm into voltages Vip and Vim , respectively, which are inputs of a log-domain integrator core composed of a logdomain operational transconductance amplifier (OTA) shown in Fig. 1(b) and a capacitor C. An output voltage Vo of the logdomain integrator core is exponentially converted to an output current Iout through Mout as an expander. Since a bias current Ibias and a bias voltage Vb are constant, a source potential VC of Ms is also fixed. A control current Ig is dynamically varied according to an envelop of the input current to achieve wide-dynamic range characteristic [1–3]. Furthermore, since Ig is a common-mode current of Iinp and Iinm , the differential structure eliminates the influence of this current for Iout [2]. In Fig. 1(a), nevertheless, changing the bias current of Minp and Minm with Ig , the common-mode voltages of Vip and Vim also change, leading to narrower dynamic range under low supply voltage because the input range of the log-domain OTA is limited. Figure 1(c) shows a modified version of a DAB-based integrator for low voltage operation [3]. In this configuration, since the common-mode voltages of Vip and Vim is kept constant by varying the source potential VC of Ms with Ig , a required input range of the log-domain OTA may be narrower than that of the previous DAB-based integrator. Therefore, the schematic of Fig. 1(c) is suitable for low-voltage circumstances. However, a current nUT CIg0 /Ig , which is generated by an SVC circuit, is required in parallel with a capacitor C in order to ensure ELTI relation between Iin and Iout . In Ref. [3], the device size of two MOSFETs in an SVC circuit should be large due to limitation of its topology at a low supply voltage. Parasitic components of large devices in an SVC circuit make difficult to accurately obtain a required SVC current and then an output error arises. On the other hand, the integrator shown in Fig. 1(a) needs no SVC circuit. Therefore, the schematic of Fig. 1(a) is suitable from the viewpoint of complexity of circuits. For the problem discussed above about both of low voltage and small circuit, a solution is proposed in Fig. 1(d). The proposed configuration is also a modified version of a DABbased one in Fig. 1(a) where a terminal of C is connected with the source terminal of Ms and Ibias in Fig. 1(a) is replaced with Ig . ELTI relation between Iin and Iout can be proved as follows. First, log-compression function of Iinp at Minp and
2244
Iinp
I bias
Ig
Ig Vip
Minp Iinm Ms
I1
Log-domain OTA
VC = nUT ln
Vo
Vim
Minm
Vb
Substituting Eqs. (1), (2), and
Iout
Mout
C
Mp2 I1
M2
Vip
Vim
M1
I1
Vim
M3
M4
Vo
Vo
Vip
+ Vb
(5)
dIout (6) dt is obtained where Ω = I0 /(nUT C) and Iin = Iinp − Iinm . It is known that the proposed circuit of Fig. 1(d) is an ELTI integrator and does not require an SVC current. Furthermore, the common-mode voltages of Vip and Vim , which are input voltages of the log-domain OTA, can be kept constant by appropriately biasing Minp , Minm , and MS with Ig . Therefore, the proposed integrator in Fig. 1(d) can operate at low supply voltage.
(a)
I0
ΩIin =
VDD Mp1
IS Ig
into Eq. (4), a differential equation
Vc
M0
(b)
Ig
Iinp
Ig
Iinm
Ig
SVC current : Vip
Minp
nUTC
I1
I g’ Ig Vo
Vim
Minm
Mout
C
Vb Ms
III. F ILTER I MPLEMENTATION
Iout
Vc
M0
(c)
Iinp
Ig
Ig
Ig
Iout Vip
Minp Iinm Vb
I1
Vim
Minm
C
Ms M0
Vo
Mout
Vc (d)
Fig. 1. Syllabic companding log domain integrators; (a) the DAB-based integrator [2], (b) the log-domain operational transconductance amplifier (OTA), (c) the modified version of (a) for low voltage operation [3], and (d) proposed schema with no state variable correction (SVC) circuit.
expansion function of Vo at Mout can be expressed as Iinp + Vb Vip = nUT ln 1 + Ig and Vo = nUT ln
Ioutp Ig
+ Vb ,
(1)
(2)
respectively. An output current I1 of the log-domain OTA in Fig. 1(b) is given as V −Vo Vim −Vo ip nUT nUT I1 = I 0 e −e . (3) Hence, Kirchhoff’s current law at the gate terminal of Mout gives V −Vo Vim −Vo ip d nUT nUT −e = C (Vo − VC ) . (4) I0 e dt
The modification for simple low-voltage log-domain integrators is applicable to the log-domain filters. As an example of this proposed modification, the third-order Butterworth lowpass filter with a 100-kHz cutoff frequency is designed. In this example, a pseudo differential form of log-domain filter cores is employed to eliminate an influence of Ig biasing Minp and Minm [2]. A half pseudo differential log-domain filter core is synthesized in the log domain by leap frog simulation as shown in Fig. 2(b) [4]. The bottom terminals of the capacitors C1 , C2 , and C3 are connected with the source terminal of Ms to keep ELTI relation between Iin and Iout as expressed in the previous section. Letting all bias current I1 , I2 , and I3 be 1.0 µA, the capacitances are set as C1 = C3 = 50 pF and C2 = 100 pF for the desired cutoff frequency. All aspect ratios (width/length) of Minp , Minm , Moutp , Moutm and MS are set as 384 µm/0.42 µm, and that of M0 is as 300 µm/0.18 µm. This filter is designed using a 0.18-µm CMOS process and a 0.6-V supply voltage VDD . A control circuit in Fig. 2(a) generates Ig which determines dynamic range of the filter and must be designed for a wide dynamic range. A control circuit shown in Fig. 3 is used here [3] and Ig takes any one of three discrete values Iref 1 , Iref 2 , or Iref 3 at a time by switching S1 to S3 according to an amplitude of input signal [5]. If Iref 1 < Iref 2 < Iref 3 is satisfied, for example, Ig is set to Iref i (i = 1, 2, or 3) when the amplitude |Iin | of an input current is in the region as Iref (i−1) < |Iin | ≤ Iref i where Iref 0 = 0. A circuit controlling the switches can be implemented by use of a peak detector, several comparators, and some reference current sources as described in Ref. [3]. The number of current sources in the control circuit is not limited to only three and this circuit can be easily extended according to a filter specification. A resistor RL and a capacitor CL compose a simple low-pass filter to avoid large disturbance at the input stage comprised of Minp , Minm , and MS . Here those values are chosen as RL = 100 kΩ and CL = 50 pF. The number of current sources and their values are determined as follows. Figure 4 shows simulation results of
2245
Control Circuit
Ig
Ig Iinp
Ig Vinp
Minp
Iinm Vb
Moutm
Ms
VC
M0
(a)
Mp2
I1
Mp3
M2
2
M4 Mf
M1
Ioutm
Moutp
Voutm
VDD
Vinp
Iout
Ioutp
Voutp
Vinm
Minm
Mp1
VDD
Pseudo Differential Log-Domain Filter Core
Mp4
I2
Mp5
M5
M7
M3
M8
M6
Ms1
Voutp
M9
Ms2
C1
Mp6
I3
Ms3
C2
C3
VC (b)
Fig. 2. The overall third-order Butterworth syllabic-companding log domain filter; (a) the proposed schema with no state variable correction (SVC) circuit, and (b) the third-order Butterworth log-domain filter core.
VDD
Ig=4uA
Ig=400nA
S1
I ref 2
S2
I ref 3
0
S3
gain [dB]
I ref 1
Ig
RL CL Fig. 3.
Ig=50uA
20 -20 -40
6 4 2 0
-60 -80
100k
-100 -120
Control circuit.
1k
10k
100k
1M
10M
frequency [Hz]
Fig. 5. Ig=400nA
70
Ig=3.2uA
Frequency Responses in case for each Ig .
Ig=51.2uA
SNDR [dB]
60 50 40
IV. S IMULATION R ESULTS
SNDRSpec.
30 20
DR = 60 dB
10 0
1n
10n
100n
1u
10u
100u
input curret [A]
Fig. 4. Signal to noise plus distortion ratios (SNDRs) in multiples from 100-nA to 208-µA Ig .
signal to noise plus distortion ratios (SNDRs) corresponding to various Ig from 100 nA to 208.4 µA in multiples of two where a distortion is calculated by summing from the 2nd to the 9th harmonic components of output current Iout for a 100-kHz sinusoidal input current and noise means the RMS output current noise integrated over the bandwidth of 400 kHz during one period. Considering a specification of a 60-dB input range for over 40-dB SNDR as an example, the bias currents of Fig. 3 are chosen as Iref 1 = 400 nA, Iref 2 = 4.0 µA, and Iref 3 = 50 µA. Their current values are determined for a current consumption to be as small as possible.
The proposed syllabic-companding log domain filter is simulated to confirm the characteristics. The parameters determined in the previous section are used in this simulation. First of all, frequency response of the proposed filter is verified. Figure 5 shows the simulation results where a control circuit used in Fig. 2(a) is replaced with a 3-output constant current source of fig. 3. The filter has a 96.5-kHz cutoff frequency each Ig as seen from Fig. 5. Figure 6(a) shows the fundamental component of Iout , total harmonic distortion, and an RMS output current noise from DC to 400 kHz during one period, versus amplitude of a 100kHz sinusoidal input current Iin . In Fig. 6(a), the fundamental output current increases in proportion to an input current, while output noise does stepwise. Figure 6(b) shows an SNDR characteristic obtained from results of Fig. 6(a). As seen from Fig. 6(b) the proposed filter can satisfy the specification of a 60-dB input range over 40-dB SNDR. Figure 7(a) shows a 100-kHz sinusoidal input current Iin with an envelope changed, and a control current Ig . In Fig. 7(b) waveform of the log-compressed voltage Vinp of the proposed
2246
50u 40u Iout
current [A]
RMS output current [A]
100u 10u 1u 100n 10n 1n 100p 10p 1p
noise : DC - 400 kHz harmonics : 2nd - 9th 10n
100n 1u input curret [A] (a)
Ig
30u 20u Iin
10u 0 -10u
10u
0
100u 200u 300u 400u 500u 600u 700u 800u time [sec] (a)
70
420m 410m
50 40
SNDRSpec. DR = 60 dB
30 20
voltage [V]
SNDR [dB]
60
10n
100n 1u input curret [A] (b)
380m
360m
Vinp
current [A]
FILTER CHARACTERISTICS .
3rd -order Butterworth 0.18-µm standard CMOS 96.5 kHz 0.6 V 100 dB 400 nA 4 µA 50 µA 45 µW 59.6 µW 198 µW 912 nA 9.6 µA 88.4 µA 351 pArms 2.19 nArms 19.4 nArms
0
100u 200u 300u 400u 500u 600u 700u 800u time [sec] (b)
TABLE I S UMMARY OF THE
390m
370m
10u
Fig. 6. Dynamic Range characteristics at a 100-kHz sinusoidal input current; (a) the rms fundamental Iout , the total harmonic distortion components in rms, and the rms output current noise for one period, and (b) Signal to noise plus distortion ratio (SNDR) versus Iin .
Order and type Technology Cutoff frequency Supply voltage Dynamic range Control current Ig Power Dissipation Input-referred IP3 Output current noise
400m
10u 8u 6u 4u 2u 0 -2u -4u -6u -8u -10u
Iout
0
100u 200u 300u 400u 500u 600u 700u 800u time [sec] (c)
Fig. 7. Transient responses; (a) Iin and Ig , (b) log-compressed voltage Vinp , and (c) the output current Iout .
filter is depicted. It is verified that the bias voltage of Vinp keeps almost constant. Figure 7(c) shows the output current Iout of the proposed filter. Table I shows summary of the filter characteristics. The proposed filter operates well for low voltage such as a 0.6-V VDD . In addition, when Ig changes from 400 nA to 50 µA, the current consumption is observed as 75 to 330 µA which corresponds to 45- to 198-µW power consumption. Finally, the proposed filter has 100-dB dynamic range, which is calculated from the ratio of the input current over 40-dB SNDR to minimum noise floor. V. C ONCLUSION A low-voltage syllabic-companding log domain filter with no state variable correction circuits has been proposed. The proposed filter is easily simplified by varying a terminal voltage of capacitors adaptively and still has wide dynamic range even at a low supply voltage. Simulation results show 60-dB input range and an over 40-dB signal to noise plus distortion ratio at a power supply of 0.6 V in a 0.18-µm CMOS process. Future works are fabrication and measurement.
ACKNOWLEDGMENT This study was supported by the 21st Century COE Program “Intelligent Human Sensing” from the ministry of Education, Culture, Sports Science and Technology of Japan and VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc. R EFERENCES [1] Y.Tsividis, “Externally linear time-invariant systems and their applications to companding signal processors, ” IEEE Trans. Circuits and Systems II, vol.44, pp.65-85, Feb. 1997. [2] N.Krishnapura and Y.Tsividis, “Noise and power reduction in filters through the use of adjustable biasing, ” IEEE J. Solid-State Circuits, vol.36, pp.1912-1920, Dec. 2001. [3] I. Akita, K. Wada, and Y. Tadokoro, “Low-voltage CMOS syllabiccompanding log domain filter, ” in Proc. 2006 IEEE Int. Symp. Circuits and Systems, pp.3337-3340, 2006. [4] D. Python and C. C. Enz, “A micropower class-AB log-domain filter for DECT applications, ” IEEE J. Solid-State Circuits, vol.36, pp.1067-1075, July 2001. [5] Y. Palaskas, Y. Tsividis, V. Prodanov, and V. Boccuzzi, “A “divide and conquer” technique for implementing wide dynamic range continuoustime filters, ” IEEE J. Solid-State Circuits, vol.39, pp.297-307, Feb. 2004.
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