Small-Signal Analysis and Control Design of Asymmetrical Half-Bridge ...
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 2, APRIL 2006
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Small-Signal Analysis and Control Design of Asymmetrical Half-Bridge DC–DC Converters Byungcho Choi, Member, IEEE, Wonseok Lim, Sanghyun Bang, and Seungwon Choi, Member, IEEE
Abstract—This paper presents the small-signal modeling, dynamic analysis, and control design of the asymmetrical half-bridge dc–dc converter that employs a clamp capacitor and a magnetizing inductor to accommodate pulsewidth-modulated operation with asymmetrical duty ratios. The circuit averaging technique is applied to extract the small-signal dynamics of the power stage, and a graphical loop-gain method is used to design the feedback compensation and analyze the closed-loop performance of the converter. The distinctive power-stage dynamics of the converter are addressed and design guidelines for voltage feedback compensation are established. The results of the control design and closed-loop analysis are substantiated by experiments using an experimental converter. Index Terms—Asymmetrical half-bridge (ASHB) converter, feedback compensation design, small-signal modeling and dynamic analysis, voltage-mode control.
I. I NTRODUCTION
W
HEN BRIDGE-TYPE pulsewidth-modulated (PWM) dc–dc converters are operated with asymmetrical duty ratios, zero-voltage-switching (ZVS) conditions can readily be provided for active switches without any penalty of an increased conduction loss [1]–[3]. As an example of such converters, Fig. 1 shows an asymmetrical half-bridge (ASHB) dc–dc converter combined with a standard voltage-mode PWM feedback controller. In addition to the circuit components usually found in conventional half-bridge dc–dc converters, the power stage of an ASHB dc–dc converter utilizes a clamp capacitor of capacitance Cc and a magnetizing inductor Lm to accommodate a PWM operation with asymmetrical duty ratios; for an ASHB converter, the magnetizing inductor is designed to be significantly smaller than that of a conventional halfbridge dc–dc converter. While the power-stage operation and dc characteristics of ASHB converters have already been well documented in [2] and [3], the compensation design and closedloop analysis of a closed-loop controlled ASHB converter are Manuscript received November 28, 2003; revised December 6, 2004. Abstract published on the Internet January 25, 2006. This work was supported in part by the Hanyang University—Software Defined Radio Research Center, Hanyang University, Seoul, Korea, under the Information Technology Research Center Program of the Ministry of Information and Communication, Korea, and in part by the Basic Research Program of the Korea Science and Engineering Foundation under Grant R12-2002-055-02001-0. B. Choi and W. Lim are with the School of Electrical Engineering and Computer Science, Kyungpook National University, Taegu 702-701, Korea (e-mail: [email protected]). S. Bang was with the School of Electrical Engineering and Computer Science, Kyungpook National University. He is now with LG Electronics Inc., Gumi, Korea. S. Choi is with the School of Electrical and Computer Engineering, Hanyang University, Seoul 133-791, Korea. Digital Object Identifier 10.1109/TIE.2006.870715
Fig. 1. ASHB dc–dc converter combined with a voltage-mode PWM feedback controller. The power stage utilizes a clamp capacitor of capacitance Cc and magnetizing inductor of inductance Lm to accommodate a PWM operation with asymmetrical duty ratios. The feedback controller employs a standard voltage-mode control.
the subject of current researches, because the small-signal dynamics of ASHB converters are markedly different from those of conventional half-bridge converters due to the presence of the clamp capacitor and the magnetizing inductor. Several previous publications [4]–[6] have analyzed the small-signal dynamics of asymmetrically driven bridge-type PWM converters, thereby establishing the theoretical background needed for the control design and closed-loop analysis of such converters. However, the results of these research efforts have not been fully explored to a stage of providing practical assistance to engineers seeking a systematic method to design the control loop and evaluate the closed-loop performance of the converter. Although open-loop power-stage dynamics are well documented in [4] and [6], limited information is available [5] on the control design and closed-loop analysis of asymmetrically driven bridge-type dc–dc converters. Accordingly, the purpose of this paper is to present the theoretical and practical details involved in the dynamic modeling, control design, and closed-loop analysis of ASHB dc–dc converters. Based on the circuit averaging technique, a small-signal model is derived for ASHB converters and used to investigate the power-stage dynamics. This paper also shows that the duty ratio–output transfer function is critically influenced by the operating conditions of ASHB converters and becomes null as the duty ratio approaches the critical value of D = 0.5. A graphical loop-gain method is adapted to design the feedback compensation and analyze the closed-loop performance
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 2, APRIL 2006
where · indicates the average value of the circuit variables specified in Fig. 2(a) and d denotes the duty ratio of the MOSFET switch Q1 . To develop an average model predicting the time-averaged dynamics of an ASHB converter, Fig. 2(a) can be converted into Fig. 2(b) by: 1) removing the ideal transformer and supplementing dependent voltage–current sources that are programmed with the circuit equations of (1) and (2); 2) replacing the complementary-driven switch pair with a pair of voltage and current sources [7] of which the branch current and node voltage are forced to track the average values of the corresponding waveforms in the original complementary-driven switch pair.
Fig. 2. Models of ASHB converter. (a) Modified model. (b) Average model. (c) Small-signal model. The average model predicts the time-averaged behavior of the converter, while the small-signal model describes the frequency-domain characteristics.
of the converter. Design guidelines are established for a voltage feedback compensation that can provide good closed-loop performance in the presence of the peculiar power-stage dynamics of ASHB converters. The results of the control design and closed-loop analysis are illustrated by computer simulations and substantiated by experiments using an experimental ASHB converter that delivers a 5 V/10 A output from a 40–55 V input source. Although this paper specifically focuses on an ASHB dc–dc converter, the general results can still be readily extended to include other asymmetrically driven bridge-type PWM dc–dc converters. II. P OWER -S TAGE M ODELING AND O PEN -L OOP A NALYSIS
Although the notations · are omitted to simplify the presentation, all circuit variables in Fig. 2(b) represent the timeaveraged values of the respective waveforms. Fig. 2(b) also includes the parasitic resistances of the major circuit components. The primary winding resistance of the transformer is absorbed as a part of the equivalent series resistance (esr) of the clamp capacitor with capacitance Cc , and the secondary winding resistance is merged into the esr of the output inductor. The average model can be used to investigate the timedomain dynamics of the converter, as will be demonstrated in Section III. A small-signal model can now be obtained from Fig. 2(b) by linearizing the dependent sources under the small-signal assumption. Fig. 2(c) shows a small-signal model of the power stage in which various small-signal sources are given by ˆisw = Dˆim + IM + IL dˆ + D ˆiL n n
(3)
vs + VS dˆ vˆsw = Dˆ
(4)
ˆipri = (2D − 1) ˆiL + 2IL dˆ n n
(5)
vˆrec =
(1 − 2D) D VS − 2VCc ˆ vˆcc + vˆs + d n n n
(6)
Based on the circuit averaging technique, a small-signal model of ASHB converters is obtained. The small-signal transfer functions are then derived from the small-signal model to investigate the power-stage dynamics of the converter.
where “∧ ” signifies the small-signal component of the respective variables.
A. Power-Stage Modeling
B. Duty Ratio–Output Transfer Function
Fig. 2(a) shows a modified circuit diagram of an ASHB converter where two asymmetrically driven MOSFET switches are collectively represented by a complementary-driven switch pair. Based on the operations of ASHB converters [2], [3], the time-averaged expressions for the circuit variables are given by
The application of circuit analysis techniques to Fig. 2(c) yields an expression for the duty ratio–output transfer function. The resulting transfer function can be factored into an approximation
1 (dvS + (1 − 2d)vcc ) n 1 ipri = (2d − 1)iL n
vrec =
(1) (2)
2 s 1+ ωesr 1+ Qn1sωn1 + ωs2 vˆo n1 ≈ Kd Gvd (s) ≡ s s2 s dˆ 1+ 1+ + + Qd1 ωd1
2 ωd1
Qd2 ωd2
s2 2 ωd2
(7)
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TABLE I OPERATING CONDITIONS, CIRCUIT COMPONENTS, AND TRANSFER FUNCTIONS OF THE EXPERIMENTAL ASHB CONVERTER
where ωd2 = Kd =
2(1 − 2D)VS R n(RLf + R)
1 RCf Cf 2 = Lm Cc 1 +
(8)
ωesr =
ωn1
2RCf IL nVS
nVS ω −1 Lm IL + nVS RCc Cc n1 RLf + R = 2 (RCf + R)Cf Lf + Lm (1−2D) 2 n
Qn1 = ωd1
(9)
Qd1 =
(RLf RCf
(10)
(11) (12)
RLf + R ω −1 (13) + RLf R + RCf R)Cf + Lf d1
Qd2 =
Lf + Lm (1−2D) n2 Lf Lm Cc
1 ω −1 RCc Cc d2
2
(14) (15)
with the assumption of Lf /Lm (1 − 2D)2 /n2 . Analytical details about the derivation of (7), together with the justification for the assumption used in the derivation, are given in the Appendix. The factorized expression of the duty ratio–output transfer function reveals the distinctive small-signal dynamics of ASHB converters. 1) Equation (8) indicates that Kd , the dc gain of Gvd (s), is positive for 0 < D < 0.5 and negative for 0.5 < D < 1.0. Since a negative Kd will cause stability problems, the operation of the converter with a duty ratio larger than 0.5 should be avoided. The dc gain Kd is also a nonlinear function of the duty ratio and the input voltage; furthermore, the transfer function becomes null with D = 0.5.
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Fig. 3. Duty ratio–output transfer function with D = 0.25. (a) Magnitude. (b) Phase. The thick lines are the predictions of the factorized transfer function (7), while the thin lines are the experimental data measured with the experimental ASHB converter. The existence of the neighboring double-pole (fd2 = 17.7 kHz) and double-zero (fn1 = 25.0 kHz) pair is apparent.
Detailed discussions on the behavior of Gvd (s) and their impact on the control design, together with experimental verification of analytical predictions, are given later in this section. 2) First quadratic term in the denominator reflects the dynamics of the output filter. The resonant frequency of this term reduces to ωd1 ≈ 1/ Lf Cf when the conditions of Lf /Lm (1 − 2D)2 /n2 , R RCf , and R RLf are met. 3) Second quadratic term in the denominator is a result of the resonance between the magnetizing inductance Lm and the clamp capacitor of capacitance CC . The √ resonant frequency of this term becomes ωd2 ≈ 1/ Lm Cc with the condition Lf /Lm (1 − 2D)2 /n2 . This term causes an additional 180◦ phase delay. 4) Quadratic term in the numerator is also an effect of the magnetizing inductance and clamp capacitor. The resonance frequency of this term becomes ωn1 ≈ (2/Lm Cc ) when√ the condition (2RCf IL /nVS ) 1 is satisfied; the factor 2 in the numerator of ωn1 originates from the results of the power-stage analysis, presented in the Appendix. Accordingly, the relationship ωn1 = √ 2 · ωd2 holds for most practical applications. This term provides a 180◦ phase boost. In order to assess the accuracy of the analysis results, an experimental ASHB converter was built and tested. The operating conditions and circuit components of the experimental converter are given in Table I. Fig. 3 compares the prediction
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 2, APRIL 2006
Fig. 4. Duty ratio–output transfer function with D = 0.75. (a) Magnitude. (b) Phase. The thick lines are the predictions of (7), and the thin lines are the measurements. The negative sign of the transfer function can be clearly seen from the phase curve.
of the factorized expression of (7) with the duty ratio–output transfer function measured with the experimental converter using an HP4194A gain-phase analyzer. The operating conditions of VS = 48 V, VO = 5 V, and R = 0.5 Ω were used for Gvd (s) and all other measurements presented in this paper. The transfer functions show a close correlation, thereby validating the modeling approach. The existence of the neighboring double-pole (fd2 = ωd2 /2π = 17.7 kHz) and double-zero (fn1 = ωn1 /2π = 25.0 kHz) pair is apparent in Fig. 3. The analytic expressions for the duty ratio–output transfer function and all other forthcoming open- and closed-loop transfer functions are also given in Table I. As presented in earlier publications [2], [3] and reconfirmed in a later section of this paper, the dc gain of the ASHB converter can be given by M≡
2D(1 − D)R VO . = VS n(RLf + R)
(16)
Accordingly, there exist two different duty ratios that provide VO = 5.0 V for the experimental converter with VS = 48 V: one is D = 0.25 and the other is D = 0.75. Fig. 3 illustrated the duty ratio–output transfer function of the experimental converter with D = 0.25. Fig. 4 shows the duty ratio–output transfer function of the experimental converter operating with D = 0.75. As predicted in (8), the magnitude is identical to Fig. 3; however, the phase manifests a negative sign for the transfer function. Since this negative gain will destablize the control loop, the duty ratio
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Fig. 5. Duty ratio–output transfer functions at different operating points. The thick lines are the predictions of (7), while the thin lines are the measurements. As the duty ratio approached the singular value of D = 0.5, the magnitude rapidly diminished and difficulties were encountered in measuring the transfer function.
should be limited to 0 < D < 0.5 during both steady-state and transition periods. Fig. 5 shows the theoretical and experimental duty ratio–output transfer functions, evaluated at different operating points as the input voltage is varied between 33.7 V < VS < 55 V. For each of the four different values of VS , the duty ratio needed to produce VO = 5 V is calculated and shown in Fig. 5. As illustrated in Fig. 5, when the input voltage is decreased, the duty ratio increases and the magnitude of the transfer function rapidly diminishes, as predicted in (8). As the duty ratio approached 0.5, difficulties were encountered in measuring the transfer function. This is consistent with the fact that D = 0.5 is a singular point at which the transfer function becomes null and the converter becomes uncontrollable. When the input voltage of the experimental converter is varied within the given specification of 40 V < VS < 55 V, the transfer function does not experience significant changes in magnitude; therefore, the feedback controller designed with VS = 48 V is found to be appropriate for all the operating conditions. On the other hand, for applications in which the input voltage changes significantly, the control loop should be designed with the maximum input voltage to secure stability with a lower input voltage; however, a substantial degradation is expected in the closed-loop performance when the input voltage approaches the lower limit.
Fig. 6. Power-stage transfer functions. (a) Input–output transfer function. (b) Open-loop output impedance. The thick lines are the predictions of (17) and (21), while the thin lines are the measurements. The measured open-loop output impedance shows the influence of the measurement noise at low and high frequencies.
where 2D(1 − D)R n(RLf + R) 2(1 − D) = Lm Cc
Ks =
(18)
ωn2
(19)
Qn2 =
1 ω −1 . RCc Cc n2
(20)
The Ks given in (18) is the dc voltage transfer gain of the converter, which was previously referred to in (16). Similarly, the open-loop output impedance is given by
s s 1 + 1 +
ωesr ωzp vˆo
≈ Kp (21) Zp (s) ≡ ˆio d=ˆ s s2 ˆ vs =0 1+ + 2 Qd1 ωd1
C. Input–Output Transfer Function and Open-Loop Output Impedance
where
By taking the same analysis steps used for Gvd (s), the input–output transfer function can be derived as
Kp =
vˆo
Gvs (s) ≡ vˆs d= ˆ ˆio =0
ωzp =
s s2 1 + + 2 ωesr Qn2 ωn2 ωn2 ≈ Ks 2 s s2 s 1 + Qd1 ωd1 + ω2 1 + Qd2 ωd2 + ωs2 1+
s
d1
ωd1
d2
(17)
RLf R RLf + R RLf Lf +
Lm (1−2D)2 n2
(22) .
(23)
Fig. 6 shows the predictions of (17) and (21) in comparison with the measured transfer functions of the experimental converter. While the input–output transfer functions [Fig. 6(a)] show a close agreement, the open-loop output impedances [Fig. 6(b)]
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Fig. 7. Closed-loop controlled ASHB converter. (a) Small-signal circuit model. (b) Small-signal block diagram representation. The converter employs a standard voltage-mode control. Fm is the modulator gain of the PWM block and Fv (s) represents the transfer function of the voltage feedback compensation.
reveal the influence of the measurement noise at low and high frequencies. III. F EEDBACK C OMPENSATION D ESIGN AND C LOSED -L OOP A NALYSIS Once the power-stage transfer functions are analyzed, the feedback compensation can be designed to obtain good closedloop performance. A graphical loop-gain method [8] is adapted to design the feedback compensation and analyze the closedloop performance of the ASHB converter. A. Feedback Compensation Design and Loop Gain Fig. 7(a) shows a small-signal circuit model of the ASHB converter that employs standard voltage-mode control, while Fig. 7(b) presents a block diagram representation of Fig. 7(a). In Fig. 7, Fm is the modulator gain of the PWM block and Fv (s) represents the transfer function of the voltage feedback compensation. Analytical expressions for all the gain blocks shown in Fig. 7(b) are given in Table I. For the given Gvd (s), a three-pole two-zero compensation is selected for Fv (s) s s 1 + ωzc2 Km 1 + ωzc1 Fv (s) = (24) s s 1 + ωpc2 s 1 + ωpc1
Fig. 8. Loop gain of closed-loop controlled ASHB converter. (a) Asymptotic plots. (b) Loop gain. The thick lines are the predictions of (25), while the thin lines are the measurements. The crossover frequency occurs at fc = ωc /2π = 4.3 kHz with a 60◦ phase margin.
in order to achieve desirable characteristics for the loop gain T (s) = Gvd (s)Fv (s)Fm . Fig. 8(a) shows the asymptotic plots for |Gvd (s)|, |Fv (s)|, and |T (s)|. The compensation parameters for Fv (s) are determined as follows. 1) Two compensation zeros are placed around the first resonant frequency of Gvd (s), the first compensation zero before the resonant frequency and the second zero after the resonant frequency (ωzc1 < ωd1 < ωzc2 ), to compensate for the −180◦ phase delay caused by the resonance. 2) The first compensation pole is placed at the esr zero of Gvd (s), ωpc1 = ωesr = 1/ (Cf RCf ), to nullify the effects of the esr zero. 3) The second compensation pole ωpc2 is added between the esr zero and the second resonant frequency of Gvd (s), ωesr < ωpc2 < ωd2 , to minimize the detrimental effects of the secondary resonance at ωd2 . 4) Finally, the integrator gain Km is adjusted to locate the crossover frequency of the loop gain, ωc in Fig. 8(a),
CHOI et al.: SMALL-SIGNAL ANALYSIS AND CONTROL DESIGN OF HALF-BRIDGE DC–DC CONVERTERS
Fig. 9. Audio susceptibility of closed-loop controlled ASHB converter. (a) Asymptotic plots. (b) Audio susceptibility. The thick line is the prediction of (29), while the thin line is the measurement. The effect of the adjoining doublepole (fd2 = 17.7 kHz) and double-zero (fn2 = 22.0 kHz) pair is evident.
between the second compensation zero and the second compensation pole, ωzc2 < ωc < ωpc2 . This ensures that the loop gain crosses the 0-dB line with a −20 dB/dec slope, thereby securing a sufficient phase margin.
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Fig. 10. Output impedance of closed-loop controlled ASHB converter. (a) Asymptotic plot. (b) Output impedance. The thick line is the prediction of (31), while the thin line is the measurement. The measured output impedance shows the noise at low frequencies and a glitch at high frequencies.
To apply the graphical method [8], the relationship of (26) can be paraphrased as Gvs (s) at frequencies below ω where |T | 1 c Au (s) ≈ T (s) . Gvs (s) at frequencies above ωc where |T | 1 (27)
The equation for the loop gain is then given by T (s) = Kd Km Fm 2 s s 1+ ωzc2 1+ Qn1sωn1 + ωs2 1+ ωzc1 n1 . (25) × 2 s s s2 s 1+ Qd2 ωd2 + ωs2 s 1+ ωpc2 1+ Qd1 ωd1 + ω2 d1
Fig. 9(a) illustrates the method of constructing an asymptotic plot for |Au (s)| based on (27). From Fig. 9(a), the maximum value for audio susceptibility is determined by |Au (s)|max = 20 log
d2
Fig. 8(b) shows the prediction of (25) and the measured loop gain of the experimental converter with the voltage compensation designed as outlined above. The crossover frequency of the loop gain occurs at fc = ωc /2π = 4.3 kHz with a phase margin of 60◦ .
Ks ωzc1 [dB]. Kd Km Fm
(28)
An equation for Au (s) can now be written based on the asymptotic plot and (28) as 2 s 1+ Qn2sωn2 + ωs2 s 1+ ωpc2 n2 Au (s) ≈ KA 2 s s s 1+ ωzc1 1+ ωzc2 1+ ωc 1+ Qd2sωd2 + ωs2 d2
(29)
B. Audio Susceptibility The application of Mason’s gain rule to Fig. 7(b) yields an expression for the audio susceptibility of the closed-loop ASHB converter Au (s) =
vo (s) Gvs (s) . = vs (s) Closed loop 1 + T (s)
(26)
with KA =
Ks . Kd Km Fm
(30)
Fig. 9(b) compares the predictions of (29) with the measured audio susceptibility. The transfer functions show a deviation
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The step load response of the ASHB converter can be analyzed using the output impedance and its relationship to the output voltage [9]. To simplify the step load analysis of the experimental converter, the output impedance is approximated to a first-order function Zapp drawn with a dotted line in Fig. 10(a), by ignoring the poles and zeros appearing before ωc : ωzp , ωzc1 , ωzc2 , and ωpc1 in Fig. 10(a). With this simplification, the following relationships hold for the experimental converter [9] ∆vo (t)max = ∆Istep |Zo (s)|max = ∆Istep |Zo (∞)| tss =
Fig. 11. Step load response of output voltage. (a) Theoretical prediction of averaged model. (b) Experimental result.
at midfrequencies, thereby revealing the limitation of the asymptotic analysis, which does not consider the effects of the phase characteristics of the transfer functions. The effects of the adjoining double-pole (fd2 = ωd2 /2π = 17.7 kHz) and double-zero (fn2 = ωn2 /2π = 22.0 kHz) pair, which are also not included in the asymptotic analysis in Fig. 9(a), are evident in Fig. 9(b). C. Output Impedance and Step Load Response Similar to the case of audio susceptibility, an asymptotic plot for the closed-loop output impedance can be constructed as shown in Fig. 10(a). The output impedance can now be expressed as vo (s) io (s) closed loop s 1 + ωpc1 s 1 + ωszp ≈ KZ s s 1 + ωzc1 1 + ωzc2 1+
(35)
where ∆vo (t)max represents the maximum excursion of the output voltage from its steady-state value, ∆Istep is the magnitude of the step change of the load current, and tss represents the setting time of the transient response. Fig. 11 shows the output voltage of the experimental converter when it experiences a step change from 0.5 to 1.67 Ω in the load resistance ∆Istep = 4 A. The upper waveform is the theoretical prediction of the average model developed for ASHB converters, and the lower waveform is the response of the experimental converter measured with an electric load. The transient responses show a good correlation with the analytical predictions of ∆vo (t)max = 4 A × (0.240.5) Ω = 0.67 V and tss = 3/(2π4.3 × 103 ) = 110 µs. The transient response also reveals a decaying oscillation, reflecting the effects of the glitch in the output impedance. The frequency of the oscillation corresponds to the frequency at which the glitch was observed in the experimental output impedance. IV. C ONCLUSION
Zo (s) ≡
s ωc
(31)
with KZ = (RCf R)
3 ωc
(34)
ωzp ωpc1 . ωzc1 ωzc2 ωc
(32)
The maximum value for the output impedance is given by its high-frequency asymptote |Zo (s)|max = |Zo (∞)| = 20 log(RCf R) [dBΩ].
(33)
Fig. 10(b) compares the prediction of (31) with the measured closed-loop output impedance. In addition to the deviation at midfrequencies, the measured output impedance also reveals a glitch at high frequencies. The glitch is an influence of the peaking of the loop gain, which was not accounted for in the asymptotic analysis. The experimental output impedance also exhibits the noise at low frequencies.
This paper presented the theoretical and practical details involved in the small-signal analysis, control design, and closed-loop analysis of an ASHB dc–dc converter. The circuit averaging technique was used to study the power-stage dynamics of the ASHB converter. It was shown that the duty ratio–output transfer function is very sensitive to the operating conditions of the converter and becomes null as the duty ratio approaches the critical value of D = 0.5. A graphical loop-gain method was adapted to design the feedback compensation and analyze the closed-loop performance. Design guidelines were established for a voltage feedback compensation that can offer good closed-loop performance in the presence of the peculiar power-stage dynamics of ASHB converters. All the open- and closed-loop transfer functions of the ASHB converter were derived in an analytical form and are summarized in Table I. The predicted transfer functions revealed a good correlation with the experimental data. The general results of this paper can also be adapted to other asymmetrically driven bridge-type PWM converters to improve their control design and analyze their closedloop performance.
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2
Lf + Cf (RLf RCf + RLf R + RCf R) + Lm (1−2D) n2 RLf + R 2 ) + RCc Cc Cf (RLf RCf + RLf R + RCf R) + Lf + Cc (RCf + R) Lf + Lm (1−2D n2
a1 = RCc Cc +
a2 = Cc Lm +
RCc Cc Cf (RCf + R) Lf + a3 = a4 =
Lm (1−2D 2 ) n2
RLf + R
Lm (1−2D)2 n2
(45)
+ Lm Cc (Cf (RLf RCf + RLf R + RCf R) + Lf ) (46)
RLf + R Lf Cf Lm Cc (RCf + R) RLf + R
(47)
A PPENDIX D ERIVATION OF D UTY R ATIO –O UTPUT T RANSFER F UNCTION From the small-signal model in Fig. 2(c) and the accompanying (3)–(6), a set of circuit equations can be derived as RCf + sC1 f R vˆo = vˆrec (36) RLf + sLf + RCf + sC1 f R (1 − 2D) VS − 2VCc ˆ vˆcc + d n n vˆsw − vˆcc ˆ = + ipri sLm
vˆrec = vˆcc RCc + sC1 c
(44)
vˆsw = VS dˆ ˆipri = (2D − 1) ˆiL + 2IL dˆ n n ˆiL = vˆrec − vˆo . RLf + sLf
(37) (38) (39) (40) (41)
A simultaneous solution of (36)–(41) with the incorporation of VCc = DVS yields 2 s 1 + ωesr 1 + Qn sωn + ωs2 vˆo n1 1 1 (42) = Kd ∆(s) dˆ
(1 − 2D)2 /n2 . While the condition Lf /Lm (1 − 2D)2 /n2 can easily be met for most practical applications, the factorized expression of the duty ratio–output transfer function retains a good accuracy, even though this assumption is not strictly satisfied. R EFERENCES [1] T. Ninomiya, N. Matsumoto, M. Nakahara, and K. Harada, “Static and dynamic analysis of ZVS half-bridge converter with PWM control,” in Proc. IEEE Power Electron. Specialists Conf., 1991, pp. 230–237. [2] P. Imbertson and N. Mohan, “Asymmetrical duty cycle permits zero switching loss in PWM circuits with no conduction loss penalty,” IEEE Trans. Ind. Appl., vol. 29, no. 1, pp. 121–125, Jan./Feb. 1993. [3] R. Oruganti, P. C. Heng, J. T. K. Guan, and L. A. Choy, “Soft-switched DC/DC converter with PWM control,” IEEE Trans. Power Electron., vol. 13, no. 1, pp. 102–114, Jan. 1998. [4] J. Sebastian, J. A. Cobos, D. Garcia, and J. Uceda, “Small-signal modeling of the half-bridge complementary-control dc-to-dc converter,” in Proc. IEEE CIEP, Oct. 1995, pp. 44–50. [5] E. F. Linear, J. Sebastian, M. A. Perez Garcia, J. Diaz, and A. Fontan, “Closing the feedback loop in the half-bridge complementary-control dc-to-dc converter,” in Proc. IEEE Appl. Power Electron. Conf., Feb. 1997, pp. 977–982. [6] S. Korotkov, V. Meleshin, A. Nemchinov, and S. Fraidlin, “Small-signal modeling of soft-switched asymmetrical half-bridge dc/dc converter,” in Proc. IEEE Applied Power Electronics Conf., Mar. 1995, pp. 707–711. [7] E. Dijk, H. Spruijt, D. M. Osullivan, and J. B. Klaassens, “PWM-switch modeling of DC-DC Converters,” IEEE Trans. Power Electron., vol. 10, no. 6, pp. 659–665, Nov. 1995. [8] R. D. Middlebrook, “Modeling current-programmed buck and boost regulators,” IEEE Trans. Power Electron., vol. 4, no. 1, pp. 36–52, Oct. 1989. [9] B. Choi, “Step load response of a current mode controlled dc-to-dc converter,” IEEE Trans. Aerosp. Electron. Syst., vol. 33, no. 4, pp. 1115–1121, Oct. 1997.
with ∆(s) = 1 + a1 s + a2 s2 + a3 s3 + a4 s4
(43)
where a1 , a2 , a3 , and a4 are as shown in (44)–(47), found at the top of the page. To show the equivalence of (42) to (7), the following relationship: s s s2 s2 ∆(s) ≈ 1 + 1+ + 2 + 2 Qd1 ωd1 ωd1 Qd2 ωd2 ωd2 (48) can now be verified by expanding the right-hand side of (48) and comparing the resulting coefficients with ak s (k = 1, 2, 3, 4) given by (44)–(47) under the condition of Lf /Lm
Byungcho Choi (S’90–M’91) received the B.S. degree in electronics from Hanyang University, Seoul, Korea, in 1980, the M.S. and the Ph.D. degrees in electrical engineering from Virginia Polytechnic Institute and State University, Blacksburg, in 1988, and 1992, respectively. From 1992 to 1993, he was a Research Scientist at the Bradley Department of Electrical Engineering, Virginia Polytechnic Institute and State University. From 1994 to 1995, he served as a Team Leader of the Power Electronics Systems Team, Samsung Electronics Company. In 1996, he joined the School of Electrical Engineering and Computer Science, Kyungpook National University, Taegu, Korea, where he is currently an Associate Professor. His research interest includes modeling and design optimization of high-frequency power converters for portable electronics, computer power systems, and distributed power systems.
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Wonseok Lim received the B.S. and M.S. degrees in electronics engineering from Kyungpook National University, Taegu, Korea, in 1999 and 2001, respectively. He is currently working toward the Ph.D. degree at Kyungpook National University. His research interest includes modeling, analysis, and control of board-mount dc–dc power converters for telecommunication applications.
Sanghyun Bang received the B.S. degree from Taegu University, Taegu, Korea, in 2001 and the M.S. degree from Kyungpook National University, Taegu, in 2003, all in electronics engineering. He is currently with LG Electronics, Gumi, Korea, where he is working on the design, fabrication, and testing of high-efficiency drive circuits for plasma display panel application systems.
Seungwon Choi (M’91) received the B.S. degree in electronics engineering from Hanyang University, Seoul, Korea, in 1980, the M.S. degree in electronics engineering from Seoul National University, Seoul Korea, in 1982, and the M.S. degree in computer engineering and the Ph.D. degree in electrical engineering from Syracuse University, Syracuse, NY, in 1985 and 1988, respectively. From 1988 to 1989, he was with the Department of Electrical and Computer Engineering, Syracuse University, as an Assistant Professor. In 1992, he joined Hanyang University as an Assistant Professor. He is currently a Professor in the School of Electrical and Computer Engineering. His research interests include digital communications and adaptive signal processing with a recent focus on the real-time implementation of the smart antenna systems for 3G mobile communication systems.
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Small-Signal Analysis and Control Design of Asymmetrical Half-Bridge DC–DC Converters Byungcho Choi, Member, IEEE, Wonseok Lim, Sanghyun Bang, and Seungwon Choi, Member, IEEE
Abstract—This paper presents the small-signal modeling, dynamic analysis, and control design of the asymmetrical half-bridge dc–dc converter that employs a clamp capacitor and a magnetizing inductor to accommodate pulsewidth-modulated operation with asymmetrical duty ratios. The circuit averaging technique is applied to extract the small-signal dynamics of the power stage, and a graphical loop-gain method is used to design the feedback compensation and analyze the closed-loop performance of the converter. The distinctive power-stage dynamics of the converter are addressed and design guidelines for voltage feedback compensation are established. The results of the control design and closed-loop analysis are substantiated by experiments using an experimental converter. Index Terms—Asymmetrical half-bridge (ASHB) converter, feedback compensation design, small-signal modeling and dynamic analysis, voltage-mode control.
I. I NTRODUCTION
W
HEN BRIDGE-TYPE pulsewidth-modulated (PWM) dc–dc converters are operated with asymmetrical duty ratios, zero-voltage-switching (ZVS) conditions can readily be provided for active switches without any penalty of an increased conduction loss [1]–[3]. As an example of such converters, Fig. 1 shows an asymmetrical half-bridge (ASHB) dc–dc converter combined with a standard voltage-mode PWM feedback controller. In addition to the circuit components usually found in conventional half-bridge dc–dc converters, the power stage of an ASHB dc–dc converter utilizes a clamp capacitor of capacitance Cc and a magnetizing inductor Lm to accommodate a PWM operation with asymmetrical duty ratios; for an ASHB converter, the magnetizing inductor is designed to be significantly smaller than that of a conventional halfbridge dc–dc converter. While the power-stage operation and dc characteristics of ASHB converters have already been well documented in [2] and [3], the compensation design and closedloop analysis of a closed-loop controlled ASHB converter are Manuscript received November 28, 2003; revised December 6, 2004. Abstract published on the Internet January 25, 2006. This work was supported in part by the Hanyang University—Software Defined Radio Research Center, Hanyang University, Seoul, Korea, under the Information Technology Research Center Program of the Ministry of Information and Communication, Korea, and in part by the Basic Research Program of the Korea Science and Engineering Foundation under Grant R12-2002-055-02001-0. B. Choi and W. Lim are with the School of Electrical Engineering and Computer Science, Kyungpook National University, Taegu 702-701, Korea (e-mail: [email protected]). S. Bang was with the School of Electrical Engineering and Computer Science, Kyungpook National University. He is now with LG Electronics Inc., Gumi, Korea. S. Choi is with the School of Electrical and Computer Engineering, Hanyang University, Seoul 133-791, Korea. Digital Object Identifier 10.1109/TIE.2006.870715
Fig. 1. ASHB dc–dc converter combined with a voltage-mode PWM feedback controller. The power stage utilizes a clamp capacitor of capacitance Cc and magnetizing inductor of inductance Lm to accommodate a PWM operation with asymmetrical duty ratios. The feedback controller employs a standard voltage-mode control.
the subject of current researches, because the small-signal dynamics of ASHB converters are markedly different from those of conventional half-bridge converters due to the presence of the clamp capacitor and the magnetizing inductor. Several previous publications [4]–[6] have analyzed the small-signal dynamics of asymmetrically driven bridge-type PWM converters, thereby establishing the theoretical background needed for the control design and closed-loop analysis of such converters. However, the results of these research efforts have not been fully explored to a stage of providing practical assistance to engineers seeking a systematic method to design the control loop and evaluate the closed-loop performance of the converter. Although open-loop power-stage dynamics are well documented in [4] and [6], limited information is available [5] on the control design and closed-loop analysis of asymmetrically driven bridge-type dc–dc converters. Accordingly, the purpose of this paper is to present the theoretical and practical details involved in the dynamic modeling, control design, and closed-loop analysis of ASHB dc–dc converters. Based on the circuit averaging technique, a small-signal model is derived for ASHB converters and used to investigate the power-stage dynamics. This paper also shows that the duty ratio–output transfer function is critically influenced by the operating conditions of ASHB converters and becomes null as the duty ratio approaches the critical value of D = 0.5. A graphical loop-gain method is adapted to design the feedback compensation and analyze the closed-loop performance
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where · indicates the average value of the circuit variables specified in Fig. 2(a) and d denotes the duty ratio of the MOSFET switch Q1 . To develop an average model predicting the time-averaged dynamics of an ASHB converter, Fig. 2(a) can be converted into Fig. 2(b) by: 1) removing the ideal transformer and supplementing dependent voltage–current sources that are programmed with the circuit equations of (1) and (2); 2) replacing the complementary-driven switch pair with a pair of voltage and current sources [7] of which the branch current and node voltage are forced to track the average values of the corresponding waveforms in the original complementary-driven switch pair.
Fig. 2. Models of ASHB converter. (a) Modified model. (b) Average model. (c) Small-signal model. The average model predicts the time-averaged behavior of the converter, while the small-signal model describes the frequency-domain characteristics.
of the converter. Design guidelines are established for a voltage feedback compensation that can provide good closed-loop performance in the presence of the peculiar power-stage dynamics of ASHB converters. The results of the control design and closed-loop analysis are illustrated by computer simulations and substantiated by experiments using an experimental ASHB converter that delivers a 5 V/10 A output from a 40–55 V input source. Although this paper specifically focuses on an ASHB dc–dc converter, the general results can still be readily extended to include other asymmetrically driven bridge-type PWM dc–dc converters. II. P OWER -S TAGE M ODELING AND O PEN -L OOP A NALYSIS
Although the notations · are omitted to simplify the presentation, all circuit variables in Fig. 2(b) represent the timeaveraged values of the respective waveforms. Fig. 2(b) also includes the parasitic resistances of the major circuit components. The primary winding resistance of the transformer is absorbed as a part of the equivalent series resistance (esr) of the clamp capacitor with capacitance Cc , and the secondary winding resistance is merged into the esr of the output inductor. The average model can be used to investigate the timedomain dynamics of the converter, as will be demonstrated in Section III. A small-signal model can now be obtained from Fig. 2(b) by linearizing the dependent sources under the small-signal assumption. Fig. 2(c) shows a small-signal model of the power stage in which various small-signal sources are given by ˆisw = Dˆim + IM + IL dˆ + D ˆiL n n
(3)
vs + VS dˆ vˆsw = Dˆ
(4)
ˆipri = (2D − 1) ˆiL + 2IL dˆ n n
(5)
vˆrec =
(1 − 2D) D VS − 2VCc ˆ vˆcc + vˆs + d n n n
(6)
Based on the circuit averaging technique, a small-signal model of ASHB converters is obtained. The small-signal transfer functions are then derived from the small-signal model to investigate the power-stage dynamics of the converter.
where “∧ ” signifies the small-signal component of the respective variables.
A. Power-Stage Modeling
B. Duty Ratio–Output Transfer Function
Fig. 2(a) shows a modified circuit diagram of an ASHB converter where two asymmetrically driven MOSFET switches are collectively represented by a complementary-driven switch pair. Based on the operations of ASHB converters [2], [3], the time-averaged expressions for the circuit variables are given by
The application of circuit analysis techniques to Fig. 2(c) yields an expression for the duty ratio–output transfer function. The resulting transfer function can be factored into an approximation
1 (dvS + (1 − 2d)vcc ) n 1 ipri = (2d − 1)iL n
vrec =
(1) (2)
2 s 1+ ωesr 1+ Qn1sωn1 + ωs2 vˆo n1 ≈ Kd Gvd (s) ≡ s s2 s dˆ 1+ 1+ + + Qd1 ωd1
2 ωd1
Qd2 ωd2
s2 2 ωd2
(7)
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TABLE I OPERATING CONDITIONS, CIRCUIT COMPONENTS, AND TRANSFER FUNCTIONS OF THE EXPERIMENTAL ASHB CONVERTER
where ωd2 = Kd =
2(1 − 2D)VS R n(RLf + R)
1 RCf Cf 2 = Lm Cc 1 +
(8)
ωesr =
ωn1
2RCf IL nVS
nVS ω −1 Lm IL + nVS RCc Cc n1 RLf + R = 2 (RCf + R)Cf Lf + Lm (1−2D) 2 n
Qn1 = ωd1
(9)
Qd1 =
(RLf RCf
(10)
(11) (12)
RLf + R ω −1 (13) + RLf R + RCf R)Cf + Lf d1
Qd2 =
Lf + Lm (1−2D) n2 Lf Lm Cc
1 ω −1 RCc Cc d2
2
(14) (15)
with the assumption of Lf /Lm (1 − 2D)2 /n2 . Analytical details about the derivation of (7), together with the justification for the assumption used in the derivation, are given in the Appendix. The factorized expression of the duty ratio–output transfer function reveals the distinctive small-signal dynamics of ASHB converters. 1) Equation (8) indicates that Kd , the dc gain of Gvd (s), is positive for 0 < D < 0.5 and negative for 0.5 < D < 1.0. Since a negative Kd will cause stability problems, the operation of the converter with a duty ratio larger than 0.5 should be avoided. The dc gain Kd is also a nonlinear function of the duty ratio and the input voltage; furthermore, the transfer function becomes null with D = 0.5.
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Fig. 3. Duty ratio–output transfer function with D = 0.25. (a) Magnitude. (b) Phase. The thick lines are the predictions of the factorized transfer function (7), while the thin lines are the experimental data measured with the experimental ASHB converter. The existence of the neighboring double-pole (fd2 = 17.7 kHz) and double-zero (fn1 = 25.0 kHz) pair is apparent.
Detailed discussions on the behavior of Gvd (s) and their impact on the control design, together with experimental verification of analytical predictions, are given later in this section. 2) First quadratic term in the denominator reflects the dynamics of the output filter. The resonant frequency of this term reduces to ωd1 ≈ 1/ Lf Cf when the conditions of Lf /Lm (1 − 2D)2 /n2 , R RCf , and R RLf are met. 3) Second quadratic term in the denominator is a result of the resonance between the magnetizing inductance Lm and the clamp capacitor of capacitance CC . The √ resonant frequency of this term becomes ωd2 ≈ 1/ Lm Cc with the condition Lf /Lm (1 − 2D)2 /n2 . This term causes an additional 180◦ phase delay. 4) Quadratic term in the numerator is also an effect of the magnetizing inductance and clamp capacitor. The resonance frequency of this term becomes ωn1 ≈ (2/Lm Cc ) when√ the condition (2RCf IL /nVS ) 1 is satisfied; the factor 2 in the numerator of ωn1 originates from the results of the power-stage analysis, presented in the Appendix. Accordingly, the relationship ωn1 = √ 2 · ωd2 holds for most practical applications. This term provides a 180◦ phase boost. In order to assess the accuracy of the analysis results, an experimental ASHB converter was built and tested. The operating conditions and circuit components of the experimental converter are given in Table I. Fig. 3 compares the prediction
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Fig. 4. Duty ratio–output transfer function with D = 0.75. (a) Magnitude. (b) Phase. The thick lines are the predictions of (7), and the thin lines are the measurements. The negative sign of the transfer function can be clearly seen from the phase curve.
of the factorized expression of (7) with the duty ratio–output transfer function measured with the experimental converter using an HP4194A gain-phase analyzer. The operating conditions of VS = 48 V, VO = 5 V, and R = 0.5 Ω were used for Gvd (s) and all other measurements presented in this paper. The transfer functions show a close correlation, thereby validating the modeling approach. The existence of the neighboring double-pole (fd2 = ωd2 /2π = 17.7 kHz) and double-zero (fn1 = ωn1 /2π = 25.0 kHz) pair is apparent in Fig. 3. The analytic expressions for the duty ratio–output transfer function and all other forthcoming open- and closed-loop transfer functions are also given in Table I. As presented in earlier publications [2], [3] and reconfirmed in a later section of this paper, the dc gain of the ASHB converter can be given by M≡
2D(1 − D)R VO . = VS n(RLf + R)
(16)
Accordingly, there exist two different duty ratios that provide VO = 5.0 V for the experimental converter with VS = 48 V: one is D = 0.25 and the other is D = 0.75. Fig. 3 illustrated the duty ratio–output transfer function of the experimental converter with D = 0.25. Fig. 4 shows the duty ratio–output transfer function of the experimental converter operating with D = 0.75. As predicted in (8), the magnitude is identical to Fig. 3; however, the phase manifests a negative sign for the transfer function. Since this negative gain will destablize the control loop, the duty ratio
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Fig. 5. Duty ratio–output transfer functions at different operating points. The thick lines are the predictions of (7), while the thin lines are the measurements. As the duty ratio approached the singular value of D = 0.5, the magnitude rapidly diminished and difficulties were encountered in measuring the transfer function.
should be limited to 0 < D < 0.5 during both steady-state and transition periods. Fig. 5 shows the theoretical and experimental duty ratio–output transfer functions, evaluated at different operating points as the input voltage is varied between 33.7 V < VS < 55 V. For each of the four different values of VS , the duty ratio needed to produce VO = 5 V is calculated and shown in Fig. 5. As illustrated in Fig. 5, when the input voltage is decreased, the duty ratio increases and the magnitude of the transfer function rapidly diminishes, as predicted in (8). As the duty ratio approached 0.5, difficulties were encountered in measuring the transfer function. This is consistent with the fact that D = 0.5 is a singular point at which the transfer function becomes null and the converter becomes uncontrollable. When the input voltage of the experimental converter is varied within the given specification of 40 V < VS < 55 V, the transfer function does not experience significant changes in magnitude; therefore, the feedback controller designed with VS = 48 V is found to be appropriate for all the operating conditions. On the other hand, for applications in which the input voltage changes significantly, the control loop should be designed with the maximum input voltage to secure stability with a lower input voltage; however, a substantial degradation is expected in the closed-loop performance when the input voltage approaches the lower limit.
Fig. 6. Power-stage transfer functions. (a) Input–output transfer function. (b) Open-loop output impedance. The thick lines are the predictions of (17) and (21), while the thin lines are the measurements. The measured open-loop output impedance shows the influence of the measurement noise at low and high frequencies.
where 2D(1 − D)R n(RLf + R) 2(1 − D) = Lm Cc
Ks =
(18)
ωn2
(19)
Qn2 =
1 ω −1 . RCc Cc n2
(20)
The Ks given in (18) is the dc voltage transfer gain of the converter, which was previously referred to in (16). Similarly, the open-loop output impedance is given by
s s 1 + 1 +
ωesr ωzp vˆo
≈ Kp (21) Zp (s) ≡ ˆio d=ˆ s s2 ˆ vs =0 1+ + 2 Qd1 ωd1
C. Input–Output Transfer Function and Open-Loop Output Impedance
where
By taking the same analysis steps used for Gvd (s), the input–output transfer function can be derived as
Kp =
vˆo
Gvs (s) ≡ vˆs d= ˆ ˆio =0
ωzp =
s s2 1 + + 2 ωesr Qn2 ωn2 ωn2 ≈ Ks 2 s s2 s 1 + Qd1 ωd1 + ω2 1 + Qd2 ωd2 + ωs2 1+
s
d1
ωd1
d2
(17)
RLf R RLf + R RLf Lf +
Lm (1−2D)2 n2
(22) .
(23)
Fig. 6 shows the predictions of (17) and (21) in comparison with the measured transfer functions of the experimental converter. While the input–output transfer functions [Fig. 6(a)] show a close agreement, the open-loop output impedances [Fig. 6(b)]
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Fig. 7. Closed-loop controlled ASHB converter. (a) Small-signal circuit model. (b) Small-signal block diagram representation. The converter employs a standard voltage-mode control. Fm is the modulator gain of the PWM block and Fv (s) represents the transfer function of the voltage feedback compensation.
reveal the influence of the measurement noise at low and high frequencies. III. F EEDBACK C OMPENSATION D ESIGN AND C LOSED -L OOP A NALYSIS Once the power-stage transfer functions are analyzed, the feedback compensation can be designed to obtain good closedloop performance. A graphical loop-gain method [8] is adapted to design the feedback compensation and analyze the closedloop performance of the ASHB converter. A. Feedback Compensation Design and Loop Gain Fig. 7(a) shows a small-signal circuit model of the ASHB converter that employs standard voltage-mode control, while Fig. 7(b) presents a block diagram representation of Fig. 7(a). In Fig. 7, Fm is the modulator gain of the PWM block and Fv (s) represents the transfer function of the voltage feedback compensation. Analytical expressions for all the gain blocks shown in Fig. 7(b) are given in Table I. For the given Gvd (s), a three-pole two-zero compensation is selected for Fv (s) s s 1 + ωzc2 Km 1 + ωzc1 Fv (s) = (24) s s 1 + ωpc2 s 1 + ωpc1
Fig. 8. Loop gain of closed-loop controlled ASHB converter. (a) Asymptotic plots. (b) Loop gain. The thick lines are the predictions of (25), while the thin lines are the measurements. The crossover frequency occurs at fc = ωc /2π = 4.3 kHz with a 60◦ phase margin.
in order to achieve desirable characteristics for the loop gain T (s) = Gvd (s)Fv (s)Fm . Fig. 8(a) shows the asymptotic plots for |Gvd (s)|, |Fv (s)|, and |T (s)|. The compensation parameters for Fv (s) are determined as follows. 1) Two compensation zeros are placed around the first resonant frequency of Gvd (s), the first compensation zero before the resonant frequency and the second zero after the resonant frequency (ωzc1 < ωd1 < ωzc2 ), to compensate for the −180◦ phase delay caused by the resonance. 2) The first compensation pole is placed at the esr zero of Gvd (s), ωpc1 = ωesr = 1/ (Cf RCf ), to nullify the effects of the esr zero. 3) The second compensation pole ωpc2 is added between the esr zero and the second resonant frequency of Gvd (s), ωesr < ωpc2 < ωd2 , to minimize the detrimental effects of the secondary resonance at ωd2 . 4) Finally, the integrator gain Km is adjusted to locate the crossover frequency of the loop gain, ωc in Fig. 8(a),
CHOI et al.: SMALL-SIGNAL ANALYSIS AND CONTROL DESIGN OF HALF-BRIDGE DC–DC CONVERTERS
Fig. 9. Audio susceptibility of closed-loop controlled ASHB converter. (a) Asymptotic plots. (b) Audio susceptibility. The thick line is the prediction of (29), while the thin line is the measurement. The effect of the adjoining doublepole (fd2 = 17.7 kHz) and double-zero (fn2 = 22.0 kHz) pair is evident.
between the second compensation zero and the second compensation pole, ωzc2 < ωc < ωpc2 . This ensures that the loop gain crosses the 0-dB line with a −20 dB/dec slope, thereby securing a sufficient phase margin.
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Fig. 10. Output impedance of closed-loop controlled ASHB converter. (a) Asymptotic plot. (b) Output impedance. The thick line is the prediction of (31), while the thin line is the measurement. The measured output impedance shows the noise at low frequencies and a glitch at high frequencies.
To apply the graphical method [8], the relationship of (26) can be paraphrased as Gvs (s) at frequencies below ω where |T | 1 c Au (s) ≈ T (s) . Gvs (s) at frequencies above ωc where |T | 1 (27)
The equation for the loop gain is then given by T (s) = Kd Km Fm 2 s s 1+ ωzc2 1+ Qn1sωn1 + ωs2 1+ ωzc1 n1 . (25) × 2 s s s2 s 1+ Qd2 ωd2 + ωs2 s 1+ ωpc2 1+ Qd1 ωd1 + ω2 d1
Fig. 9(a) illustrates the method of constructing an asymptotic plot for |Au (s)| based on (27). From Fig. 9(a), the maximum value for audio susceptibility is determined by |Au (s)|max = 20 log
d2
Fig. 8(b) shows the prediction of (25) and the measured loop gain of the experimental converter with the voltage compensation designed as outlined above. The crossover frequency of the loop gain occurs at fc = ωc /2π = 4.3 kHz with a phase margin of 60◦ .
Ks ωzc1 [dB]. Kd Km Fm
(28)
An equation for Au (s) can now be written based on the asymptotic plot and (28) as 2 s 1+ Qn2sωn2 + ωs2 s 1+ ωpc2 n2 Au (s) ≈ KA 2 s s s 1+ ωzc1 1+ ωzc2 1+ ωc 1+ Qd2sωd2 + ωs2 d2
(29)
B. Audio Susceptibility The application of Mason’s gain rule to Fig. 7(b) yields an expression for the audio susceptibility of the closed-loop ASHB converter Au (s) =
vo (s) Gvs (s) . = vs (s) Closed loop 1 + T (s)
(26)
with KA =
Ks . Kd Km Fm
(30)
Fig. 9(b) compares the predictions of (29) with the measured audio susceptibility. The transfer functions show a deviation
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The step load response of the ASHB converter can be analyzed using the output impedance and its relationship to the output voltage [9]. To simplify the step load analysis of the experimental converter, the output impedance is approximated to a first-order function Zapp drawn with a dotted line in Fig. 10(a), by ignoring the poles and zeros appearing before ωc : ωzp , ωzc1 , ωzc2 , and ωpc1 in Fig. 10(a). With this simplification, the following relationships hold for the experimental converter [9] ∆vo (t)max = ∆Istep |Zo (s)|max = ∆Istep |Zo (∞)| tss =
Fig. 11. Step load response of output voltage. (a) Theoretical prediction of averaged model. (b) Experimental result.
at midfrequencies, thereby revealing the limitation of the asymptotic analysis, which does not consider the effects of the phase characteristics of the transfer functions. The effects of the adjoining double-pole (fd2 = ωd2 /2π = 17.7 kHz) and double-zero (fn2 = ωn2 /2π = 22.0 kHz) pair, which are also not included in the asymptotic analysis in Fig. 9(a), are evident in Fig. 9(b). C. Output Impedance and Step Load Response Similar to the case of audio susceptibility, an asymptotic plot for the closed-loop output impedance can be constructed as shown in Fig. 10(a). The output impedance can now be expressed as vo (s) io (s) closed loop s 1 + ωpc1 s 1 + ωszp ≈ KZ s s 1 + ωzc1 1 + ωzc2 1+
(35)
where ∆vo (t)max represents the maximum excursion of the output voltage from its steady-state value, ∆Istep is the magnitude of the step change of the load current, and tss represents the setting time of the transient response. Fig. 11 shows the output voltage of the experimental converter when it experiences a step change from 0.5 to 1.67 Ω in the load resistance ∆Istep = 4 A. The upper waveform is the theoretical prediction of the average model developed for ASHB converters, and the lower waveform is the response of the experimental converter measured with an electric load. The transient responses show a good correlation with the analytical predictions of ∆vo (t)max = 4 A × (0.240.5) Ω = 0.67 V and tss = 3/(2π4.3 × 103 ) = 110 µs. The transient response also reveals a decaying oscillation, reflecting the effects of the glitch in the output impedance. The frequency of the oscillation corresponds to the frequency at which the glitch was observed in the experimental output impedance. IV. C ONCLUSION
Zo (s) ≡
s ωc
(31)
with KZ = (RCf R)
3 ωc
(34)
ωzp ωpc1 . ωzc1 ωzc2 ωc
(32)
The maximum value for the output impedance is given by its high-frequency asymptote |Zo (s)|max = |Zo (∞)| = 20 log(RCf R) [dBΩ].
(33)
Fig. 10(b) compares the prediction of (31) with the measured closed-loop output impedance. In addition to the deviation at midfrequencies, the measured output impedance also reveals a glitch at high frequencies. The glitch is an influence of the peaking of the loop gain, which was not accounted for in the asymptotic analysis. The experimental output impedance also exhibits the noise at low frequencies.
This paper presented the theoretical and practical details involved in the small-signal analysis, control design, and closed-loop analysis of an ASHB dc–dc converter. The circuit averaging technique was used to study the power-stage dynamics of the ASHB converter. It was shown that the duty ratio–output transfer function is very sensitive to the operating conditions of the converter and becomes null as the duty ratio approaches the critical value of D = 0.5. A graphical loop-gain method was adapted to design the feedback compensation and analyze the closed-loop performance. Design guidelines were established for a voltage feedback compensation that can offer good closed-loop performance in the presence of the peculiar power-stage dynamics of ASHB converters. All the open- and closed-loop transfer functions of the ASHB converter were derived in an analytical form and are summarized in Table I. The predicted transfer functions revealed a good correlation with the experimental data. The general results of this paper can also be adapted to other asymmetrically driven bridge-type PWM converters to improve their control design and analyze their closedloop performance.
CHOI et al.: SMALL-SIGNAL ANALYSIS AND CONTROL DESIGN OF HALF-BRIDGE DC–DC CONVERTERS
519
2
Lf + Cf (RLf RCf + RLf R + RCf R) + Lm (1−2D) n2 RLf + R 2 ) + RCc Cc Cf (RLf RCf + RLf R + RCf R) + Lf + Cc (RCf + R) Lf + Lm (1−2D n2
a1 = RCc Cc +
a2 = Cc Lm +
RCc Cc Cf (RCf + R) Lf + a3 = a4 =
Lm (1−2D 2 ) n2
RLf + R
Lm (1−2D)2 n2
(45)
+ Lm Cc (Cf (RLf RCf + RLf R + RCf R) + Lf ) (46)
RLf + R Lf Cf Lm Cc (RCf + R) RLf + R
(47)
A PPENDIX D ERIVATION OF D UTY R ATIO –O UTPUT T RANSFER F UNCTION From the small-signal model in Fig. 2(c) and the accompanying (3)–(6), a set of circuit equations can be derived as RCf + sC1 f R vˆo = vˆrec (36) RLf + sLf + RCf + sC1 f R (1 − 2D) VS − 2VCc ˆ vˆcc + d n n vˆsw − vˆcc ˆ = + ipri sLm
vˆrec = vˆcc RCc + sC1 c
(44)
vˆsw = VS dˆ ˆipri = (2D − 1) ˆiL + 2IL dˆ n n ˆiL = vˆrec − vˆo . RLf + sLf
(37) (38) (39) (40) (41)
A simultaneous solution of (36)–(41) with the incorporation of VCc = DVS yields 2 s 1 + ωesr 1 + Qn sωn + ωs2 vˆo n1 1 1 (42) = Kd ∆(s) dˆ
(1 − 2D)2 /n2 . While the condition Lf /Lm (1 − 2D)2 /n2 can easily be met for most practical applications, the factorized expression of the duty ratio–output transfer function retains a good accuracy, even though this assumption is not strictly satisfied. R EFERENCES [1] T. Ninomiya, N. Matsumoto, M. Nakahara, and K. Harada, “Static and dynamic analysis of ZVS half-bridge converter with PWM control,” in Proc. IEEE Power Electron. Specialists Conf., 1991, pp. 230–237. [2] P. Imbertson and N. Mohan, “Asymmetrical duty cycle permits zero switching loss in PWM circuits with no conduction loss penalty,” IEEE Trans. Ind. Appl., vol. 29, no. 1, pp. 121–125, Jan./Feb. 1993. [3] R. Oruganti, P. C. Heng, J. T. K. Guan, and L. A. Choy, “Soft-switched DC/DC converter with PWM control,” IEEE Trans. Power Electron., vol. 13, no. 1, pp. 102–114, Jan. 1998. [4] J. Sebastian, J. A. Cobos, D. Garcia, and J. Uceda, “Small-signal modeling of the half-bridge complementary-control dc-to-dc converter,” in Proc. IEEE CIEP, Oct. 1995, pp. 44–50. [5] E. F. Linear, J. Sebastian, M. A. Perez Garcia, J. Diaz, and A. Fontan, “Closing the feedback loop in the half-bridge complementary-control dc-to-dc converter,” in Proc. IEEE Appl. Power Electron. Conf., Feb. 1997, pp. 977–982. [6] S. Korotkov, V. Meleshin, A. Nemchinov, and S. Fraidlin, “Small-signal modeling of soft-switched asymmetrical half-bridge dc/dc converter,” in Proc. IEEE Applied Power Electronics Conf., Mar. 1995, pp. 707–711. [7] E. Dijk, H. Spruijt, D. M. Osullivan, and J. B. Klaassens, “PWM-switch modeling of DC-DC Converters,” IEEE Trans. Power Electron., vol. 10, no. 6, pp. 659–665, Nov. 1995. [8] R. D. Middlebrook, “Modeling current-programmed buck and boost regulators,” IEEE Trans. Power Electron., vol. 4, no. 1, pp. 36–52, Oct. 1989. [9] B. Choi, “Step load response of a current mode controlled dc-to-dc converter,” IEEE Trans. Aerosp. Electron. Syst., vol. 33, no. 4, pp. 1115–1121, Oct. 1997.
with ∆(s) = 1 + a1 s + a2 s2 + a3 s3 + a4 s4
(43)
where a1 , a2 , a3 , and a4 are as shown in (44)–(47), found at the top of the page. To show the equivalence of (42) to (7), the following relationship: s s s2 s2 ∆(s) ≈ 1 + 1+ + 2 + 2 Qd1 ωd1 ωd1 Qd2 ωd2 ωd2 (48) can now be verified by expanding the right-hand side of (48) and comparing the resulting coefficients with ak s (k = 1, 2, 3, 4) given by (44)–(47) under the condition of Lf /Lm
Byungcho Choi (S’90–M’91) received the B.S. degree in electronics from Hanyang University, Seoul, Korea, in 1980, the M.S. and the Ph.D. degrees in electrical engineering from Virginia Polytechnic Institute and State University, Blacksburg, in 1988, and 1992, respectively. From 1992 to 1993, he was a Research Scientist at the Bradley Department of Electrical Engineering, Virginia Polytechnic Institute and State University. From 1994 to 1995, he served as a Team Leader of the Power Electronics Systems Team, Samsung Electronics Company. In 1996, he joined the School of Electrical Engineering and Computer Science, Kyungpook National University, Taegu, Korea, where he is currently an Associate Professor. His research interest includes modeling and design optimization of high-frequency power converters for portable electronics, computer power systems, and distributed power systems.
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 2, APRIL 2006
Wonseok Lim received the B.S. and M.S. degrees in electronics engineering from Kyungpook National University, Taegu, Korea, in 1999 and 2001, respectively. He is currently working toward the Ph.D. degree at Kyungpook National University. His research interest includes modeling, analysis, and control of board-mount dc–dc power converters for telecommunication applications.
Sanghyun Bang received the B.S. degree from Taegu University, Taegu, Korea, in 2001 and the M.S. degree from Kyungpook National University, Taegu, in 2003, all in electronics engineering. He is currently with LG Electronics, Gumi, Korea, where he is working on the design, fabrication, and testing of high-efficiency drive circuits for plasma display panel application systems.
Seungwon Choi (M’91) received the B.S. degree in electronics engineering from Hanyang University, Seoul, Korea, in 1980, the M.S. degree in electronics engineering from Seoul National University, Seoul Korea, in 1982, and the M.S. degree in computer engineering and the Ph.D. degree in electrical engineering from Syracuse University, Syracuse, NY, in 1985 and 1988, respectively. From 1988 to 1989, he was with the Department of Electrical and Computer Engineering, Syracuse University, as an Assistant Professor. In 1992, he joined Hanyang University as an Assistant Professor. He is currently a Professor in the School of Electrical and Computer Engineering. His research interests include digital communications and adaptive signal processing with a recent focus on the real-time implementation of the smart antenna systems for 3G mobile communication systems.
