Spin-Transfer Torque Magnetic RAM (STT-MRAM) Opportunities in On ...
Graduate Category: Engineering and Technology Degree Level: MSECE Abstract ID# 1018
Spin-Transfer Torque Magnetic RAM (STT-MRAM) Opportunities in On-chip Caches Daein Kang Faculty Advisor: Yong-Bin Kim, High Performance VLSI Research Laboratory Abstract
STT-MRAM as a Embedded Memory Solution
Embedded STT-MRAM (Spin Transfer Toque Magnetic RAM) is about to create potentially disruptive nonvolatile memory subsystem due to its capability of providing high write speed and essentially high write endurance. Embedded STT-MRAM has become more energy-efficient in conjunction with robust data retention, scalable for advanced logic technology nodes. Also STT-MRAM is likely to become a promising technology to partly replace SRAM as embedded cache and to get high performance microprocessor. To take all advantages of STT-MRAM and SRAM, the use of STT-MRAM only and hybrid type cache (SRAM & STT-MRAM or eDRAM & STT-MRAM) is investigated to construct new system hierarchies using these new combinations. This paper focuses on the emerging memory technologies like STT-MRAM to improve the performance of system architectures and to reduce power consumption, and possible impact on integrating STT-MRAM into current memory subsystems so as to create new system hierarchies.
Measurements and Results
I. Memory technologies for on-die caches
MTJ parameters integrated into CACTI
Memory technologies for implementing on-die LLCs (Last level caches) include SRAM, STT-RAM, and eDRAM. These candidate technologies are fast and have high write endurance. Other memory technologies such as PCM (phase change memory), Flash, and Memristor are relatively slow and have limited endurance, making them less suitable for implementing on-die caches. Bandwidth are the most important design considerations for the L1 and L2 caches. Therefore these caches are usually implemented using high-performance SRAMs. L3 last-level cache designs, however, target high capacity and low power. As a result, in addition to using low leakage SRAM to construct LLCs, STTRAM are potential memory technology alternatives.
Source : Mu-Tien Chang et al. (University of Maryland)
MTJ Configurations
Emerging Memory Technologies for Future New Memory Subsystems Replacement Strategies
Ⅲ. Embedded STT-MRAM Possibilities
A: MTJ configuration A B : MTJ configuration B C: SRAM
SRAM-based L3 cache replacement or Hybrid type (eDRAM+STT-MRAM or SRAM+STTMRAM)
• Performance : Read/Write Speed 10e12 cycles for RAM applications • Low Power Logic CMOS platform compatibility • Scalability : less than 20nm • Cell size & Density : less demanding requirements than standalone Only embedded STT-MRAM has a potential to meet these requirements Challenges : to get a 64~256Mb density, 1~10ns of read latency, 1e16 endurance
New memory solutions are being developed for the future value. It is not expected that emerging memories will replace the existing memory (DRAM and Flash) but will make a new memory class. Emerging memory can alter the current memory system architectures. While memory industry is pursuing DRAM-like performance with low latency but relatively high cost such as STTMRAM, they are seeking cost focused solution with higher latency but low cost such as PCRAM and ReRAM. Source : Jason Heidecker, Cal. Institute of Tech 2012 Everspin, Crocus technology
Source : Yuan Xie, Penn State University
In-Plane
JC0[mA/cm2]
2
2
Δ MTJ Area [cm2] Rp [㏀] Rap [㏀] Bit line Voltage [V] Raccess [㏀]
40
40
2*10-10 1.5 3 1.8 1.5
2*10-10 1.5 3 1.3 0.3
In order to compare with SRAM , we use CACTI tool that generate low-power cache memories for two different MTJ configurations. The fastest read latency is achieved by SRAM. Among the MTJ configurations, the configuration A shows the best timing. This is due to its small cell area. The configurations A and B have a similar write time of around 10 ns that is quite worse than SRAM. Regarding the read energy, the configuration A shows the best results also outperforming SRAM. Write energy consumption mainly depends on both current density and pulse width needed to flip over the magnetic orientation of MTJ device. The in-plane MTJ still requires a great deal of energy to write, about 3x more than SRAM.
Conclusion
Source : Applied Materials at AVS TFUG 2014
Emerging memory Technologies
In-Plane
Source : KAUSHIK ROY, Purdue Univ.
Reconfigurable Hybrid Cache Architecture Source : Samsung Investors Forum 2014
B
STT Type
II. STT-MRAM as Last Level Cache
Drop-in replacement of SRAM with STT-MRAM for LLC leads to improvement in Capacity and leakage, but higher latency and active energy
A
Configuration
For the time being, emerging memories will not replace the existing memory (DRAM and Flash) but will make a new memory class. Of all the emerging memory technologies, STTMRAM is applied to the embedded applications in the form of pure STT-MRAM or Hybrid cache in terms of large capacity and low leakage power as well as performance. As discussed above, it can be challenging to meet all these requirements at the same time, but STT-MRAM’s attributes can lead to in-memory computing architectures for future SoC.
References [1] Yuan Xie, Pennsylvania State University, “Emerging NVM memory Technologies [2] Kangho Lee, GlobalFoundries, “Embedded Spin-Transfer Torque MRAM” [3] Samsung Investor’s Forum 2014 [4] Micron 2015 Winter Analyst Conference
Spin-Transfer Torque Magnetic RAM (STT-MRAM) Opportunities in On-chip Caches Daein Kang Faculty Advisor: Yong-Bin Kim, High Performance VLSI Research Laboratory Abstract
STT-MRAM as a Embedded Memory Solution
Embedded STT-MRAM (Spin Transfer Toque Magnetic RAM) is about to create potentially disruptive nonvolatile memory subsystem due to its capability of providing high write speed and essentially high write endurance. Embedded STT-MRAM has become more energy-efficient in conjunction with robust data retention, scalable for advanced logic technology nodes. Also STT-MRAM is likely to become a promising technology to partly replace SRAM as embedded cache and to get high performance microprocessor. To take all advantages of STT-MRAM and SRAM, the use of STT-MRAM only and hybrid type cache (SRAM & STT-MRAM or eDRAM & STT-MRAM) is investigated to construct new system hierarchies using these new combinations. This paper focuses on the emerging memory technologies like STT-MRAM to improve the performance of system architectures and to reduce power consumption, and possible impact on integrating STT-MRAM into current memory subsystems so as to create new system hierarchies.
Measurements and Results
I. Memory technologies for on-die caches
MTJ parameters integrated into CACTI
Memory technologies for implementing on-die LLCs (Last level caches) include SRAM, STT-RAM, and eDRAM. These candidate technologies are fast and have high write endurance. Other memory technologies such as PCM (phase change memory), Flash, and Memristor are relatively slow and have limited endurance, making them less suitable for implementing on-die caches. Bandwidth are the most important design considerations for the L1 and L2 caches. Therefore these caches are usually implemented using high-performance SRAMs. L3 last-level cache designs, however, target high capacity and low power. As a result, in addition to using low leakage SRAM to construct LLCs, STTRAM are potential memory technology alternatives.
Source : Mu-Tien Chang et al. (University of Maryland)
MTJ Configurations
Emerging Memory Technologies for Future New Memory Subsystems Replacement Strategies
Ⅲ. Embedded STT-MRAM Possibilities
A: MTJ configuration A B : MTJ configuration B C: SRAM
SRAM-based L3 cache replacement or Hybrid type (eDRAM+STT-MRAM or SRAM+STTMRAM)
• Performance : Read/Write Speed 10e12 cycles for RAM applications • Low Power Logic CMOS platform compatibility • Scalability : less than 20nm • Cell size & Density : less demanding requirements than standalone Only embedded STT-MRAM has a potential to meet these requirements Challenges : to get a 64~256Mb density, 1~10ns of read latency, 1e16 endurance
New memory solutions are being developed for the future value. It is not expected that emerging memories will replace the existing memory (DRAM and Flash) but will make a new memory class. Emerging memory can alter the current memory system architectures. While memory industry is pursuing DRAM-like performance with low latency but relatively high cost such as STTMRAM, they are seeking cost focused solution with higher latency but low cost such as PCRAM and ReRAM. Source : Jason Heidecker, Cal. Institute of Tech 2012 Everspin, Crocus technology
Source : Yuan Xie, Penn State University
In-Plane
JC0[mA/cm2]
2
2
Δ MTJ Area [cm2] Rp [㏀] Rap [㏀] Bit line Voltage [V] Raccess [㏀]
40
40
2*10-10 1.5 3 1.8 1.5
2*10-10 1.5 3 1.3 0.3
In order to compare with SRAM , we use CACTI tool that generate low-power cache memories for two different MTJ configurations. The fastest read latency is achieved by SRAM. Among the MTJ configurations, the configuration A shows the best timing. This is due to its small cell area. The configurations A and B have a similar write time of around 10 ns that is quite worse than SRAM. Regarding the read energy, the configuration A shows the best results also outperforming SRAM. Write energy consumption mainly depends on both current density and pulse width needed to flip over the magnetic orientation of MTJ device. The in-plane MTJ still requires a great deal of energy to write, about 3x more than SRAM.
Conclusion
Source : Applied Materials at AVS TFUG 2014
Emerging memory Technologies
In-Plane
Source : KAUSHIK ROY, Purdue Univ.
Reconfigurable Hybrid Cache Architecture Source : Samsung Investors Forum 2014
B
STT Type
II. STT-MRAM as Last Level Cache
Drop-in replacement of SRAM with STT-MRAM for LLC leads to improvement in Capacity and leakage, but higher latency and active energy
A
Configuration
For the time being, emerging memories will not replace the existing memory (DRAM and Flash) but will make a new memory class. Of all the emerging memory technologies, STTMRAM is applied to the embedded applications in the form of pure STT-MRAM or Hybrid cache in terms of large capacity and low leakage power as well as performance. As discussed above, it can be challenging to meet all these requirements at the same time, but STT-MRAM’s attributes can lead to in-memory computing architectures for future SoC.
References [1] Yuan Xie, Pennsylvania State University, “Emerging NVM memory Technologies [2] Kangho Lee, GlobalFoundries, “Embedded Spin-Transfer Torque MRAM” [3] Samsung Investor’s Forum 2014 [4] Micron 2015 Winter Analyst Conference
