How to improve system ESD protection while lowering on-chip ESD protection Richard Renard STMicroelectronics
Abstract This article presents the new challenges of ESD protection for portable equipment, with the evolution of sub-micron CMOS ICs lithography dimensions. While the integration of on-chip ESD protections is becoming more challenging, the Industry Council is proposing a reduction of the target levels of on-chip ESD protection. We will discuss how to select and implement the most efficient external ESD protection to pass IEC 61000-4-2 at the system level.
Introduction Mobile devices featuring multimedia capability now incorporate richer, thinner, and lighter designs with increased needs for intensive integration and high bandwidth. This is possible with the evolution of sub-micron CMOS ICs towards lower lithography dimensions and increased use of system in package technology. This highly-integrated and compact environment makes ESD considerations even more important. The integration of on-chip ESD protection becomes more challenging and the closer juxtaposition of the integrated circuits to the external connectors makes the system protection (IEC 61000-4-2 standard compliance) even more difficult to achieve. Very efficient external ESD protection is required to sufficiently protect the sensitive Sub-micron CMOS ICs and pass IEC 61000-4-2 standards compliance.
Sub-micron Integrated Circuit Evolution In order to improve circuit speed, address high speed application, and richer content, thinner lithography dimensions are required. As a matter of fact, the gate oxide thickness enters the nanometer range. 20 Maximum core supply voltage Oxide breakdown @ 100ns
Voltage (V)
15
10
5
0 L (µm) 0.5 Gox (nm) 15
0.35 8
0.25 5
0.18 3.5
0.13 2.2
0.1 1.7
Source: JEDEC JEP155
Figure 1. Sub-micron Integrated circuit oxide breakdown voltage
For instance, in 0.1µm and smaller generations, the gate oxide of a transistor becomes increasingly thin (below 1.7 nm). This thinness results in a remarkable drop of the transistor's oxide breakdown voltage (Figure 1). Thinner the oxides - lower the CDM (Contact Discharge Model) performance. Thinner the metallization - higher the resistance and the heating of the circuit. As a result, the circuit has lower CDM and HBM (Human Body Model) performances and is remarkably more sensitive to ESD discharges.
On-chip ESD protection trend & ESD council targets As the cost of circuits is a ubiquitous concern for both circuit makers and users, an Industry Council on ESD target levels was initiated in 2006 to review on-chip ESD target levels. According to this Council, the enhanced static control methods required by OEMs do not justify the current Human Body Model and Machine Models. In addition, everybody knows that the thinner the circuit lithography, the higher the technology cost. Thus, according to the ESD Council, ESD over-design in today’s high integration technologies is tremendously constraining in terms of chip area, and the cost of on-chip ESD protections becomes non-negligible. Furthermore, those areas occupied by ESD protection elements have significant impact on silicon performance, design cycle time, and time to market.
$ Design for 2kV HBM
Design for 1kV HBM
Standard
HBM
MM
Current
2kV
200V
Proposed
1kV
30V
Design necessary for safe handling 90nm 2003
65nm 2005
45nm 2008
Technology node @ product qualification
Source: JEDEC JEP155
Figure 2. On-chip ESD protection cost versus technology node Figure 2 shows the impact of the technology node on the cost of on-chip ESD protection. The gap in cost between the design necessary for safe handling and the design for 2kV HBM sustainability has increased a lot, thanks to enhanced static control methods. Therefore, the ESD Council has proposed new ESD targets levels, downgrading the HBM and MM targets from, respectively, 2kV to 1kV and 200V to 30V. However, the combination of thinner gate oxide and lower on-chip ESD protection levels will highly decrease the robustness of the integrated circuit in an ESD-risky environment such as portable electronic applications.
Electro-Static Discharge effects The effects of electro-static discharges can lead to IC destruction through various failure modes. Two examples are given below. See Figure 3 & 4.
Figure 3. Oxide punchthrough
Figure 4. Melting Oxide
In addition, ESD can lead to IC latch-up by triggering a parasitic structure (equivalent to a thyristor), a PNPN structure which acts as a PNP and an NPN transistor stacked together. It causes a high amount of current to continuously flow through it, once it is accidentally triggered. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS). Vcc I/O
Rwell
T1
T2 Rsubstrat
Figure 5. A parasitic thyristor that can result in latch-up Now, let’s compare two major ESD test standards applied in the electronic industry: • The JESD22-A114D applied to integrated circuit • The IEC 61000-4-2 applied to electronic equipments such as mobile phone, notebook, displays…
ESD standards comparison The JESD22-A114D is commonly used as the Human Body Model (HBM). The levels are shown in figure 6a and figure 6b. Basically, a 2kV surge corresponds to a 1.33A surge. A 1kV surge corresponds to a 0.67A surge. The rise time duration of the surge is 5 to 9ns. This ESD standard intends to simulate ESD issues during handling in the assembly line. It has no meaning when the IC device is implemented into a system.
Human body
ESD Surge Generator R=1500 Ω
R=1.5kΩ
HIGH VOLTAGE GENERATOR
C= 100pF
DUT
DEVICE UNDER TEST
C=100pF
tR < 10ns Figure 6a. JESD22-A114D ESD Surge generator
Current through a shorting wire
Current through a shorting wire
Figure 6b. JESD22-A114D Standard Test Waveform Class Class 0
Voltage Range V < 250 V
Class 1A
250 V < V
8kV
I > 5.33A
Figure 6C. JESD22-A114D Standard Class levels There are other standards that are applied to semiconductor ICs like Charge Device Model and Machine Model. We will not discuss these models. For a system point of view, the standard that must apply is the IEC 61000-4-2. This standard certifies the ESD requirement for the final application. In terms of power, the rise time of the surge less than 1ns and the current can go up to 30A. The di/dt is then above 30A/ns. See Figure 7a and figure 7b. So, in terms of energy this is far above the HBM standard values.
ESD Surge Generator R=330 Ω
HIGH VOLTAGE GENERATOR
DEVICE UNDER TEST
C=150pF
tR < 1ns Figure 7a. IEC 61000-4-2 ESD Surge generator
Level
Contact
Air
Indicated Voltage (kV)
peak current (A)
1
2
2
7.5
2
4
4
15
3
6
8
22.5
4
8
15
30
Figure 7b. IEC 61000-4-2 Standard Waveform and Class levels If we compare the main parameters of IEC61000-4-2 versus the HBM model we notice the following: 1. IEC 61000-4-2 applies to final applications. Consumer products (such as Mobile handset) must pass IEC61000-4-2 level 4. 2. IEC 61000-4-2 level 4 discharge current is more than 20 times more powerful than the HBM Class 1C discharge current. Too high of a discharge current usually leads to IC destruction (damages transistor gate oxide). 3. IEC 61000-4-2 level 4 di/dt is more than 250 times higher than the HBM Class 1C di/dt. Too high di/dt usually leads to either IC destruction or latch-up failure. So, moving down the IC ESD targets may create more susceptibility to IEC 61000-4-2 failures and will require even more efficient external ESD protection in order to clamp remaining overvoltage below the maximum oxide breakdown voltage and soften the di/dt surge. Now, we must discuss how to select the right external ESD protection.
External ESD protection solutions There are mainly three types of ESD protection devices widely used in the market: 1. Metal Oxide Varistor 2. Transient Voltage Suppressor (TVS) 3. Integrated Z-R-Z structure (TVS – Resistor – TVS) MOV
TVS
Integrated Z-R-Z
Directionality
Bi-dir only
Uni or Bi-dir
Uni or Bi-dir
Turn-on time
500-1000ps
Few ps
Few ps
Typical Clamping Voltage
>100V
20-50V