Statistical Design and Optimization of SRAM Cell for Yield Enhancement
Statistical Design and Optimization of SRAM Cell for Yield Enhancement Saibal Mukhopadhyay, Hamid Mahmoodi, and Kaushik Roy Dept. of Electrical and Computer Engineering, Purdue University, West Lafayette, IN-47907, USA <sm, mahmoodi, kaushik>@ecn.purdue.edu ABSTRACT In this paper, we have analyzed and modeled the failure probabilities of SRAM cells due to process parameter variations. A method to predict the yield of a memory chip based on the cell failure probability is proposed. The developed method is used in an early stage of a design cycle to minimize memory failure probability by statistically sizing of SRAM cell. 1. INTRODUCTION In nano-scaled devices, the random variations in the number and location of dopant atoms in the channel region of the device cause random variations in transistor threshold voltage [1–3], known as “Random (or discrete) Dopant Fluctuation” (RDF). The impacts of random dopant effect are most pronounced in minimum-geometry transistors commonly used in area-constrained circuits such as SRAM cells [4]. This can result in the threshold voltage mismatch between the neighboring transistors in a cell, resulting in the failure of a cell. Since these failures are caused by the variation in the device parameters, these are known as the parametric failures. A failure in any of the cells in a column (or row) of the memory will make that column (or row) faulty. If the number of faulty columns (or rows) in a memory chip is larger than the number of available redundant columns (or rows), then the chip is considered to be faulty. Hence, the failure probability of a cell is directly related to the yield of a memory chip. The parametric variations, and in particular the Vt fluctuation due to RDF, is a strong function of the size of the different transistors in the cell (channel length (L), width (W)), collectively called as the cell parameters. Hence, the failure probability of a memory can be reduced by optimally designing these parameters. However, any such optimization has to consider its impact on the overall area and the leakage of the SRAM array. Moreover, the memory organization (i.e. # of row (NROW) and # of row (NCOL), # of redundant column (NRC)) will also have a strong impact on the memory failure probability. Hence, a statistical design and optimization of the SRAM cell and memory organization is very important to reduce the memory failure and improve the yield in nano-scaled SRAM. In this paper, we have developed a methodology to optimize the parameters of an SRAM cell and the memory organization to reduce the memory failure probability (constrained by the overall memory area and leakage power) and improve the yield in nanometer regime. The method is developed considering the on-die Vt variation, but can be extended to consider on-die L and W variation. In our SRAM cell (Fig.1), we have used transistors of 50nm gate Drain−to−Source Current (µA/µm)
PR
PL
V R = ‘0 ’
V L = ‘1 ’ AXL
AXR NL
NR
Subthreshold
leakage ( I sub )
Gate leakage ( I gd) BL
Junction leakage (
I jn)
Fig. 1: SRAM Cell
BR
700
MODEL MEDICI
NMOS with L =25nm eff
600 500 400 300 200
PMOS with L =25nm eff
100 0 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
flipping
(a) read failure
(c) hold failure
length (Leff=25nm) designed using MEDICI [6-7]. In our analysis, we have used the short channel MOSFET theory to model the currents and threshold voltage considering the device geometry and doping profile [3,5] (Fig. 2). 2. DISTRIBUTION OF THE INTRINSIC Vt VARIATION In an SRAM cell, the threshold voltage (Vt) fluctuations (GVt) of the cell transistors are considered as six independent Gaussian random variables (mean=0) [1]. The standard deviation of the Vt fluctuation (ıVt) depends on the manufacturing process, doping profile, and the transistor sizing. In the proposed method, ıVt for a minimum sized transistor (ıVt0) is an input parameter and the dependence of ıVt on the transistor size is given by [3]:
V Vt
V Vt 0
Lmin L Wmin
W
(1)
3. MODELING OF SRAM FAILURE The failures due to parametric variations in a SRAM cell are principally caused by: (1) An increase in the access time of the cell resulting in a violation of delay requirement, defined as access time failure, (2) Destructive read (i.e. flipping of the stored data in a cell known as the read failure) and/or unsuccessful write (inability to write to a cell defined as the write failure), resulting in a dynamic stability failure (Fig. 3) and, (3) The destruction of the cell content in the standby mode with the application of a pre-specified (designed) lower supply voltage (VHOLD), known as hold-stability failure (Fig. 3). In a die, failures are principally caused by the mismatch in the device parameters (L, W, Vt) of different transistors (intra-die) in the cell. Such device mismatch changes the strength of the different transistors resulting in different failure events. The principal source of the device mismatch is the intrinsic fluctuation of the Vt of different transistors due to RDF [1]. Hence, in this work we have considered the Vt variation due to RDF as the major source of intra-die variation. The proposed method can also be extended to include L and W variation.
0.8
Gate−to−Source Voltage [V]
Fig. 2: Device Characteristics
0-7803-8702-3/04/$20.00 ©2004 IEEE.
(b) write failure
Fig. 3: Unstable read, write, and hold failures in SRAM cell
3.1. Modeling Methodology In this section, we will summarize the key mathematical bases used to estimate the failure probabilities. Let us consider y=f(x1, …, xn) as a function, where x1, …, xn are independent Gaussian random variables with mean K1,…,K2 and standard deviation (STD) V1,…,V2. The mean (Py) and the STD (Vy) of the random variable y can be estimated as (using multi-variable Taylor-series expansion) [8]:
800 WL VDD
No writing
flipping
10
V
n
1 2
n
¦
i 1
§ w f ( x ,..., x ) n 1 w ( xi ) ©
¦ ¨¨
2 y
i 1
w 2 f ( x 1 ,..., x n ) w ( xi ) 2
(2)
2
Ki
distributions with the means the variances obtained using (2) (Fig. 4). PRF is given by: PRF P>Z R { VREAD VTRIPRD ! 0@ 1 ) ZR (0) (7) 2 where, K ZR KV READ KVTRIP and V ZR V V2READ V V2TRIPRD
V i2 Ki
· ¸ V2 ¸ i ¹
Assuming the Probability Distribution Function (PDF) of y to be also Gaussian (Ny(y:Py,Vy)), the probability of (y > Y0) is given by: Y0
f
P> y ! Y0 @
3.3. Write Stability Failure (WF) While writing a ‘0’ to a cell storing ‘1’, the node VL gets discharged through BL to a low value (VWR) determined by the voltage division between the PMOS PL and the access transistor AXL [9]. If VL can-not be reduced below the trip point of the inverter PR-NR (VTRIPWR), within the time when word-line is high (TWL), then a write failure occurs (Fig. 3b). The write-failure probability (PWF) is given by: PWF P> TWRITE ! TWL @ (8) where, TWRITE is the time required to pull down VL from VDD to VTRIPWR. TWRITE is obtained by solving: VTRIP C L (VL ) dVL ° ; if (VWR VTRIPWR ) ° TWRITE ® I in ( L ) (VL ) I out ( L ) (VL ) V DD (9) ° if (VWR t VTRIPWR ) ¯°f;
³N
y ( y : P y , V y )dy
1
y Y0
³N
y ( y )dy
1 ) y Y0
(3)
y f
where, )y is the Cumulative Distribution Function (CDF) of y. Let us assume y=f(x1,…,xn) and z=g(x1,…,xn) are two Gaussian random variables Ny(y:Py,Vy) and Nz(y:Pz,Vz), respectively. The probability of (y > Y0 & z > Z0) is given by: P> y ! Y0 & z ! Z 0 @ 1 P> y d Y0 z d Z 0 @ 1 ^P> y d Y0 @ P>z d Z 0 @ P> y d Y0 & z d Z 0 @` (4) ^P>y ! Y0 @ P>z ! Z 0 @ 1` ) y, z Y0 , Z 0
³
where, ) y,z(y,z) is the joint CDF of y and z. In order to evaluate )y,z(y,z) the correlation coefficient between y and z needs to be computed. The correlation coefficient (U is given by: E yz E y E z E yz P y P z U V y V z V yV z 1 n w 2 fg 2 f (K 1 ,..., K n ) g (K 1 ,..., K n ) ¦ Vi 2 i 1 w ( xi ) 2
E yz f0 g0
1 n § w2 f wf wg w2g ¨¨ g 0 2 f0 ¦ 2 2 i 1© wxi wxi wxi w x i2
I in ( L )
(5)
· 2 ¸¸V i ¹
The above results will be used in this paper to estimate the failure probabilities of different events. 3.2. Read Stability Failure (RF) While reading the cell shown in Fig. 1 (VL=‘1’ & VR=‘0’), due to the voltage divider action between AXR and NR , VR increases to a positive value VREAD. If VREAD is higher than the trip point of the inverter PL-NL (VTRIPRD), then the cell flips while reading the cell (Fig. 3(a)) [9]. This represents a read failure (RF) event. Hence, the read-failure probability (PRF) is given by: (6) PRF P VREAD ! VTRIPRD VTRIPRD and VREAD can be obtained by solving KCL at node L and R, respectively. The estimated value of VTRIPRD and VREAD closely follows the MEDICI simulation result (Fig. 4). Assuming the PDF of VREAD (=NRD(vREAD)) and VTRIP (=NTRIP(vTRIP)) as Gaussian
>
@
1200
0.48 MODEL MEDICI
∆Vt to PMOS Only (δVtPL)
65
0.4 0.38 0.36
700 Gaussian Model (Numerical)
600 Gaussian Model (Analytical)
400
50
0
0.05
0 0.1
0.1
0.12
0.14
0.16 VREAD 0.18 [V]
0.2
0.22
0.24
450 Analytical Non−Central
24
350 # of occurance
400 F−Model
22 20
T
18
14
250
∆Vt applied to PL only (δVtPL)
∆Vt applied to AXL )
12 only (δVt
0
0.05
0 20
0.1
100
30
40
50 Taccess [ps]
60
70
80
(b) distribution of TACCESS
1000
Variation in δVt , NR δVt , δVt , δVt NL PL PR
MODEL MEDICI
The write failures mostly comes from the long tail of the distribution. Non−Central F distribution matches the tail of the distribution better.
200
−0.05
0.8
300
150
16
200
0.9
Monte−Carlo Gaussian Model Non−Central F Model VDDMin at HOLD (VHOLD [V])
MODEL MEDICI
26
Gaussian Model (Numerical)
400
|∆Vt| [V]
500
28
Gaussian Model (Analytical)
500
Fig. 6: (a) TACCESS variation with įVt
Fig. 4: (a) Variation of VTRIP of PL-NL (b) Distributions of VREAD 30
600
100
35 −0.1
Monte Carlo Gaussian Model (Numerical) Gaussian Model (Analytical)
900 800 700
0.7
Variation in δVt , δVt NL
600
PL
0.6
0.5
Variation in δVt
# of occurance
−0.05
MODEL MEDICI
40
|∆Vt| [V]
[ps]
NR
55
300
200
∆Vt to NMOS Only (δVtNL)
0.3 −0.1
WRITE
∆Vt applied to NR only (δVt )
60
45
0.34 0.32
Monte−Carlo Gaussian Model (Numerical) Analytical Model (Analytical)
800
800
[ps]
# of occurance
VTRIP
0.42
900
∆Vt applied to AX R only (δVtAXR)
70
ACCESS
0.44
1000
75
Monte−Carlo Gaussian Model (Numerical) Gaussian Model (Analytical)
1000
current out of L | I dsAXL
where CL is the net capacitance at the node L. VWR can be obtained by solving KCL at node L & R [9]. VTRIPWR can be obtained by solving for trip-point of the inverter PR-NR. TWRITE obtained using (9) closely matches the MEDICI simulation result with Vt variation of different transistors (Fig. 5a). Using (2), we can estimate the mean (ȘTWR) and the standard-deviation (ıTWR) and approximate its pdf as a Gaussian one (fWR(tWR)) (Fig. 5b). However, most of the write-failures originate from the ‘tail’ of the distribution function. Hence, to improve the accuracy of the model at the tail region, we can use a non-central F distribution [8]. Using the PDF (Gaussian/non-central F) of TWRITE(NWR(tWR), the PWF can be estimated using (3). 3.4. Access Time Failure (AF) The cell access time (TACCESS) is defined as the time required to produce a pre-specified voltage difference (ǻMIN§0.1VDD) between two bit-lines (bit-differential). If due to Vt variation, the access time of the cell is longer than the maximum tolerable limit (TMAX), an access time failure is said to have occurred. The probability of access time failure (PAF) of a cell is given by: PAF P (TACCESS ! TMAX ) (10) While reading the cell storing VL=‘1’ and VR=‘0’ (Fig.1, Fig.3), bitline BR will discharge through AXR and NR (by the current IBR).
T
0.46
current into L | I dsPL , I out ( L )
# of occurance
f (K 1 ,..., K n )
Py
, δVt
NR
PR
0.4
500 Gaussian Model (Numerical)
400 300 200 Gaussian Model
100 (Analytical)
50
AXL
10 −0.1
−0.05
|∆Vt| 0[V]
0.05
0.1
Fig. 5: (a) TWRITE variation with įVt
0 0
10
20
30 40 Twrite [ps]
50
(b) distribution of TWRITE
0.3 0
60
0.05
0.1
0.15
0.2
|∆Vt| [V]
Fig. 7: (a) VDDHmin variation with įVt
11
0
0.1
0.2
0.3
0.4
0.5 0.6 0.7 V [ps]
0.8
HOLD
(b) distribution of VDDHmin
0.9
columns fail. Hence, PCOL and PMEM can be given by:
Simultaneously, BL will discharge by the leakage of AXL of all the cells (IBL) connected to BL. Hence, the access time is given by: T ACCESS
C BR C BL ' MIN C BL I BR C BR I BL
C B ' MIN I dsatAXR
¦I
subAXL ( i )
PCOL
(11)
i 1,.., N
where, N is the #of cells attached to a bit-line (or column), CBR/BL is the bit-line capacitance (assumed to be equal). The access time given by (11) closely follows the MEDICI simulation result (Fig. 6a). The PDF of TACCESS can be approximated as a Gaussian one with the mean (ȘTAC) and the standard deviation (ıTAC) obtained from (2) (Fig. 6b). Using the derived PDF (NTACCESS(tACCESS)), PAF can be estimated using (3). 3.5. Hold Stability Failure (HF) In the stand-by mode, the VDD of the cell is reduced to reduce the leakage power consumption. However, if the lowering of VDD causes the data stored in the cell to be destroyed, then the cell is said to have failed in the hold-mode [10] (Fig. 3c). Hence, for a hold-failure event, the minimum supply voltage that can be applied to the cell in the hold-mode (VDDHmin), without destroying the data, is higher than the designed stand-by mode supply voltage (VHOLD). Thus, the probability of hold-stability failure (PHF) is given by: PHF P>VDDHmin ! VHOLD @ (12) Lowering the VDD of the cell (say VDDH represents the cell VDD at the hold mode) reduces the voltage at the node storing ‘1’ (VL in Fig. 1). Due to leakage of NL, VL will be less than VDDH for low VDDH. The hold-failure occurs if VL < VTRIP of PR-NR. Hence, VDDHmin can be obtained by numerically solving: VL VDDHmin , GVt PL , GVt NL VTRIP VDDHmin , GVt PR , GVt NR (13) The estimated value of VDDHmin using (13) closely follows the values obtained from MEDICI simulation (Fig. 7a). The distribution of VDDHmin can be approximated as a Gaussian one with mean and variance obtained using (6) (Fig. 7b). Using the Gaussian pdf for VDDHmin the PHF can be estimated (using (3)). 3.6. Estimation of Overall Cell Failure Probability (PF) The overall failure probability is given by: PF
i
§ N COL · i NCOL i ¨¨ i ¸¸ PCOL 1 PCOL ¹ N RC 1 ©
¦
§ · Yield 1 ¨ PMEM LINTER ,WINTER ,Vt INTER N INTER ¸ ¨ ¸ © INTER ¹
¦
P>AF RF @ P>AFWF @ P>AF H F @ P>RFWF @ P>RF H F @ P>WF H F @ (14) P>AF RFWF @ P>AF RF H F @ P>RFWF H F @ P>WF H F AF @ P>All @
(15)
The exact estimation of the different failure probabilities requires numerical solutions of the KCL at different nodes. In order to reduce the computation complexity, analytical models of different failure probabilities were also obtained using simplified longchannel current equations. The distributions of VREAD, VTRIPRD, TACCESS, TWRITE and VHOLD using the analytical models are also shown in Figs. 4-7. 4. SENSITIVITY ANALYSIS OF FAILURE PROBABILITY Fig. 8 shows that a weak access transistor (small Wnax) reduces PRF (VREAD decreases); however, it increases PAF and PWF (Fig. 8) and has very small impact on PHF. Reducing the strength of the PMOS pull-up transistors (by decreasing Wp) reduces PWF (reducing IdsPL), but increases PRF (lowers VTRIPRD). PAF does not depend strongly on PMOS strength (Fig. 8). PHF improves with an increase in Wp as the node L is more strongly coupled to the supply voltage (VL oVDDH). Increasing Wnpd increases the strength of pull-down NMOSs (NL & NR)). This reduces PRF (VREAD p) and PAF by increasing the strength of NR (Fig. 8). Increase in width of NR has little impact on PWF. Although, it slightly increases the nominal value of TWRITE, the reduction of ıVT of NR (see (1)) tends to reduce ıTWRITE and hence PWF remains almost constant. An increase in the VTRIP of PR-NR initially reduces PHF with the increase in Wnpd. However, a higher width of NL reduces VL (from the applied VDDH) due to an increase the leakage of NL. Consequently, a very high Wnpd increases the PHF. 5. STATISTICAL OPTIMIZATION OF SRAM CELL 5.1. SRAM Yield Estimation Model To estimate the yield, we have used Monte-Carlo simulations for inter-die distributions of L, W and Vt (assumed to be Gaussian).For each inter-die values of the parameters (say LINTER, WINTER and VtINTER) we estimate PF, PCOL and PMEM considering the intra-die distribution of įVt. Finally, the yield is defined as:
P>Fail@ P>AF RF WF H F @ PAF PRF PWF PHF
(16)
where, NINTER is the total number of inter-die Monte-Carlo simulations (i.e. total number of chips). In order to maximize the yield PMEM needs to be minimized. This requires optimum design of the cell configurations (i.e. length and width of transistors) and the number of redundant columns (NRC). However, such an optimization of PMEM has to consider the impact on the total leakage and the total area (AMEM). 5.2. Estimation of Leakage in SRAM The total leakage in a cell is principally consist of the subthreshold leakage, the gate leakage, and the junction BTBT leakage through different transistors in the cell (Fig. 1). The leakage current expressions presented in [5] are used to evaluate the different leakage components. The total memory leakage (ILeakMem) is the summation of leakage of individual cells. 5.3. Area Estimation of SRAM
An accurate estimate of the probability of joint events is possible by constructing the joint PDF representing two events using the procedure given in (4). We have also assumed that probabilities of simultaneous occurrence of more than two events are negligible (§0). The estimated probabilities match the Monte-Carlo results very closely. 3.7. Estimation of Column and Memory Failure Probability The failure probability of column (PCOL) (or row (PROW)) is defined as the probability that any of the cells (out of N cells) in that column (or row) fails. Assuming a column redundancy, the probability of failure of a memory chip (PMEM) designed with NCOL number of columns and NRC number of redundant columns, is defined as the probability that more than NRC (i.e. at least NRC+1) (a) Wnpd
NCOL
1 (1 PF ) N and PMEM
(b) Wp
(c) Wnax
Fig. 8: Variation of Cell Failure Probabilities with Cell structure
12
1. Determine the bounds on NRC and initialize: i=0, NRC(0)=NRCmin, PMEMmin= 1 2. repeat 3. Determine maximum allowable cell area: 4. Acellmax (i ) d AMAX >N ROW N RC (i ) N COL @ 5. Solve the following optimization problem 6. Minimize PF (Lnax, Wnax, Lnpd, Wnpd, Lpup, Wpup) 7. Subject to: Acell Acellmax(i); PLeakPower PLeakMin; PTAC PTAC-MAX. 8. Calculate PCOL(i) and PMEM(i) using the optimum PF and NRC(i). 9. If PMEM(i) < PMEMMIN Then PMEMmin := PMEM(i) 10. until NRC(i)=NRCmax
The total memory area is given by:
AMEM
Aactual Aredundant
N ROW N RC Acell
N ROW ( N COL N RC ) Acell
(17)
where, Aactual is the required memory area (given by the memory size) and Aredundant is the area overhead of the redundant columns. Acell is the cell area computed using the layout given in [11]. 5.4. Optimization Procedure The optimization problem can be stated as:
Minimize PMEM=f(X) where X Ł [Lnax, Wnax, Lnpd, Wnpd, Lpup, Wpup, NRC] Subject to: ILeakMem ILeakMax AMEM Maximum Area (AMAX)
Fig. 9: Optimization procedure 0
(18)
0.25
10
Write−Failure Probability −1
10
E[TAC]=PTACCESS Maximum access time mean (PTAC-MAX)
Probability
σ
For all the parameters: {XMIN} {X} {XMAX}
=35mV
Vt0
−2
10
σ
=45mV
Vt0
0 0 0.2
This is essentially a non-linear optimization problem with nonlinear constraints. The upper bound on the mean access time is given to ensure that robustness of the memory has not been achieved by significantly sacrificing performance. Fig. 9 shows the basic steps of the optimization process. The upper bound of NRC is Fig. 10: impact NRC on memory yield. Fig. 11: Impact of SNM on failure determined using (17) as shown below: probability of SRAM cell AMEM N ROW N COL Acellmin AMEM N RCmax N COL (19) Acellmin N ROW Acellmin N ROW Table I: optimization results PMEM ILeak TAC Yield The minimization of PF in step 5-7 requires the estimation of the Enax/Ep EnpdEnax PF joint probabilities given in (4) which are computationally expensive. Cell [11] 1.5 1.36 2.6e-3 0.034 851PA 55ps 47% However, it should be noted that: Opt. Cell 1.2 1.48 3.4e-5 0.001 950PA 46ps 95% indicates that with larger amount of variations, design of robust cell PF P>AF RF WF H F @ d PAF PRF PWF PHF PFMOD (20) is more effective in reducing the failure probability (improving Hence, instead of minimizing PF we try to minimize PFMOD. The yield) as compared to increasing number of redundant columns. above problem can be solved using Lagrange Multiplier based Hence, it can be concluded that a statistical analysis of algorithm [12]. The Lagrangian formulation of the above problem effectiveness of the redundancy is necessary to improve the is shown below: memory failure probability. Minimize f(X)=PFMOD The static noise margin (SNM) of a cell is often used as a measure where X Ł [Lnax, Wnax, Lnpd, Wnpd, Lpup, Wpup] of the robustness of an SRAM cell against flipping [1]. However, Subject to: h1(X) = (Acell / Acellmax(i))-1d 0 an increase in SNM makes the cell difficult to write by increasing its data holding capability, which increases write failures (Fig. 11). h2(X) = (ILeakMem /ILeakMax )-1d0 Consequently, an increase in the SNM does not necessarily reduce h3(X) = (PTAC /PTAC-MAX r )-1d0 In this work, we have considered the discrete variable space (to the overall failure probability. Using the proposed models, it is account for the minimum limit on the lithographic controllability of observed that SNM does not have a strong relationship with the L and W) for Lnax, Wnax, Lnpd, Wnpd, Lpup and Wpup. To solve the parametric failure of the memory. discrete space Lagrangian problem, we have used the Discrete 7. CONCLUSION In this work, we have proposed a semi-analytical method to Lagrangian Method (DLM) described in [12,13]. estimate the failure probability of an SRAM cell and memory due 6. OPTIMIZATION RESULTS to parameter variations. The derived models have been used to The optimization methodology described earlier is used to predict the yield of memory at an early stage of a design. The optimize the cell structure (from [14]) and the use of redundancy to proposed models are used for statistical optimization of memory minimize the memory failure probability (Table-I). To improve the design, which is necessary for maximizing yield in nano-meter beta ratio between the pull-up PMOS and access transistor, the regimes. original cell was designed with a longer PMOS. However, a weaker REFERENCES PMOS tends to increase the read failure. Hence, the optimization [1] A. Bhavnagarwala, et. al., IEEE JSSC, vol. 36, pp. 658-665, April 2001. reduces the length of the PMOS and uses the extra area in the pull- [2] X. Tang, et. al., IEEE Trans. VLSI Syst., vol. 5, pp. 369–376, Dec. 1997. down NMOS, thereby reducing the access failure. The proposed [3] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, New optimization algorithm allows to trade-off between the redundancy York: Cambridge Univ. Press, 1998. area and the active cell area. Reducing the number of redundant [4] D. Burnett, et. al., Symp. VLSI Tech., pp. 15–16, June 1994. column allows more area for each of the actual cells. This reduces [5] S. Mukhopadhyay, et. al., DAC, pp. 169 -174, June 2003. the failure probability of the cells, thereby reducing PMEM. On the [6] http://www-mtl.mit.edu/Well/ other hand, from (15) it can be observed that reducing NRC will tend [7] MEDICI: 2-D device simulation program, Synopsys Inc. [8] A. Papoulis, Probability, Random Variables and Stochastic Process to increase PMEM. Fig. 10 shows the variation of PMEM with the [9]A. Chandrakasan, Design of High-Performance Microprocessor Circuits variation of NRC considering constant AMEM. It can be observed that [10] H. Quin, et. al., Symp. On Quality Elect. Design, pp. 55-60, Mar. 2004. increasing the redundancy beyond a certain point increases the [11] R.W. Mann, IBM journal of R&D, pp. 553-566, Sep. 2003. memory failure probability. It should be further noted that with the [12] B. W. Wah, et. al., Int. Conf. on Tools with AI, 2000 application of a higher value of the ıVt0, the optimized value of the [13] Edwin K. P. Chong, An introduction to Optimization [14] A. Agarwal, et. al., IEEE JSSC, vol. 38, pp. 319-328, Feb. 2003. redundancy (that minimizes failure probability) reduces. This −3
10
Cell failure Memory Failure
Static Noise Margin (V)
N ROW N COL Acell ; Aredundant
Probability
Aactual
Read−Failure Probability
−4
10
13
0
5 10 Redundant Column/Actual Coulmn [%]
15
1
1.5
0.15 2.5
2
Width of Access Transistor
−7
x 10
PR
PL
V R = ‘0 ’
V L = ‘1 ’ AXL
AXR NL
NR
Subthreshold
leakage ( I sub )
Gate leakage ( I gd) BL
Junction leakage (
I jn)
Fig. 1: SRAM Cell
BR
700
MODEL MEDICI
NMOS with L =25nm eff
600 500 400 300 200
PMOS with L =25nm eff
100 0 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
flipping
(a) read failure
(c) hold failure
length (Leff=25nm) designed using MEDICI [6-7]. In our analysis, we have used the short channel MOSFET theory to model the currents and threshold voltage considering the device geometry and doping profile [3,5] (Fig. 2). 2. DISTRIBUTION OF THE INTRINSIC Vt VARIATION In an SRAM cell, the threshold voltage (Vt) fluctuations (GVt) of the cell transistors are considered as six independent Gaussian random variables (mean=0) [1]. The standard deviation of the Vt fluctuation (ıVt) depends on the manufacturing process, doping profile, and the transistor sizing. In the proposed method, ıVt for a minimum sized transistor (ıVt0) is an input parameter and the dependence of ıVt on the transistor size is given by [3]:
V Vt
V Vt 0
Lmin L Wmin
W
(1)
3. MODELING OF SRAM FAILURE The failures due to parametric variations in a SRAM cell are principally caused by: (1) An increase in the access time of the cell resulting in a violation of delay requirement, defined as access time failure, (2) Destructive read (i.e. flipping of the stored data in a cell known as the read failure) and/or unsuccessful write (inability to write to a cell defined as the write failure), resulting in a dynamic stability failure (Fig. 3) and, (3) The destruction of the cell content in the standby mode with the application of a pre-specified (designed) lower supply voltage (VHOLD), known as hold-stability failure (Fig. 3). In a die, failures are principally caused by the mismatch in the device parameters (L, W, Vt) of different transistors (intra-die) in the cell. Such device mismatch changes the strength of the different transistors resulting in different failure events. The principal source of the device mismatch is the intrinsic fluctuation of the Vt of different transistors due to RDF [1]. Hence, in this work we have considered the Vt variation due to RDF as the major source of intra-die variation. The proposed method can also be extended to include L and W variation.
0.8
Gate−to−Source Voltage [V]
Fig. 2: Device Characteristics
0-7803-8702-3/04/$20.00 ©2004 IEEE.
(b) write failure
Fig. 3: Unstable read, write, and hold failures in SRAM cell
3.1. Modeling Methodology In this section, we will summarize the key mathematical bases used to estimate the failure probabilities. Let us consider y=f(x1, …, xn) as a function, where x1, …, xn are independent Gaussian random variables with mean K1,…,K2 and standard deviation (STD) V1,…,V2. The mean (Py) and the STD (Vy) of the random variable y can be estimated as (using multi-variable Taylor-series expansion) [8]:
800 WL VDD
No writing
flipping
10
V
n
1 2
n
¦
i 1
§ w f ( x ,..., x ) n 1 w ( xi ) ©
¦ ¨¨
2 y
i 1
w 2 f ( x 1 ,..., x n ) w ( xi ) 2
(2)
2
Ki
distributions with the means the variances obtained using (2) (Fig. 4). PRF is given by: PRF P>Z R { VREAD VTRIPRD ! 0@ 1 ) ZR (0) (7) 2 where, K ZR KV READ KVTRIP and V ZR V V2READ V V2TRIPRD
V i2 Ki
· ¸ V2 ¸ i ¹
Assuming the Probability Distribution Function (PDF) of y to be also Gaussian (Ny(y:Py,Vy)), the probability of (y > Y0) is given by: Y0
f
P> y ! Y0 @
3.3. Write Stability Failure (WF) While writing a ‘0’ to a cell storing ‘1’, the node VL gets discharged through BL to a low value (VWR) determined by the voltage division between the PMOS PL and the access transistor AXL [9]. If VL can-not be reduced below the trip point of the inverter PR-NR (VTRIPWR), within the time when word-line is high (TWL), then a write failure occurs (Fig. 3b). The write-failure probability (PWF) is given by: PWF P> TWRITE ! TWL @ (8) where, TWRITE is the time required to pull down VL from VDD to VTRIPWR. TWRITE is obtained by solving: VTRIP C L (VL ) dVL ° ; if (VWR VTRIPWR ) ° TWRITE ® I in ( L ) (VL ) I out ( L ) (VL ) V DD (9) ° if (VWR t VTRIPWR ) ¯°f;
³N
y ( y : P y , V y )dy
1
y Y0
³N
y ( y )dy
1 ) y Y0
(3)
y f
where, )y is the Cumulative Distribution Function (CDF) of y. Let us assume y=f(x1,…,xn) and z=g(x1,…,xn) are two Gaussian random variables Ny(y:Py,Vy) and Nz(y:Pz,Vz), respectively. The probability of (y > Y0 & z > Z0) is given by: P> y ! Y0 & z ! Z 0 @ 1 P> y d Y0 z d Z 0 @ 1 ^P> y d Y0 @ P>z d Z 0 @ P> y d Y0 & z d Z 0 @` (4) ^P>y ! Y0 @ P>z ! Z 0 @ 1` ) y, z Y0 , Z 0
³
where, ) y,z(y,z) is the joint CDF of y and z. In order to evaluate )y,z(y,z) the correlation coefficient between y and z needs to be computed. The correlation coefficient (U is given by: E yz E y E z E yz P y P z U V y V z V yV z 1 n w 2 fg 2 f (K 1 ,..., K n ) g (K 1 ,..., K n ) ¦ Vi 2 i 1 w ( xi ) 2
E yz f0 g0
1 n § w2 f wf wg w2g ¨¨ g 0 2 f0 ¦ 2 2 i 1© wxi wxi wxi w x i2
I in ( L )
(5)
· 2 ¸¸V i ¹
The above results will be used in this paper to estimate the failure probabilities of different events. 3.2. Read Stability Failure (RF) While reading the cell shown in Fig. 1 (VL=‘1’ & VR=‘0’), due to the voltage divider action between AXR and NR , VR increases to a positive value VREAD. If VREAD is higher than the trip point of the inverter PL-NL (VTRIPRD), then the cell flips while reading the cell (Fig. 3(a)) [9]. This represents a read failure (RF) event. Hence, the read-failure probability (PRF) is given by: (6) PRF P VREAD ! VTRIPRD VTRIPRD and VREAD can be obtained by solving KCL at node L and R, respectively. The estimated value of VTRIPRD and VREAD closely follows the MEDICI simulation result (Fig. 4). Assuming the PDF of VREAD (=NRD(vREAD)) and VTRIP (=NTRIP(vTRIP)) as Gaussian
>
@
1200
0.48 MODEL MEDICI
∆Vt to PMOS Only (δVtPL)
65
0.4 0.38 0.36
700 Gaussian Model (Numerical)
600 Gaussian Model (Analytical)
400
50
0
0.05
0 0.1
0.1
0.12
0.14
0.16 VREAD 0.18 [V]
0.2
0.22
0.24
450 Analytical Non−Central
24
350 # of occurance
400 F−Model
22 20
T
18
14
250
∆Vt applied to PL only (δVtPL)
∆Vt applied to AXL )
12 only (δVt
0
0.05
0 20
0.1
100
30
40
50 Taccess [ps]
60
70
80
(b) distribution of TACCESS
1000
Variation in δVt , NR δVt , δVt , δVt NL PL PR
MODEL MEDICI
The write failures mostly comes from the long tail of the distribution. Non−Central F distribution matches the tail of the distribution better.
200
−0.05
0.8
300
150
16
200
0.9
Monte−Carlo Gaussian Model Non−Central F Model VDDMin at HOLD (VHOLD [V])
MODEL MEDICI
26
Gaussian Model (Numerical)
400
|∆Vt| [V]
500
28
Gaussian Model (Analytical)
500
Fig. 6: (a) TACCESS variation with įVt
Fig. 4: (a) Variation of VTRIP of PL-NL (b) Distributions of VREAD 30
600
100
35 −0.1
Monte Carlo Gaussian Model (Numerical) Gaussian Model (Analytical)
900 800 700
0.7
Variation in δVt , δVt NL
600
PL
0.6
0.5
Variation in δVt
# of occurance
−0.05
MODEL MEDICI
40
|∆Vt| [V]
[ps]
NR
55
300
200
∆Vt to NMOS Only (δVtNL)
0.3 −0.1
WRITE
∆Vt applied to NR only (δVt )
60
45
0.34 0.32
Monte−Carlo Gaussian Model (Numerical) Analytical Model (Analytical)
800
800
[ps]
# of occurance
VTRIP
0.42
900
∆Vt applied to AX R only (δVtAXR)
70
ACCESS
0.44
1000
75
Monte−Carlo Gaussian Model (Numerical) Gaussian Model (Analytical)
1000
current out of L | I dsAXL
where CL is the net capacitance at the node L. VWR can be obtained by solving KCL at node L & R [9]. VTRIPWR can be obtained by solving for trip-point of the inverter PR-NR. TWRITE obtained using (9) closely matches the MEDICI simulation result with Vt variation of different transistors (Fig. 5a). Using (2), we can estimate the mean (ȘTWR) and the standard-deviation (ıTWR) and approximate its pdf as a Gaussian one (fWR(tWR)) (Fig. 5b). However, most of the write-failures originate from the ‘tail’ of the distribution function. Hence, to improve the accuracy of the model at the tail region, we can use a non-central F distribution [8]. Using the PDF (Gaussian/non-central F) of TWRITE(NWR(tWR), the PWF can be estimated using (3). 3.4. Access Time Failure (AF) The cell access time (TACCESS) is defined as the time required to produce a pre-specified voltage difference (ǻMIN§0.1VDD) between two bit-lines (bit-differential). If due to Vt variation, the access time of the cell is longer than the maximum tolerable limit (TMAX), an access time failure is said to have occurred. The probability of access time failure (PAF) of a cell is given by: PAF P (TACCESS ! TMAX ) (10) While reading the cell storing VL=‘1’ and VR=‘0’ (Fig.1, Fig.3), bitline BR will discharge through AXR and NR (by the current IBR).
T
0.46
current into L | I dsPL , I out ( L )
# of occurance
f (K 1 ,..., K n )
Py
, δVt
NR
PR
0.4
500 Gaussian Model (Numerical)
400 300 200 Gaussian Model
100 (Analytical)
50
AXL
10 −0.1
−0.05
|∆Vt| 0[V]
0.05
0.1
Fig. 5: (a) TWRITE variation with įVt
0 0
10
20
30 40 Twrite [ps]
50
(b) distribution of TWRITE
0.3 0
60
0.05
0.1
0.15
0.2
|∆Vt| [V]
Fig. 7: (a) VDDHmin variation with įVt
11
0
0.1
0.2
0.3
0.4
0.5 0.6 0.7 V [ps]
0.8
HOLD
(b) distribution of VDDHmin
0.9
columns fail. Hence, PCOL and PMEM can be given by:
Simultaneously, BL will discharge by the leakage of AXL of all the cells (IBL) connected to BL. Hence, the access time is given by: T ACCESS
C BR C BL ' MIN C BL I BR C BR I BL
C B ' MIN I dsatAXR
¦I
subAXL ( i )
PCOL
(11)
i 1,.., N
where, N is the #of cells attached to a bit-line (or column), CBR/BL is the bit-line capacitance (assumed to be equal). The access time given by (11) closely follows the MEDICI simulation result (Fig. 6a). The PDF of TACCESS can be approximated as a Gaussian one with the mean (ȘTAC) and the standard deviation (ıTAC) obtained from (2) (Fig. 6b). Using the derived PDF (NTACCESS(tACCESS)), PAF can be estimated using (3). 3.5. Hold Stability Failure (HF) In the stand-by mode, the VDD of the cell is reduced to reduce the leakage power consumption. However, if the lowering of VDD causes the data stored in the cell to be destroyed, then the cell is said to have failed in the hold-mode [10] (Fig. 3c). Hence, for a hold-failure event, the minimum supply voltage that can be applied to the cell in the hold-mode (VDDHmin), without destroying the data, is higher than the designed stand-by mode supply voltage (VHOLD). Thus, the probability of hold-stability failure (PHF) is given by: PHF P>VDDHmin ! VHOLD @ (12) Lowering the VDD of the cell (say VDDH represents the cell VDD at the hold mode) reduces the voltage at the node storing ‘1’ (VL in Fig. 1). Due to leakage of NL, VL will be less than VDDH for low VDDH. The hold-failure occurs if VL < VTRIP of PR-NR. Hence, VDDHmin can be obtained by numerically solving: VL VDDHmin , GVt PL , GVt NL VTRIP VDDHmin , GVt PR , GVt NR (13) The estimated value of VDDHmin using (13) closely follows the values obtained from MEDICI simulation (Fig. 7a). The distribution of VDDHmin can be approximated as a Gaussian one with mean and variance obtained using (6) (Fig. 7b). Using the Gaussian pdf for VDDHmin the PHF can be estimated (using (3)). 3.6. Estimation of Overall Cell Failure Probability (PF) The overall failure probability is given by: PF
i
§ N COL · i NCOL i ¨¨ i ¸¸ PCOL 1 PCOL ¹ N RC 1 ©
¦
§ · Yield 1 ¨ PMEM LINTER ,WINTER ,Vt INTER N INTER ¸ ¨ ¸ © INTER ¹
¦
P>AF RF @ P>AFWF @ P>AF H F @ P>RFWF @ P>RF H F @ P>WF H F @ (14) P>AF RFWF @ P>AF RF H F @ P>RFWF H F @ P>WF H F AF @ P>All @
(15)
The exact estimation of the different failure probabilities requires numerical solutions of the KCL at different nodes. In order to reduce the computation complexity, analytical models of different failure probabilities were also obtained using simplified longchannel current equations. The distributions of VREAD, VTRIPRD, TACCESS, TWRITE and VHOLD using the analytical models are also shown in Figs. 4-7. 4. SENSITIVITY ANALYSIS OF FAILURE PROBABILITY Fig. 8 shows that a weak access transistor (small Wnax) reduces PRF (VREAD decreases); however, it increases PAF and PWF (Fig. 8) and has very small impact on PHF. Reducing the strength of the PMOS pull-up transistors (by decreasing Wp) reduces PWF (reducing IdsPL), but increases PRF (lowers VTRIPRD). PAF does not depend strongly on PMOS strength (Fig. 8). PHF improves with an increase in Wp as the node L is more strongly coupled to the supply voltage (VL oVDDH). Increasing Wnpd increases the strength of pull-down NMOSs (NL & NR)). This reduces PRF (VREAD p) and PAF by increasing the strength of NR (Fig. 8). Increase in width of NR has little impact on PWF. Although, it slightly increases the nominal value of TWRITE, the reduction of ıVT of NR (see (1)) tends to reduce ıTWRITE and hence PWF remains almost constant. An increase in the VTRIP of PR-NR initially reduces PHF with the increase in Wnpd. However, a higher width of NL reduces VL (from the applied VDDH) due to an increase the leakage of NL. Consequently, a very high Wnpd increases the PHF. 5. STATISTICAL OPTIMIZATION OF SRAM CELL 5.1. SRAM Yield Estimation Model To estimate the yield, we have used Monte-Carlo simulations for inter-die distributions of L, W and Vt (assumed to be Gaussian).For each inter-die values of the parameters (say LINTER, WINTER and VtINTER) we estimate PF, PCOL and PMEM considering the intra-die distribution of įVt. Finally, the yield is defined as:
P>Fail@ P>AF RF WF H F @ PAF PRF PWF PHF
(16)
where, NINTER is the total number of inter-die Monte-Carlo simulations (i.e. total number of chips). In order to maximize the yield PMEM needs to be minimized. This requires optimum design of the cell configurations (i.e. length and width of transistors) and the number of redundant columns (NRC). However, such an optimization of PMEM has to consider the impact on the total leakage and the total area (AMEM). 5.2. Estimation of Leakage in SRAM The total leakage in a cell is principally consist of the subthreshold leakage, the gate leakage, and the junction BTBT leakage through different transistors in the cell (Fig. 1). The leakage current expressions presented in [5] are used to evaluate the different leakage components. The total memory leakage (ILeakMem) is the summation of leakage of individual cells. 5.3. Area Estimation of SRAM
An accurate estimate of the probability of joint events is possible by constructing the joint PDF representing two events using the procedure given in (4). We have also assumed that probabilities of simultaneous occurrence of more than two events are negligible (§0). The estimated probabilities match the Monte-Carlo results very closely. 3.7. Estimation of Column and Memory Failure Probability The failure probability of column (PCOL) (or row (PROW)) is defined as the probability that any of the cells (out of N cells) in that column (or row) fails. Assuming a column redundancy, the probability of failure of a memory chip (PMEM) designed with NCOL number of columns and NRC number of redundant columns, is defined as the probability that more than NRC (i.e. at least NRC+1) (a) Wnpd
NCOL
1 (1 PF ) N and PMEM
(b) Wp
(c) Wnax
Fig. 8: Variation of Cell Failure Probabilities with Cell structure
12
1. Determine the bounds on NRC and initialize: i=0, NRC(0)=NRCmin, PMEMmin= 1 2. repeat 3. Determine maximum allowable cell area: 4. Acellmax (i ) d AMAX >N ROW N RC (i ) N COL @ 5. Solve the following optimization problem 6. Minimize PF (Lnax, Wnax, Lnpd, Wnpd, Lpup, Wpup) 7. Subject to: Acell Acellmax(i); PLeakPower PLeakMin; PTAC PTAC-MAX. 8. Calculate PCOL(i) and PMEM(i) using the optimum PF and NRC(i). 9. If PMEM(i) < PMEMMIN Then PMEMmin := PMEM(i) 10. until NRC(i)=NRCmax
The total memory area is given by:
AMEM
Aactual Aredundant
N ROW N RC Acell
N ROW ( N COL N RC ) Acell
(17)
where, Aactual is the required memory area (given by the memory size) and Aredundant is the area overhead of the redundant columns. Acell is the cell area computed using the layout given in [11]. 5.4. Optimization Procedure The optimization problem can be stated as:
Minimize PMEM=f(X) where X Ł [Lnax, Wnax, Lnpd, Wnpd, Lpup, Wpup, NRC] Subject to: ILeakMem ILeakMax AMEM Maximum Area (AMAX)
Fig. 9: Optimization procedure 0
(18)
0.25
10
Write−Failure Probability −1
10
E[TAC]=PTACCESS Maximum access time mean (PTAC-MAX)
Probability
σ
For all the parameters: {XMIN} {X} {XMAX}
=35mV
Vt0
−2
10
σ
=45mV
Vt0
0 0 0.2
This is essentially a non-linear optimization problem with nonlinear constraints. The upper bound on the mean access time is given to ensure that robustness of the memory has not been achieved by significantly sacrificing performance. Fig. 9 shows the basic steps of the optimization process. The upper bound of NRC is Fig. 10: impact NRC on memory yield. Fig. 11: Impact of SNM on failure determined using (17) as shown below: probability of SRAM cell AMEM N ROW N COL Acellmin AMEM N RCmax N COL (19) Acellmin N ROW Acellmin N ROW Table I: optimization results PMEM ILeak TAC Yield The minimization of PF in step 5-7 requires the estimation of the Enax/Ep EnpdEnax PF joint probabilities given in (4) which are computationally expensive. Cell [11] 1.5 1.36 2.6e-3 0.034 851PA 55ps 47% However, it should be noted that: Opt. Cell 1.2 1.48 3.4e-5 0.001 950PA 46ps 95% indicates that with larger amount of variations, design of robust cell PF P>AF RF WF H F @ d PAF PRF PWF PHF PFMOD (20) is more effective in reducing the failure probability (improving Hence, instead of minimizing PF we try to minimize PFMOD. The yield) as compared to increasing number of redundant columns. above problem can be solved using Lagrange Multiplier based Hence, it can be concluded that a statistical analysis of algorithm [12]. The Lagrangian formulation of the above problem effectiveness of the redundancy is necessary to improve the is shown below: memory failure probability. Minimize f(X)=PFMOD The static noise margin (SNM) of a cell is often used as a measure where X Ł [Lnax, Wnax, Lnpd, Wnpd, Lpup, Wpup] of the robustness of an SRAM cell against flipping [1]. However, Subject to: h1(X) = (Acell / Acellmax(i))-1d 0 an increase in SNM makes the cell difficult to write by increasing its data holding capability, which increases write failures (Fig. 11). h2(X) = (ILeakMem /ILeakMax )-1d0 Consequently, an increase in the SNM does not necessarily reduce h3(X) = (PTAC /PTAC-MAX r )-1d0 In this work, we have considered the discrete variable space (to the overall failure probability. Using the proposed models, it is account for the minimum limit on the lithographic controllability of observed that SNM does not have a strong relationship with the L and W) for Lnax, Wnax, Lnpd, Wnpd, Lpup and Wpup. To solve the parametric failure of the memory. discrete space Lagrangian problem, we have used the Discrete 7. CONCLUSION In this work, we have proposed a semi-analytical method to Lagrangian Method (DLM) described in [12,13]. estimate the failure probability of an SRAM cell and memory due 6. OPTIMIZATION RESULTS to parameter variations. The derived models have been used to The optimization methodology described earlier is used to predict the yield of memory at an early stage of a design. The optimize the cell structure (from [14]) and the use of redundancy to proposed models are used for statistical optimization of memory minimize the memory failure probability (Table-I). To improve the design, which is necessary for maximizing yield in nano-meter beta ratio between the pull-up PMOS and access transistor, the regimes. original cell was designed with a longer PMOS. However, a weaker REFERENCES PMOS tends to increase the read failure. Hence, the optimization [1] A. Bhavnagarwala, et. al., IEEE JSSC, vol. 36, pp. 658-665, April 2001. reduces the length of the PMOS and uses the extra area in the pull- [2] X. Tang, et. al., IEEE Trans. VLSI Syst., vol. 5, pp. 369–376, Dec. 1997. down NMOS, thereby reducing the access failure. The proposed [3] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, New optimization algorithm allows to trade-off between the redundancy York: Cambridge Univ. Press, 1998. area and the active cell area. Reducing the number of redundant [4] D. Burnett, et. al., Symp. VLSI Tech., pp. 15–16, June 1994. column allows more area for each of the actual cells. This reduces [5] S. Mukhopadhyay, et. al., DAC, pp. 169 -174, June 2003. the failure probability of the cells, thereby reducing PMEM. On the [6] http://www-mtl.mit.edu/Well/ other hand, from (15) it can be observed that reducing NRC will tend [7] MEDICI: 2-D device simulation program, Synopsys Inc. [8] A. Papoulis, Probability, Random Variables and Stochastic Process to increase PMEM. Fig. 10 shows the variation of PMEM with the [9]A. Chandrakasan, Design of High-Performance Microprocessor Circuits variation of NRC considering constant AMEM. It can be observed that [10] H. Quin, et. al., Symp. On Quality Elect. Design, pp. 55-60, Mar. 2004. increasing the redundancy beyond a certain point increases the [11] R.W. Mann, IBM journal of R&D, pp. 553-566, Sep. 2003. memory failure probability. It should be further noted that with the [12] B. W. Wah, et. al., Int. Conf. on Tools with AI, 2000 application of a higher value of the ıVt0, the optimized value of the [13] Edwin K. P. Chong, An introduction to Optimization [14] A. Agarwal, et. al., IEEE JSSC, vol. 38, pp. 319-328, Feb. 2003. redundancy (that minimizes failure probability) reduces. This −3
10
Cell failure Memory Failure
Static Noise Margin (V)
N ROW N COL Acell ; Aredundant
Probability
Aactual
Read−Failure Probability
−4
10
13
0
5 10 Redundant Column/Actual Coulmn [%]
15
1
1.5
0.15 2.5
2
Width of Access Transistor
−7
x 10
