stf behaviour in a ct Ïâ modulator - Semantic Scholar
STF BEHAVIOUR IN A CT Σ∆ MODULATOR J. De Maeyer, J. Raman, P. Rombouts and L. Weyten Ghent University Dept. Electronics and Information Systems Laboratory (ELIS) Sint-Pietersnieuwstraat 41, 9000 Ghent, Belgium {jpdmaeye, raman, rombouts, weyten}@elis.ugent.be ABSTRACT In this paper we propose a topology for continuous time Σ∆ modulators. Unlike the modulators presented until now, they exhibit no peaking in their signal transfer function. Instead it achieves a ‘flat’ STF with the desired anti-aliasing properties and with small internal nodes signal levels. Now, a simple filter, e.g. a first-order low-pass filter can precede the modulator to prevent out of band signals corrupting the correct operation of the modulator. 1. INTRODUCTION Continuous time (CT) Σ∆ modulators are considered to be very interesting because of their implicit anti-aliasing filter. However, while an anti-aliasing filter is not necessary, still a ‘no-overload’ filter should precede the modulator to prevent instability. This filter is required as in the CT Σ∆ modulators presented until now, the signal transfer function (STF) peaks. This causes out of band signals to be amplified, which can corrupt the correct operation of the modulator and cause instability. Especially at lower oversampling ratio’s (OSR) the STF-peaking occurs close to the bandwidth of the modulator, making the requirements on this ‘no-overload’ filter high. In this paper we extend our previous work [1] and propose a way to prevent this peaking of the STF. Next, we compare the proposed modulator preceded with a simple first-order low-pass filter with traditional modulators preceded with such a filter. This comparison is done for noise transfer functions designed according to two different methods [2, 3]. In both cases good results were obtained. Furthermore, we show that the proposed modulator exhibits the desired feature of containing little input related signal at its internal nodes. 2. STF IN A CT Σ∆ MODULATOR Figure 1 (left) shows the linearized model of a general CT Σ∆ modulator. It consists of a loop filter H(s), a pulse shaper HDAC (s), an (implicit) input filter G(s) and a sampler, with sampling frequency fs (normalized to 1). With J. De Maeyer is supported by a fellowship of the Fund for Scientific Research -Flanders (F.W.O.-Vlaanderen, Belgium).
this model the output of the modulator is: Vout (z) = [G(s)NTF(z)Vin (s)]∗ + Q(z)NTF(z)
(1)
Here, we used the fact that sampling a continuous time signal corresponds to taking the periodic extension of its frequency domain representation. Such a periodic extension of a signal with Laplace transformation A(s) has been denoted as [A(s)]∗ . Also in eq. (1), NTF(z) is the discrete time (DT) noise transfer function, which equals 1/(1 + ˜ ˜ H(z)), where H(z) is the DT equivalent of the CT loop filter H(s) and HDAC (s) [4]. A lot of research has been performed with respect to the second part of eq. (1) as it dictates the performance of the modulator. However, in this paper we concentrate on the first part of eq. (1). The importance of this first term has been recognized before in DT modulators [5] and recently in CT modulators as well as [6]. Q(z) Vin
G(s)
+
+ H(s)
HDAC(s)
Vout
Vin
STF
Q(z)
NTF
+
Vout
Figure 1. CT Σ∆ modulator, definition of NTF and STF. On the right of figure 1 the graphical equivalent of eq. (1) is shown. Besides quantization noise, at the output of the modulator a discrete time signal appears, which is the sampled version of the filtered input signal. The filter acting upon the input signal is the STF (see figure 1): STF(jω) = G(jω)NTF(ejω )
(2)
Let us now look at the STF for two very popular CT Σ∆ modulator topologies. These topologies essentially use a feedforward topology [2] and we will refer to them as FF-I and FF-II. The only difference between the two, is the presence (FF-I) or the absence (FF-II) of a direct path from the input of the modulator to the input of the quantizer. For the FF-I topology the input filter G1 (s) equals 1 + H(s), for FF-II G2 (s) = H(s). While, the DT FF-I topology leads to a STF which is identical to one [5], this is not the case for continuous time modulators. This is illustrated in figure 2, which shows 4 curves. The first is the NTF, which was designed using [2] for an H∞ = 2.5. With the
impulse invariant method (e.g. [4]) the corresponding DT loop filter was translated into a CT loop filter H(s), which is also shown in this figure. The last two curves display the STF for the FF-I and the FF-II topology. The bandwidth of the modulator (OSR of 16) is indicated as well. 20 15
STF FF-II
10
(zzk ), to corresponding CT poles (spk ) and zeros (szk ) according to zpk = espk T and zzk = eszk T (T = f1s ) . Note, that such an equivalence does not exist for negative real zeros/poles with odd multiplicity. In this case an acceptable G(s) is obtained by applying the bilinear transformation (with prewarp distortion) [7] to 1/NTF: 1 1+s/2 G(s) = (3) NTF(z) z= 1−s/2 20
5
15
G
0
10
STFFF-I
-5
H(s)
-10
5
fBW
-15
dB 0
NTF
-20 10
-2
f
10
-1
STF
-5 10
0
-10
fBW
-15
NTF
Figure 2. STF, NTF and H of a typical modulator. -20
Observing the STFs, roughly three regions can be observed. First, for signals in the frequency band of interest, in both the FF-I and FF-II case the STF approximates 1 very well. Second, for larger frequencies, the loop filter H(s) rapidly decreases and then behaves like a first-order filter. As a result in this frequency range G1 (s) approximates 1 for FF-I and G2 (s) ≈ 1 + as for FF-II. Meanwhile the NTF evolves to its maximum value of H∞ . Hence, STFFF-I evolves to the NTF, while STFFF-II first peaks and next behaves like a first-order filter. Third, for frequencies around multiples of fs , the frequency responses of the STFs are dominated by the zeros of the NTF. This leads to the well known (implicit) anti-aliasing filtering action of a CT Σ∆ modulator. In conclusion the frequency responses of both STFFF-I and STFFF-II exhibit a frequency range where the input signals are highly amplified. Hence, out of band signals in this frequency range can cause the input of the quantizer to become overloaded and the modulator unstable. To prevent this risk of instability, a kind of ‘no-overload’ filter should precede these modulators. As, for lower OSR the peaking of the STF occurs much closer to the bandwidth of the modulator, the requirements on this filter can become high. 3. DESIGN OF A FLAT STF In DT Σ∆ modulators, the FF-I structure results in a flat STF [5]. As shown above, this is not the case for CT modulators. However, based on eq. (2) it should be possible to approximate the STF to 1. The input filter G(s) that achieves this property has the same frequency response as 1/NTF. One possible way to obtain this G(s) is to perform a DT/CT pole-zero mapping on 1/NTF. This mapping includes the transformation of the DT poles (zpk ) and zeros
-2
10
-1
f
10
0
10
Figure 3. The resulting G, NTF and STF. For the third order Σ∆ modulator of the previous section, the frequency response of G(s) resulting from the proposed pole-zero mapping is shown in figure 3. Also shown in the figure are the frequency response of the NTF and the resulting STF. Clearly the frequency response of the signal transfer function is greatly improved compared to the STFFF-I and STFFF-II and can be denoted as a ‘flat’ STF. 4. IMPLEMENTATION OF G(S) The proposed procedure yields a G(s) which can be written as: G(s) =
aN sN + aN −1 sN −1 + a1 s + a0 , sN + bN −1 sN −1 + b1 s + b0
(4)
where N is the order of the modulator. Here, it should be noted that the poles of this G(s) are identical to the poles of the loop filter H(s). This general result is the basis of the proposed method as it allows the filter G(s) to be implemented using the (on chip) active components of the filter H(s). This is best illustrated for a modulator with a feedback (FB) topology. A third order variant is depicted in figure 4. Here, the denominator of both H(s) and G(s) equals s3 . The numerator of H(s) is set by the feedback parameters FBi , i ∈ {1, 2, 3}, while the numerator of G(s) is set by the parameters FIni , i ∈ {1, 2, 3, 4}. In the literature three special cases with frequency independent feed-in paths FIni , i ∈ {1, 2, 3, 4} are known. The first type is the purely feedback topology, which corresponds to FIn1 = FB1 and FIni = 0, i 6= 1. The second and
third type correspond to FIni = FBi , i ∈ {1, 2, 3}. With FIn4 = 1 the input filter is G(s) = 1 + H(s), cfr. FF-I. Making FIn4 = 0 yields G(s) = H(s), cfr. FF-II.
the right of figure 6 a possible gm -based implementation is depicted. (only resistor Ri is drawn). In both case the path corresponding to s · FInC is implemented with the capacitor Cin .
Vin
Vb b
FIn1(s)
FIn2(s)
FIn3(s)
Cin
FIn4(s) Vin
1 s
+
-
1 s
+
-
FB1
1 s
+
-
FB2
+
+
Ci
Rin Ri
Vi
-
RDAC
i
V Vin
Vi+1
-
Ci
(a)
Figure 4. A third order FB topology, with feed-in paths to realize the desired input filter G(s). The FB topology of figure 4 allows to implement any kind of G(s) as long as the denominator is s3 , like it is for the loop filter H(s). In principle it is sufficient to set the required feed-in paths FIni according to the numerator of G(s). Unfortunately, doing so leads to FIni 6= FBi . Hence, this would lead to the output of the integrators containing input related signal roughly proportional to the difference FIni − FBi . As shown in [5], this is not desirable with respect to the distortion requirements on the integrators of the loop filter. To prevent this while still being able to implement the desired filter G(s), we propose to make the feed-in paths frequency dependent, more specific: FIni (s) = FIni + s . FInCi . Next we set FIni = FBi which ensures that for s → 0, FIni (s) − FBi → 0. As a result at least for signals in the bandwidth of the modulator the signal levels at the internal nodes remain small. Simulation results of the signal levels at the internal nodes are presented in section 5. With the parameters FIni equal to FBi the parameters FInCi still leave enough freedom to implement the required filter G(s). Finally, note that the proposed FB topology can easily be transformed to a FF topology, like shown in figure 5. Vin
+
s.FInC2 1 s
+
s.FInC3 1 s
+
+
+
Vi+1
+
5. RESULTS Now that we have realized a ‘flat’ STF as shown in figure 3, we can investigate the behaviour of the modulator when it is preceded with a simple filter, e.g. a first-order low-pass filter. To illustrate this we compare the cascade of such a low-pass filter with different modulators. The bandwidth of the low-pass filter was chosen such that it does not attenuate signals in the signal band of interest with more then 0.3 dB. The results are shown in figure 7 and figure 8. For figure 7 a fourth order modulator was designed according to [2] with H∞ = 2.5 and OSR of 16. The resulting STFs for the FF-I and FF-II topology with and without the preceding first-order low-pass filter are shown in figure 7. As can be seen in this case their is a (large) frequency range of signals with a large amplification. Out of band signals in this frequency range can prohibit a correct operation of the modulator and lead to instability. At the same time in the proposed topology all out of band signals are nicely suppressed and the behavior of the transfer function from the input to the output of the system is much more desirable.
STF FF-I
STFFF-II,RC Vo u t
-
Figure 6. Possible circuit implementations.
Q(z) FF3 s
Vin Vb
(b)
10 s.FInC1
+
Vi+1
+
VDAC
HDAC(s)
V
+ i
Vb
Vo u t
FB3
Cin
Ri
Q(z)
STF FF-II
5
FF2 FF1
0 HDAC(s)
Figure 5. A third order FF topology, with feed-in paths to realize the desired input filter G(s).
dB
STFFF-I,RC
-5
-10
In figure 6 simple circuits are shown which can be used to implement the proposed frequency dependent feed-in paths. On the left of figure 6 a possible active-RC implementation is shown, resistor Ri provides the input path for the output of the previous integrator. RDAC and Rin do the same for the feedback signal resp. the input signal. They correspond to the parameters FBi resp. FIni . On
fBW -15
-2
10
f
this work RC 10
-1
10
0
Figure 7. Frequency responses for an NTF designed with [2]. Note that the subscript ‘RC’ stands for the fact that the modulator is preceded with a first-order filter.
In the design method of [2] the poles are placed in butterworth position, all with a positive real part. Furthermore, due to this butterworth position the NTF behaves ‘smoothly’. As a result the pole-zero mapping technique can be used and the results are excellent. In contrast with the above example, the NTF of the next example is designed with the CLANS method [3]. The following parameters orde = 3, OSR = 16, rmax = 0.95, Q = 4 [2] were used. This NTF behaves not as ‘smoothly’ and one of the poles is positioned on the negative real axis in the z-domain. Now, the pole-zero mapping cannot be used. Therefore, as proposed in section 3, the bilinear transformation is used. This yields an acceptable G(s), but if the parameter values FInCi are further tuned it is possible to get even better results. These are presented in figure 8. Again the STFs for the FF-I, FF-II topology both with and without the first-order low-pass filter preceding the modulator show a very undesirable frequency response. The proposed topology of figure 5 the frequency response of the STF is almost flat (except for frequencies above fs /2) With the first-order (‘no-overload’) filter a very good frequency response is obtained. 15
STF FF-II
STF FF-I
10
STFFF-II,RC 5
dB
0
STFFF-I,RC
-5
this work
0
in, quant
int1
-10
int2
-20 dB -30 -40
int3 int4
-50 -60
10-1
f
100
Figure 9. Signal levels at the internal nodes of a FB topology. 6. CONCLUSIONS In this paper we proposed a way to obtain a ‘flat’ STF in a CT Σ∆ modulator. The proposed procedure and topology was tested on different designs, i.e. NTFs having different orders and aggressivity (e.g. H∞ [2] or Q [2, 3]). Compared to the traditional topologies the frequency response of the STF has been improved considerable. Preceded with a simple first-order low-pass filter out of band signals are nicely suppressed and like other CT modulators they still exhibit the implicit anti-aliasing filter. Meanwhile, the distortion requirements on the integrators remain modest as the signal levels at the output of the integrators remain small. 7. REFERENCES
-10 -15
10
this work RC -2
10
f
-1
10
0
10
Figure 8. Frequency responses for an NTF designed with [3]. Note that the subscript ‘RC’ stands for the fact that the modulator is preceded with a first-order filter. Finally, we present some simulation results with respect to the signal levels at the internal nodes of the modulator. The simulated modulator was the fourth order modulator of figure 7, with an ideal quantizer inserted in the loop in order to set the contribution of the quantization noise to zero. The input signal was a sine wave of which the frequency was varied between approximately zero and 2.5 fs . The simulated time domain maxima of the internal nodes’ signal levels (normalized to the amplitude of the input sine wave) are shown in figure 9. Shown in this figure are 5 curves: four of them correspond to the output of the integrators (numbered front to back), the last curve corresponds to the input of the quantizer. Note that, the actual signal levels in a modulator depend both on the scaling as well as on the chosen topology (FF versus FB). So, with the simulation results of figure 9 we want to show that these levels can be made small.
[1] J. De Maeyer, J. Raman, P. Rombouts, and L. Weyten, “Controlled Behavior of the STF in CT Σ∆ Modulators,” Electronics Letters, 2005, submitted. [2] R. Schreier, “An Emperical Study of Higher-Order Single-Bit Delta-Sigma Modulators,” IEEE Trans. Circuits Syst.-II, vol. 40, no. 8, pp. 461–466, Aug. 1993. [3] J. G. Kenney and L. R. Carley, “Desing of Mutlibit Noise-Shaping Data Converters,” Analog Integrated Circuits and Signal Processing, vol. 3, pp. 259–272, Apr. 1993. [4] R. Schreier and B. Zhang, “Delta-Sigma Modulators Employing Continuous-Time Circuitry,” IEEE Trans. Circuits Syst.-I, vol. 43, no. 4, pp. 324–332, Apr. 1996. [5] J. Silva, U. Moon, J. Steensgaard, and G.C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electronics Letters, vol. 37, no. 12, pp. 737–738, June 2001. [6] K. Philips, P. Nuyten, R. Roovers, F. Mu oz, M. Tejero, and A. Torralba, “A continuous-time Σ∆ ADC with increased immunity to wide-band interferers,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2170–2178, Dec. 2004. [7] Oppenheim A., V., Schafer R., W., and Buck J., R., Discrete-Time Signal Processing, Prentice-Hall International, 2nd edition, 1999.
this model the output of the modulator is: Vout (z) = [G(s)NTF(z)Vin (s)]∗ + Q(z)NTF(z)
(1)
Here, we used the fact that sampling a continuous time signal corresponds to taking the periodic extension of its frequency domain representation. Such a periodic extension of a signal with Laplace transformation A(s) has been denoted as [A(s)]∗ . Also in eq. (1), NTF(z) is the discrete time (DT) noise transfer function, which equals 1/(1 + ˜ ˜ H(z)), where H(z) is the DT equivalent of the CT loop filter H(s) and HDAC (s) [4]. A lot of research has been performed with respect to the second part of eq. (1) as it dictates the performance of the modulator. However, in this paper we concentrate on the first part of eq. (1). The importance of this first term has been recognized before in DT modulators [5] and recently in CT modulators as well as [6]. Q(z) Vin
G(s)
+
+ H(s)
HDAC(s)
Vout
Vin
STF
Q(z)
NTF
+
Vout
Figure 1. CT Σ∆ modulator, definition of NTF and STF. On the right of figure 1 the graphical equivalent of eq. (1) is shown. Besides quantization noise, at the output of the modulator a discrete time signal appears, which is the sampled version of the filtered input signal. The filter acting upon the input signal is the STF (see figure 1): STF(jω) = G(jω)NTF(ejω )
(2)
Let us now look at the STF for two very popular CT Σ∆ modulator topologies. These topologies essentially use a feedforward topology [2] and we will refer to them as FF-I and FF-II. The only difference between the two, is the presence (FF-I) or the absence (FF-II) of a direct path from the input of the modulator to the input of the quantizer. For the FF-I topology the input filter G1 (s) equals 1 + H(s), for FF-II G2 (s) = H(s). While, the DT FF-I topology leads to a STF which is identical to one [5], this is not the case for continuous time modulators. This is illustrated in figure 2, which shows 4 curves. The first is the NTF, which was designed using [2] for an H∞ = 2.5. With the
impulse invariant method (e.g. [4]) the corresponding DT loop filter was translated into a CT loop filter H(s), which is also shown in this figure. The last two curves display the STF for the FF-I and the FF-II topology. The bandwidth of the modulator (OSR of 16) is indicated as well. 20 15
STF FF-II
10
(zzk ), to corresponding CT poles (spk ) and zeros (szk ) according to zpk = espk T and zzk = eszk T (T = f1s ) . Note, that such an equivalence does not exist for negative real zeros/poles with odd multiplicity. In this case an acceptable G(s) is obtained by applying the bilinear transformation (with prewarp distortion) [7] to 1/NTF: 1 1+s/2 G(s) = (3) NTF(z) z= 1−s/2 20
5
15
G
0
10
STFFF-I
-5
H(s)
-10
5
fBW
-15
dB 0
NTF
-20 10
-2
f
10
-1
STF
-5 10
0
-10
fBW
-15
NTF
Figure 2. STF, NTF and H of a typical modulator. -20
Observing the STFs, roughly three regions can be observed. First, for signals in the frequency band of interest, in both the FF-I and FF-II case the STF approximates 1 very well. Second, for larger frequencies, the loop filter H(s) rapidly decreases and then behaves like a first-order filter. As a result in this frequency range G1 (s) approximates 1 for FF-I and G2 (s) ≈ 1 + as for FF-II. Meanwhile the NTF evolves to its maximum value of H∞ . Hence, STFFF-I evolves to the NTF, while STFFF-II first peaks and next behaves like a first-order filter. Third, for frequencies around multiples of fs , the frequency responses of the STFs are dominated by the zeros of the NTF. This leads to the well known (implicit) anti-aliasing filtering action of a CT Σ∆ modulator. In conclusion the frequency responses of both STFFF-I and STFFF-II exhibit a frequency range where the input signals are highly amplified. Hence, out of band signals in this frequency range can cause the input of the quantizer to become overloaded and the modulator unstable. To prevent this risk of instability, a kind of ‘no-overload’ filter should precede these modulators. As, for lower OSR the peaking of the STF occurs much closer to the bandwidth of the modulator, the requirements on this filter can become high. 3. DESIGN OF A FLAT STF In DT Σ∆ modulators, the FF-I structure results in a flat STF [5]. As shown above, this is not the case for CT modulators. However, based on eq. (2) it should be possible to approximate the STF to 1. The input filter G(s) that achieves this property has the same frequency response as 1/NTF. One possible way to obtain this G(s) is to perform a DT/CT pole-zero mapping on 1/NTF. This mapping includes the transformation of the DT poles (zpk ) and zeros
-2
10
-1
f
10
0
10
Figure 3. The resulting G, NTF and STF. For the third order Σ∆ modulator of the previous section, the frequency response of G(s) resulting from the proposed pole-zero mapping is shown in figure 3. Also shown in the figure are the frequency response of the NTF and the resulting STF. Clearly the frequency response of the signal transfer function is greatly improved compared to the STFFF-I and STFFF-II and can be denoted as a ‘flat’ STF. 4. IMPLEMENTATION OF G(S) The proposed procedure yields a G(s) which can be written as: G(s) =
aN sN + aN −1 sN −1 + a1 s + a0 , sN + bN −1 sN −1 + b1 s + b0
(4)
where N is the order of the modulator. Here, it should be noted that the poles of this G(s) are identical to the poles of the loop filter H(s). This general result is the basis of the proposed method as it allows the filter G(s) to be implemented using the (on chip) active components of the filter H(s). This is best illustrated for a modulator with a feedback (FB) topology. A third order variant is depicted in figure 4. Here, the denominator of both H(s) and G(s) equals s3 . The numerator of H(s) is set by the feedback parameters FBi , i ∈ {1, 2, 3}, while the numerator of G(s) is set by the parameters FIni , i ∈ {1, 2, 3, 4}. In the literature three special cases with frequency independent feed-in paths FIni , i ∈ {1, 2, 3, 4} are known. The first type is the purely feedback topology, which corresponds to FIn1 = FB1 and FIni = 0, i 6= 1. The second and
third type correspond to FIni = FBi , i ∈ {1, 2, 3}. With FIn4 = 1 the input filter is G(s) = 1 + H(s), cfr. FF-I. Making FIn4 = 0 yields G(s) = H(s), cfr. FF-II.
the right of figure 6 a possible gm -based implementation is depicted. (only resistor Ri is drawn). In both case the path corresponding to s · FInC is implemented with the capacitor Cin .
Vin
Vb b
FIn1(s)
FIn2(s)
FIn3(s)
Cin
FIn4(s) Vin
1 s
+
-
1 s
+
-
FB1
1 s
+
-
FB2
+
+
Ci
Rin Ri
Vi
-
RDAC
i
V Vin
Vi+1
-
Ci
(a)
Figure 4. A third order FB topology, with feed-in paths to realize the desired input filter G(s). The FB topology of figure 4 allows to implement any kind of G(s) as long as the denominator is s3 , like it is for the loop filter H(s). In principle it is sufficient to set the required feed-in paths FIni according to the numerator of G(s). Unfortunately, doing so leads to FIni 6= FBi . Hence, this would lead to the output of the integrators containing input related signal roughly proportional to the difference FIni − FBi . As shown in [5], this is not desirable with respect to the distortion requirements on the integrators of the loop filter. To prevent this while still being able to implement the desired filter G(s), we propose to make the feed-in paths frequency dependent, more specific: FIni (s) = FIni + s . FInCi . Next we set FIni = FBi which ensures that for s → 0, FIni (s) − FBi → 0. As a result at least for signals in the bandwidth of the modulator the signal levels at the internal nodes remain small. Simulation results of the signal levels at the internal nodes are presented in section 5. With the parameters FIni equal to FBi the parameters FInCi still leave enough freedom to implement the required filter G(s). Finally, note that the proposed FB topology can easily be transformed to a FF topology, like shown in figure 5. Vin
+
s.FInC2 1 s
+
s.FInC3 1 s
+
+
+
Vi+1
+
5. RESULTS Now that we have realized a ‘flat’ STF as shown in figure 3, we can investigate the behaviour of the modulator when it is preceded with a simple filter, e.g. a first-order low-pass filter. To illustrate this we compare the cascade of such a low-pass filter with different modulators. The bandwidth of the low-pass filter was chosen such that it does not attenuate signals in the signal band of interest with more then 0.3 dB. The results are shown in figure 7 and figure 8. For figure 7 a fourth order modulator was designed according to [2] with H∞ = 2.5 and OSR of 16. The resulting STFs for the FF-I and FF-II topology with and without the preceding first-order low-pass filter are shown in figure 7. As can be seen in this case their is a (large) frequency range of signals with a large amplification. Out of band signals in this frequency range can prohibit a correct operation of the modulator and lead to instability. At the same time in the proposed topology all out of band signals are nicely suppressed and the behavior of the transfer function from the input to the output of the system is much more desirable.
STF FF-I
STFFF-II,RC Vo u t
-
Figure 6. Possible circuit implementations.
Q(z) FF3 s
Vin Vb
(b)
10 s.FInC1
+
Vi+1
+
VDAC
HDAC(s)
V
+ i
Vb
Vo u t
FB3
Cin
Ri
Q(z)
STF FF-II
5
FF2 FF1
0 HDAC(s)
Figure 5. A third order FF topology, with feed-in paths to realize the desired input filter G(s).
dB
STFFF-I,RC
-5
-10
In figure 6 simple circuits are shown which can be used to implement the proposed frequency dependent feed-in paths. On the left of figure 6 a possible active-RC implementation is shown, resistor Ri provides the input path for the output of the previous integrator. RDAC and Rin do the same for the feedback signal resp. the input signal. They correspond to the parameters FBi resp. FIni . On
fBW -15
-2
10
f
this work RC 10
-1
10
0
Figure 7. Frequency responses for an NTF designed with [2]. Note that the subscript ‘RC’ stands for the fact that the modulator is preceded with a first-order filter.
In the design method of [2] the poles are placed in butterworth position, all with a positive real part. Furthermore, due to this butterworth position the NTF behaves ‘smoothly’. As a result the pole-zero mapping technique can be used and the results are excellent. In contrast with the above example, the NTF of the next example is designed with the CLANS method [3]. The following parameters orde = 3, OSR = 16, rmax = 0.95, Q = 4 [2] were used. This NTF behaves not as ‘smoothly’ and one of the poles is positioned on the negative real axis in the z-domain. Now, the pole-zero mapping cannot be used. Therefore, as proposed in section 3, the bilinear transformation is used. This yields an acceptable G(s), but if the parameter values FInCi are further tuned it is possible to get even better results. These are presented in figure 8. Again the STFs for the FF-I, FF-II topology both with and without the first-order low-pass filter preceding the modulator show a very undesirable frequency response. The proposed topology of figure 5 the frequency response of the STF is almost flat (except for frequencies above fs /2) With the first-order (‘no-overload’) filter a very good frequency response is obtained. 15
STF FF-II
STF FF-I
10
STFFF-II,RC 5
dB
0
STFFF-I,RC
-5
this work
0
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Figure 9. Signal levels at the internal nodes of a FB topology. 6. CONCLUSIONS In this paper we proposed a way to obtain a ‘flat’ STF in a CT Σ∆ modulator. The proposed procedure and topology was tested on different designs, i.e. NTFs having different orders and aggressivity (e.g. H∞ [2] or Q [2, 3]). Compared to the traditional topologies the frequency response of the STF has been improved considerable. Preceded with a simple first-order low-pass filter out of band signals are nicely suppressed and like other CT modulators they still exhibit the implicit anti-aliasing filter. Meanwhile, the distortion requirements on the integrators remain modest as the signal levels at the output of the integrators remain small. 7. REFERENCES
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Figure 8. Frequency responses for an NTF designed with [3]. Note that the subscript ‘RC’ stands for the fact that the modulator is preceded with a first-order filter. Finally, we present some simulation results with respect to the signal levels at the internal nodes of the modulator. The simulated modulator was the fourth order modulator of figure 7, with an ideal quantizer inserted in the loop in order to set the contribution of the quantization noise to zero. The input signal was a sine wave of which the frequency was varied between approximately zero and 2.5 fs . The simulated time domain maxima of the internal nodes’ signal levels (normalized to the amplitude of the input sine wave) are shown in figure 9. Shown in this figure are 5 curves: four of them correspond to the output of the integrators (numbered front to back), the last curve corresponds to the input of the quantizer. Note that, the actual signal levels in a modulator depend both on the scaling as well as on the chosen topology (FF versus FB). So, with the simulation results of figure 9 we want to show that these levels can be made small.
[1] J. De Maeyer, J. Raman, P. Rombouts, and L. Weyten, “Controlled Behavior of the STF in CT Σ∆ Modulators,” Electronics Letters, 2005, submitted. [2] R. Schreier, “An Emperical Study of Higher-Order Single-Bit Delta-Sigma Modulators,” IEEE Trans. Circuits Syst.-II, vol. 40, no. 8, pp. 461–466, Aug. 1993. [3] J. G. Kenney and L. R. Carley, “Desing of Mutlibit Noise-Shaping Data Converters,” Analog Integrated Circuits and Signal Processing, vol. 3, pp. 259–272, Apr. 1993. [4] R. Schreier and B. Zhang, “Delta-Sigma Modulators Employing Continuous-Time Circuitry,” IEEE Trans. Circuits Syst.-I, vol. 43, no. 4, pp. 324–332, Apr. 1996. [5] J. Silva, U. Moon, J. Steensgaard, and G.C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electronics Letters, vol. 37, no. 12, pp. 737–738, June 2001. [6] K. Philips, P. Nuyten, R. Roovers, F. Mu oz, M. Tejero, and A. Torralba, “A continuous-time Σ∆ ADC with increased immunity to wide-band interferers,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2170–2178, Dec. 2004. [7] Oppenheim A., V., Schafer R., W., and Buck J., R., Discrete-Time Signal Processing, Prentice-Hall International, 2nd edition, 1999.
