Subharmonic Analysis for Buck Converters With Constant On-Time ...
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
Subharmonic Analysis for Buck Converters With Constant On-Time Control and Ramp Compensation Ting Qian
Abstract—This paper presents a new subharmonic analysis for buck converters with constant on-time control and ramp compensation. For constant on-time control, subharmonic oscillation can be eliminated by adding a compensation ramp with a fixed slope during the off time and a fixed level during the on time. Based on the inductor current information, the compensation ramp, and the charge variations of the output capacitor, the minimum amount of compensation ramp to avoid subharmonic is derived, and the effect of circuit propagation delay is quantified. A prototype of buck converter is built by using constant on-time control with ramp compensation. Experimental results demonstrate the detailed theoretical analysis. Index Terms—Constant on-time control, ramp compensation, subharmonic.
I. I NTRODUCTION
W
ITH THE rapid development of modern power electronics, there is an increasing demand for the load transient response of nonisolated dc–dc converters. Conventional voltage- or current-mode control [1]–[8] usually has difficulty to obtain very fast load transient response due to loop speed limitation. To overcome the aforementioned challenge, constant on-time control has been widely used for power supply controllers in industry due to the benefits of fast load transient response and simple compensation [9]–[27]. The ripple voltage across the output capacitor equivalent series resistance (ESR) is utilized to regulate the output voltage. When step load change occurs, feedback of the output ripple voltage makes it possible to adjust the equivalent duty ratio promptly and thus minimize the output voltage overshoot or undershoot. Previously, several approaches [10]–[19] have been proposed to estimate the loop stability of constant on-time control by using small-signal models. The models in [10]–[14] are derived based on the pulse width modulation (PWM) model in [5], which is developed for peak-current control. The approach in [15] considers the influence of capacitor ripple to predict the subharmonic instability when low-ESR capacitors are utilized. Also, the Krylov–Bogoliubov–Mitropolsky algorithm is utilized to improve the accuracy of the model. More recently, Li and Lee [17], [18] and Wang et al. [19] have proposed small-signal modeling approaches to accurately predict the subharmonic
Manuscript received September 11, 2011; revised December 20, 2011; accepted January 29, 2012. Date of publication March 8, 2012; date of current version January 30, 2013. The author is with Texas Instruments, Warwick, RI 02886 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2012.2190375
oscillation for constant on-time control. According to them, there are also some restrictions for the basic constant on-time control due to the demand of certain ESR · Co value to avoid subharmonic oscillation. To eliminate subharmonic oscillation for buck converters, an effective solution is to add compensation ramp [12], [13], [15], [18], [21], which is often utilized by peak-current-mode control particularly when the duty ratio is over 50% [5], [6]. For constant on-time control, ramp compensation can be fulfilled by adding a ramp with a fixed level during the on time and a fixed slope during the off time. Of course, load transient performance can be affected by the added compensation ramp. There are design tradeoffs to be considered. Therefore, to avoid overcompensation in practical applications, it is important to understand and quantify the effect of the compensation ramp for constant on-time control. The purpose of this paper is to explore the subharmonic mechanism for buck converters with constant on-time control and ramp compensation. Specifically, the required minimum amount of compensation ramp to avoid subharmonic is derived, and the effect of circuit propagation delay is quantified. A thorough study is provided based on the inductor current information, the compensation ramp, and the charge variations of the output capacitor. According to the detailed analysis, the subharmonic can be avoided if the perturbation of the inductor current can be attenuated. The demand for the compensation ramp is determined by the gain of the output ripple voltage feedback, the slope of the inductor current during the off time, the output capacitance, the ESR of the output capacitor, the on time, and the total circuit propagation delay. In addition to that, experimental results demonstrate the theoretical analysis. II. O PERATION P RINCIPLE AND S UBHARMONIC A NALYSIS FOR C ONSTANT O N -T IME C ONTROL W ITH R AMP C OMPENSATION Fig. 1 shows the diagram of a buck converter using constant on-time control and ramp compensation. (Of course, it can also be fulfilled by using other equivalent approaches.) The principle for PWM regulation is described as follows: 1) The on time has a constant value, and 2) the off time is adjusted by comparing the output ripple voltage feedback (K · (Vref − vo )) with the compensation ramp. The output ripple voltage feedback is achieved by multiplying a constant value (K) with the difference of the output voltage (vo ) and the reference voltage (Vref ). The value of K determines the droop voltage between light- and heavy-load conditions. Hence, by adjusting the off time, the equivalent duty ratio is controlled for output voltage
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QIAN: ANALYSIS FOR BUCK CONVERTERS WITH CONSTANT ON-TIME CONTROL AND RAMP COMPENSATION
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aforementioned demand is not satisfied, the deviation will keep increasing until a minimum off time occurs in every two consecutive cycles. Therefore, the eventual subharmonic waveform shows as double pulses. The detailed analysis is presented in the following paragraphs. In Fig. 2, the compensation ramp has deviations of ΔVc0 , ΔVc1 , and ΔVc2 at t3 , t8 , and t13 , respectively. Because the slope of the inductor current is S2 during the off time, the length of t1 −t3 is represented as (ΔI + ΔI0 + ΔI1 ) · (1/S2 ) (according to Fig. 2). Therefore, the time difference between the length of t1 −t3 and the steady-state off time (ΔI · (1/S2 )) is equal to (ΔI0 + ΔI1 ) · (1/S2 ). The value of ΔVc0 can be derived as (1) by multiplying the aforementioned time difference with Mc . Similarly, ΔVc1 and ΔVc2 can be expressed as (2) and (3), respectively
Fig. 1.
Diagram of constant on-time control with ramp compensation caption.
regulation. If a resistor divider is used for the output voltage feedback, its gain is included by the value of K. Fig. 2 shows the dynamic waveforms related with the circuit in Fig. 1 when the inductor current is perturbed. Specifically, the waveforms of the inductor current, the compensation ramp, the output ripple voltage feedback [K · (Vref − vo )], and the PWM signal are included. The inductor current and PWM duty cycle fluctuate over and below the steady-state value in two consecutive cycles. The inductor current increases and decreases with slopes of S1 = (vin − vo )/L and S2 = vo /L, respectively. (Since the ripples of vin and vo are relatively negligible in comparison with their dc values, S1 and S2 are approximated to be constant values.) ΔI is the peak-to-peak inductor current ripple at steady state, and Ton is the on time with a constant value. The compensation ramp has a fixed value during the on time and decreases with a slope of Mc during the off time. The shadowed current-time areas represent the amounts of charge variations on the output capacitor defined as ΔQ1 −ΔQ8 , respectively. Also, the time points that K · (Vref − vo ) reaches the compensation ramp are defined as t2 , t7 , and t12 for the three consecutive cycles. The circuit propagation delay Δt is defined as the time interval from the time that K · (Vref − vo ) reaches the compensation ramp to the end of the off time. It is mainly determined by the comparator propagation delay and the driver delay. The subharmonic analysis is based on the inductor current information, the compensation ramp, and the charge variations of the output capacitor. As shown in Fig. 2, the inductor current is perturbed, and the deviations from the steady-state value are equal to ΔI0 at t0 . The deviations are ΔI1 , ΔI2 , and ΔI3 at the end of the following three consecutive cycles. Subharmonic oscillation can be avoided when the deviation is attenuated, which implies that ΔI0 > ΔI1 > ΔI2 > ΔI3 . Based on the relations between ΔI0 , ΔI1 , ΔI2 , and ΔI3 , it is concluded that subharmonic oscillation can be avoided when the slope of the compensation ramp (Mc ) is higher than ((K · S2 )/(2 · Co )) · ((Ton /2) + Δt − ESR · Co ). If the
ΔVc0 = (ΔI0 + ΔI1 ) ·
Mc S2
(1)
ΔVc1 = (ΔI1 + ΔI2 ) ·
Mc S2
(2)
ΔVc2 = (ΔI2 + ΔI3 ) ·
Mc . S2
(3)
First Cycle: The first switching cycle starts at time t0 and finishes at time t3 . According to Fig. 2, K · (Vref − vo ) reaches the compensation ramp at t2 , but the inductor current starts to increase at t3 due to circuit propagation delay. The length of t2 −t3 is equal to Δt. The deviations of the inductor current from the steady-state value are equal to ΔI0 and ΔI1 at time t0 and t3 , respectively. Second Cycle: The second switching cycle starts at time t3 and finishes at time t8 . Because the on time is constant, the increment of the inductor current during the on time is still equal to the peak-to-peak inductor current ripple at steady state ΔI. Therefore, the deviation of the inductor current from the steady-state value is still equal to ΔI1 at the end of the on time t5 . K · (Vref − vo ) reaches the compensation ramp at t7 . Then, with a delay of Δt, the switching cycle finishes at time t8 . Since K · (Vref − vo ) and the compensation ramp are equal at t2 and t7 , they have the same amount of changes during the interval of t2 −t7 . According to Fig. 2, the change of K · (Vref − vo ) is equal to K · [((ΔQ1 + ΔQ2 + ΔQ4 − ΔQ3 )/Co ) − (ΔI1 + ΔI2 ) · ESR], and the change of the compensation ramp is equal to ΔVc0 + ΔVc1 . Thus, the relation between charge variations and inductor current deviations can be derived ΔQ1 + ΔQ2 + ΔQ4 − ΔQ3 Co Mc 1 ΔVc0 · = (ΔI1 + ΔI2 ) · ESR + + K S2 K
(4)
where the charge variation divided by the capacitance value is equal to the capacitor ripple voltage. ESR represents the ESR of the output capacitor, and Co is the capacitance of the output capacitor.
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Fig. 2. Waveforms of a buck converter with constant on-time control and ramp compensation.
According to Fig. 2, the amounts of charge variations are derived as ΔI S2 · Δt + ΔI1 − ΔQ1 = · Δt (5) 2 2 ΔQ2 =
1 · 2
ΔQ3 =
1 · 2
ΔQ4 =
1 · 2
ΔI + ΔI1 2
2 ·
1 S1
2 ·
1 . S2
ΔI1 =
1+2·
ΔVc0 Mc Ton + Δt − · Co . · Co > K · S2 2 2 · K · ΔI1 (11)
Also, according to (1) and the demand of ΔI0 > ΔI1 > ΔI2 ΔVc0 (ΔI0 + ΔI1 ) · Mc Mc · Co = · Co > . 2 · K · ΔI1 2 · K · ΔI1 · S2 K · S2
(7)
(8)
Assume that N is equal to (ESR + (Mc /(K · S2 )) − (Δt/ Co )) · Co · S2 . By combining (4)–(8), (9) is derived, shown at the bottom of the page. Thus, the relation between ΔI1 and
ΔI12 −
ESR +
(6)
2 ΔI 1 1 − ΔI1 · + 2 S1 S2 ΔI − ΔI2 − S2 · Δt 2
ΔI2 can be represented as (10), also shown at the bottom of the page. According to (10), ΔI1 is larger than ΔI2 when
(12)
The value of (ΔVc0 /(2 · K · ΔI1 )) · Co is equal to (Mc / (K · S2 )) at critical condition (ΔI0 = ΔI1 = ΔI2 ). Also, based on (4)–(8), the decrease in ΔI2 leads to the increase in ESR + (Mc /(K · S2 )) with the same S1 , S2 , ΔI, ΔVc0 , and ΔI1 values.
S2 ΔVc0 ·Co ·S2 = 0 ·ΔI −2·N ·ΔI1 −ΔI22 +ΔI ·ΔI2 +2·N ·ΔI2 +2· S1 K
2 c0 1+2· SS21 ·ΔI −2·N −4· −ΔI22 +ΔI ·ΔI2 +2·N ·ΔI2 +2· ΔV 1+2· SS21 ·ΔI −2·N − K ·Co ·S2 2
(9)
(10)
QIAN: ANALYSIS FOR BUCK CONVERTERS WITH CONSTANT ON-TIME CONTROL AND RAMP COMPENSATION
As a result, the following formula is derived to satisfy the demand of ΔI0 > ΔI1 > ΔI2 by combining (11) and (12) ESR +
2Mc K · S2
· Co >
Ton + Δt. 2
(13)
Third Cycle: Similarly, the third switching cycle starts at time t8 and ends at time t13 . Due to the constant on time, the differences between the actual inductor current and the steadystate value are still equal to ΔI2 at both the beginning and the end of the on time (t8 and t10 ). K · (Vref − vo ) reaches the compensation ramp at t12 . Then, with a delay of Δt, the switching cycle finishes at time t13 . Since K · (Vref − vo ) and the compensation ramp are equal at t7 and t12 , they have the same amount of changes during the interval of t7 −t12 . From t7 to t12 , the change of K · (Vref − vo ) is equal to K · [((ΔQ5 + ΔQ6 + ΔQ8 − ΔQ7 )/Co ) − (ΔI2 + ΔI3 ) · ESR], and the change of the compensation ramp is equal to −(ΔVc1 + ΔVc2 ). Thus, the relation between charge variations and inductor current deviations is derived ΔQ5 + ΔQ6 + ΔQ8 − ΔQ7 Co Mc 1 ΔVc1 · . = (ΔI2 + ΔI3 ) · ESR − − K S2 K
(14)
According to Fig. 2, the amounts of charge variations are determined by ΔI S2 · Δt − ΔI2 − ΔQ5 = · Δt (15) 2 2 1 ΔQ6 = · 2 ΔQ7 =
1 · 2
ΔQ8 =
1 · 2
ΔI − ΔI2 2 ΔI + ΔI2 2
2 ·
1 S1
(16)
2 1 1 · + S1 S2
ΔI + ΔI3 − S2 · Δt 2
2 ·
1 . S2
(17)
(18)
Similar to the calculation for the Second Cycle, by combining (14)–(18), it is concluded that ΔI2 is larger than ΔI3 when ΔVc1 Mc Ton + Δt − ESR+ · Co . · Co > K · S2 2 2 · K · ΔI2 (19) Also, according to (2) and the demand of ΔI1 > ΔI2 > ΔI3 ΔVc1 (ΔI1 + ΔI2 ) · Mc Mc · Co = · Co > . 2 · K · ΔI2 2 · K · ΔI2 · S2 K · S2
(20)
Combining (19) and (20), ΔI1 > ΔI2 > ΔI3 is satisfied when
2Mc ESR + K · S2
· Co >
Ton + Δt. 2
(21)
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Summary: Based on (13) and (21), the demand for the slope of the compensation ramp is obtained to satisfy ΔI0 > ΔI1 > ΔI2 > ΔI3 K · S2 Ton + Δt − ESR · Co . Mc > · (22) 2 · Co 2 Alternatively, this implies that subharmonic can be avoided when the slope of the compensation ramp (Mc ) is higher than ((K · S2 )/(2 · Co )) · ((Ton /2) + Δt − ESR · Co ). By using (22), the minimum amount of compensation ramp to avoid subharmonic is calculated based on power stage and control circuit parameters, which are usually determined first for buck converter design. Then, the estimated result is utilized to choose proper compensation ramp. Generally, the actual slope of the compensation ramp is recommended to be two to four times of the estimated minimum value in order to keep some design margin. On the other hand, an increased compensation ramp is beneficial for stability at the penalty of slower load transient response. The upper limit of the compensation ramp is usually determined by the load transient requirement of the specific application and can be measured based on experimental or simulation results. The condition of “overcompensation” occurs when excessive ramp compensation prevents the converter from achieving the required load transient response. It should be noted that parameter redesign is needed if the desired load transient response is still not achievable with the estimated minimum compensation ramp. Increasing output capacitance and decreasing output inductance are effective solutions to improve the load transient response. III. E XPERIMENTAL R ESULTS To verify the proposed subharmonic analysis for constant on-time control with ramp compensation, a prototype of buck converter is built by using discrete components for the control circuit. The detailed specification is shown as follows: 1) input voltage: 12 V; 2) output voltage: 1.2 V; 3) load current: 3 A; 4) switching frequency: 200 kHz. Fig. 3 shows the detailed circuit diagram used for experimental verification. The value of K is equal to R1 /R2 , which is set to six. The inductor has 1-μH inductance with a direct current resistance of 5.6 mΩ. The total output capacitance value is 88 μF. ESR is adjusted by connecting various highprecision resistors (milliohm-level resistance) in series with the capacitors. The comparator utilizes MAX942 with 80-ns propagation delay. ISL6612 is utilized as the driver. The total circuit propagation delay (Δt) is shown as 118 ns in Fig. 4. The experimental results are summarized in Table I, and the detailed waveforms are shown in Figs. 5 and 6. Notice that all the results match the conclusion in (22). Fig. 5 shows the waveforms when the ESR is 1 mΩ. The value of ESR · Co is approximately 88 ns, and Ton is approximately 500 ns. S2 = vo /L is equal to 1.2 A/μs. According to (22), Mc is required to be higher than 11.5 mV/μs in order to
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Fig. 3. Circuit diagram of the prototype for experimental verification (buck converter using constant on-time control with ramp compensation).
Fig. 4. Waveforms to show the total circuit propagation delay. The measured circuit propagation delay is 118 ns (MAX942 was used as a comparator for off time regulation). CH1: Input pulse for the control circuit (1 V/div). CH2: Output pulse for the control circuit (5 V/div). TABLE I S TABILITY OF C ONSTANT O N -T IME C ONTROL W ITH E XTERNAL C OMPENSATION R AMP AT VARIOUS C ONDITIONS
Fig. 5. Waveforms to explain the subharmonic mechanism for constant ontime control with ramp compensation (ESR = 1 mΩ): (a) Mc = 6.4 mV/μs, (b) Mc = 9.2 mV/μs, and (c) Mc = 15 mV/μs. CH1: V out ripple (200 mV/div). CH2: switch node voltage (SW) (5 V/div). CH3: Inductor current (5 A/div). CH4: Output of the compensation ramp generator (200 mV/div). (2 μs/div.) Mc is the change rate of the external compensation ramp, which is connected to the inverting input of the comparator in Fig. 3. Mc can be derived by multiplying R4 /(R3 + R4 ) with the change rate of the compensation ramp generator output. R4 /(R3 + R4 ) is set to 0.2.
avoid subharmonic. The conclusion is demonstrated in various conditions by the following examples. Fig. 5(a) is measured when Mc is equal to 6.4 mV/μs, which is lower than the required 11.5 mV/μs. The perturbation is unable to decrease with time, and subharmonic occurs.
Fig. 5(b) shows the waveform when Mc is equal to 9.2 mV/μs, which is also lower than 11.5 mV/μs. Subharmonic still occurs in this case.
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Fig. 6 shows the waveforms when the ESR is 3 mΩ. The value of ESR · Co is approximately 264 ns, and Ton is approximately 500 ns. S2 = vo /L is equal to 1.2 A/μs. Based on (22), the value of Mc is required to be higher than 4.25 mV/μs in order to avoid subharmonic. Fig. 6(a) is measured when Mc is equal to 3 mV/μs, which is lower than the required 4.25 mV/μs. Thus, subharmonic occurs. Fig. 6(b) is measured when Mc is 4 mV/μs, which is also lower than 4.25 mV/μs. Therefore, subharmonic still occurs. Fig. 6(c) shows the waveform without subharmonic. In this case, Mc is equal to 6 mV/μs, which is higher than 4.25 mV/μs.
IV. C ONCLUSION This paper has provided detailed analysis to explore the subharmonic mechanism for buck converters with constant ontime control and ramp compensation. For constant on-time control, ramp compensation can be fulfilled by utilizing a ramp with a fixed slope during the off time and a fixed level during the on time. Based on the inductor current information and the charge variations of the output capacitor, the effect of the compensation ramp is quantified. Also, the effect of circuit propagation delay is considered. Experimental results demonstrate the subharmonic mechanism for constant on-time control with ramp compensation. R EFERENCES
Fig. 6. Waveforms to explain the subharmonic mechanism for constant on-time control with ramp compensation (ESR = 3 mΩ): (a) Mc = 3 mV/μs, (b) Mc = 4 mV/μs, and (c) Mc = 6 mV/μs. CH1: V out ripple (200 mV/div). CH2: SW (5 V/div). CH3: Inductor current (5 A/div). CH4: Output of the compensation ramp generator (100 mV/div). (2 μs/div.) Mc is the change rate of the external compensation ramp, which is connected to the inverting input of the comparator in Fig. 3. Mc can be derived by multiplying R4 /(R3 + R4 ) with the change rate of the compensation ramp generator output. R4 /(R3 + R4 ) is set to 0.2.
Fig. 5(c) shows the waveform when Mc is equal to 15 mV/μs, which is higher than 11.5 mV/μs. Therefore, no subharmonic occurs.
[1] R. Redl and N. O. Sokal, “Current-mode control, five different types, used with the three basic classes of power converters: Small-signal ac and largesignal dc characterization, stability requirements, and implementation of practical circuits,” in Proc. IEEE PESC, 1985, pp. 771–785. [2] B. P. Schweitzer and A. B. Rosenstein, “Free running switching mode power regulator: Analysis and design,” IEEE Trans. Aerosp., vol. AS-2, no. 4, pp. 1171–1180, Oct. 1964. [3] L. H. Dixon, “Average current-mode control of switching power supplies,” Unitrode Power Supply Design Seminar Handbook, pp. 5.1–5.14, 1990. [4] F. D. Tan and R. D. Middlebrook, “A unified model for currentprogrammed converters,” IEEE Trans. Power Electron., vol. 10, no. 4, pp. 397–408, Jul. 1995. [5] R. B. Ridley, “A new, continuous-time model for current-mode control [power converters],” IEEE Trans. Power Electron., vol. 6, no. 2, pp. 271– 280, Apr. 1991. [6] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics. Norwell, MA: Kluwer, 2001. [7] Y. Qiu, H. Liu, and X. Chen, “Digital average current-mode control of PWM dc–dc converters without current sensors,” IEEE Trans. Ind. Electron., vol. 57, no. 5, pp. 1670–1677, May 2010. [8] S.-Y. Chen and J.-J. Chen, “Study of the effect and design criteria of the input filter for buck converters with peak current-mode control using a novel system block diagram,” IEEE Trans. Ind. Electron., vol. 55, no. 8, pp. 3159–3166, Aug. 2008. [9] D. Goder, “Switching regulators,” U.S. Patent 5 770 940, Jun. 23, 1998. [10] D. Goder and W. R. Pelletier, “V2 architecture provides ultra-fast transient response in switch mode power supplies,” in Proc. HFPC, 1996, pp. 414–420. [11] R. B. Ridley, “A new continuous-time model for current-mode control with constant on-time, constant off-time, and discontinuous conduction mode,” in Proc. IEEE Power Electron. Spec. Conf., 1990, pp. 382–389. [12] W. Huang and J. Clarkin, “Analysis and design of multiphase synchronous buck converter with enhanced V2 control,” in Proc. HFPC, 2000, pp. 74–81. [13] W. Huang, “A new control for multi-phase buck converter with fast transient response,” in Proc. IEEE APEC, 2001, pp. 273–279.
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[14] S. Qu, “Modeling and design considerations of V2 controlled buck regulator,” in Proc. IEEE APEC, 2001, pp. 507–513. [15] J. Sun, “Characterization and performance comparison of ripple-based control for voltage regulator modules,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 346–353, Mar. 2006. [16] J. Sun, “Small-signal modeling of variable-frequency pulsewidth modulators,” IEEE Trans. Aerosp. Electron. Syst., vol. 38, no. 3, pp. 1104–1108, Jul. 2002. [17] J. Li and F. C. Lee, “Modeling of V2 current-mode control,” in Proc. IEEE APEC, 2009, pp. 298–304. [18] J. Li and F. C. Lee, “New modeling approach and equivalent circuit representation for current-mode control,” IEEE Trans. Power Electron., vol. 25, no. 5, pp. 1218–1230, May 2010. [19] J. Wang, J. Xu, and B. Bao, “Analysis of pulse bursting phenomenon in constant on-time controlled buck converter,” IEEE Trans. Ind. Electron., vol. 58, no. 12, pp. 5406–5410, Dec. 2011. [20] L. K. Wong and T. K. Man, “Maximum frequency for hysteretic control COT buck converters,” in Proc. Power Electron. Motion Control Conf., 2008, pp. 475–478. [21] R. Redl and J. Sun, “Ripple-based control of switching regulators—An overview,” IEEE Trans. Power Electron., vol. 24, no. 12, pp. 2669–2680, Dec. 2009. [22] X. Duan and A. Q. Huang, “Current-mode variable-frequency control architecture for high-current low-voltage dc–dc converters,” IEEE Trans. Power Electron., vol. 21, no. 4, pp. 1133–1137, Jul. 2006. [23] Y.-F. Liu and X. Liu, “Recent developments in digital control strategies for dc/dc switching power converters,” in Proc. Power Electron. Motion Control Conf., 2009, pp. 307–314.
[24] Texas Instruments Corporation, Dallas, TX, 2009, Texas Instruments, TPS51116 datasheet. [Online]. Available: http://focus.ti.com/lit/ds/ symlink/tps51116.pdf [25] C.-A. Yeh and Y.-S. Lai, “Digital pulsewidth modulation technique for a synchronous buck dc/dc converter to reduce switching frequency,” IEEE Trans. Ind. Electron., vol. 59, no. 1, pp. 550–561, Jan. 2012. [26] L. K. Wong and T. K. Man, “Adaptive on-time converters,” IEEE Ind. Electron. Mag., vol. 4, no. 3, pp. 28–35, Sep. 2010. [27] S. Concepción Huerta, P. Alou, J. A. Oliver, O. Garcia, J. A. Cobos, and A. M. Abou-Alfotouh, “Nonlinear control for dc–dc converters based on hysteresis of the COUT current with a frequency loop to operate at constant frequency,” IEEE Trans. Ind. Electron., vol. 58, no. 3, pp. 1036– 1043, Mar. 2011.
Ting Qian received the B.S. and M.S. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 1999 and 2002, respectively, and the Ph.D. degree in electrical engineering from Northeastern University, Boston, MA, in 2007. He is currently with Texas Instruments, Warwick, RI. His research interests include power converter topologies, on-chip integration and control schemes of power converters, active power filters, and digital control on power electronics.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
Subharmonic Analysis for Buck Converters With Constant On-Time Control and Ramp Compensation Ting Qian
Abstract—This paper presents a new subharmonic analysis for buck converters with constant on-time control and ramp compensation. For constant on-time control, subharmonic oscillation can be eliminated by adding a compensation ramp with a fixed slope during the off time and a fixed level during the on time. Based on the inductor current information, the compensation ramp, and the charge variations of the output capacitor, the minimum amount of compensation ramp to avoid subharmonic is derived, and the effect of circuit propagation delay is quantified. A prototype of buck converter is built by using constant on-time control with ramp compensation. Experimental results demonstrate the detailed theoretical analysis. Index Terms—Constant on-time control, ramp compensation, subharmonic.
I. I NTRODUCTION
W
ITH THE rapid development of modern power electronics, there is an increasing demand for the load transient response of nonisolated dc–dc converters. Conventional voltage- or current-mode control [1]–[8] usually has difficulty to obtain very fast load transient response due to loop speed limitation. To overcome the aforementioned challenge, constant on-time control has been widely used for power supply controllers in industry due to the benefits of fast load transient response and simple compensation [9]–[27]. The ripple voltage across the output capacitor equivalent series resistance (ESR) is utilized to regulate the output voltage. When step load change occurs, feedback of the output ripple voltage makes it possible to adjust the equivalent duty ratio promptly and thus minimize the output voltage overshoot or undershoot. Previously, several approaches [10]–[19] have been proposed to estimate the loop stability of constant on-time control by using small-signal models. The models in [10]–[14] are derived based on the pulse width modulation (PWM) model in [5], which is developed for peak-current control. The approach in [15] considers the influence of capacitor ripple to predict the subharmonic instability when low-ESR capacitors are utilized. Also, the Krylov–Bogoliubov–Mitropolsky algorithm is utilized to improve the accuracy of the model. More recently, Li and Lee [17], [18] and Wang et al. [19] have proposed small-signal modeling approaches to accurately predict the subharmonic
Manuscript received September 11, 2011; revised December 20, 2011; accepted January 29, 2012. Date of publication March 8, 2012; date of current version January 30, 2013. The author is with Texas Instruments, Warwick, RI 02886 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2012.2190375
oscillation for constant on-time control. According to them, there are also some restrictions for the basic constant on-time control due to the demand of certain ESR · Co value to avoid subharmonic oscillation. To eliminate subharmonic oscillation for buck converters, an effective solution is to add compensation ramp [12], [13], [15], [18], [21], which is often utilized by peak-current-mode control particularly when the duty ratio is over 50% [5], [6]. For constant on-time control, ramp compensation can be fulfilled by adding a ramp with a fixed level during the on time and a fixed slope during the off time. Of course, load transient performance can be affected by the added compensation ramp. There are design tradeoffs to be considered. Therefore, to avoid overcompensation in practical applications, it is important to understand and quantify the effect of the compensation ramp for constant on-time control. The purpose of this paper is to explore the subharmonic mechanism for buck converters with constant on-time control and ramp compensation. Specifically, the required minimum amount of compensation ramp to avoid subharmonic is derived, and the effect of circuit propagation delay is quantified. A thorough study is provided based on the inductor current information, the compensation ramp, and the charge variations of the output capacitor. According to the detailed analysis, the subharmonic can be avoided if the perturbation of the inductor current can be attenuated. The demand for the compensation ramp is determined by the gain of the output ripple voltage feedback, the slope of the inductor current during the off time, the output capacitance, the ESR of the output capacitor, the on time, and the total circuit propagation delay. In addition to that, experimental results demonstrate the theoretical analysis. II. O PERATION P RINCIPLE AND S UBHARMONIC A NALYSIS FOR C ONSTANT O N -T IME C ONTROL W ITH R AMP C OMPENSATION Fig. 1 shows the diagram of a buck converter using constant on-time control and ramp compensation. (Of course, it can also be fulfilled by using other equivalent approaches.) The principle for PWM regulation is described as follows: 1) The on time has a constant value, and 2) the off time is adjusted by comparing the output ripple voltage feedback (K · (Vref − vo )) with the compensation ramp. The output ripple voltage feedback is achieved by multiplying a constant value (K) with the difference of the output voltage (vo ) and the reference voltage (Vref ). The value of K determines the droop voltage between light- and heavy-load conditions. Hence, by adjusting the off time, the equivalent duty ratio is controlled for output voltage
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aforementioned demand is not satisfied, the deviation will keep increasing until a minimum off time occurs in every two consecutive cycles. Therefore, the eventual subharmonic waveform shows as double pulses. The detailed analysis is presented in the following paragraphs. In Fig. 2, the compensation ramp has deviations of ΔVc0 , ΔVc1 , and ΔVc2 at t3 , t8 , and t13 , respectively. Because the slope of the inductor current is S2 during the off time, the length of t1 −t3 is represented as (ΔI + ΔI0 + ΔI1 ) · (1/S2 ) (according to Fig. 2). Therefore, the time difference between the length of t1 −t3 and the steady-state off time (ΔI · (1/S2 )) is equal to (ΔI0 + ΔI1 ) · (1/S2 ). The value of ΔVc0 can be derived as (1) by multiplying the aforementioned time difference with Mc . Similarly, ΔVc1 and ΔVc2 can be expressed as (2) and (3), respectively
Fig. 1.
Diagram of constant on-time control with ramp compensation caption.
regulation. If a resistor divider is used for the output voltage feedback, its gain is included by the value of K. Fig. 2 shows the dynamic waveforms related with the circuit in Fig. 1 when the inductor current is perturbed. Specifically, the waveforms of the inductor current, the compensation ramp, the output ripple voltage feedback [K · (Vref − vo )], and the PWM signal are included. The inductor current and PWM duty cycle fluctuate over and below the steady-state value in two consecutive cycles. The inductor current increases and decreases with slopes of S1 = (vin − vo )/L and S2 = vo /L, respectively. (Since the ripples of vin and vo are relatively negligible in comparison with their dc values, S1 and S2 are approximated to be constant values.) ΔI is the peak-to-peak inductor current ripple at steady state, and Ton is the on time with a constant value. The compensation ramp has a fixed value during the on time and decreases with a slope of Mc during the off time. The shadowed current-time areas represent the amounts of charge variations on the output capacitor defined as ΔQ1 −ΔQ8 , respectively. Also, the time points that K · (Vref − vo ) reaches the compensation ramp are defined as t2 , t7 , and t12 for the three consecutive cycles. The circuit propagation delay Δt is defined as the time interval from the time that K · (Vref − vo ) reaches the compensation ramp to the end of the off time. It is mainly determined by the comparator propagation delay and the driver delay. The subharmonic analysis is based on the inductor current information, the compensation ramp, and the charge variations of the output capacitor. As shown in Fig. 2, the inductor current is perturbed, and the deviations from the steady-state value are equal to ΔI0 at t0 . The deviations are ΔI1 , ΔI2 , and ΔI3 at the end of the following three consecutive cycles. Subharmonic oscillation can be avoided when the deviation is attenuated, which implies that ΔI0 > ΔI1 > ΔI2 > ΔI3 . Based on the relations between ΔI0 , ΔI1 , ΔI2 , and ΔI3 , it is concluded that subharmonic oscillation can be avoided when the slope of the compensation ramp (Mc ) is higher than ((K · S2 )/(2 · Co )) · ((Ton /2) + Δt − ESR · Co ). If the
ΔVc0 = (ΔI0 + ΔI1 ) ·
Mc S2
(1)
ΔVc1 = (ΔI1 + ΔI2 ) ·
Mc S2
(2)
ΔVc2 = (ΔI2 + ΔI3 ) ·
Mc . S2
(3)
First Cycle: The first switching cycle starts at time t0 and finishes at time t3 . According to Fig. 2, K · (Vref − vo ) reaches the compensation ramp at t2 , but the inductor current starts to increase at t3 due to circuit propagation delay. The length of t2 −t3 is equal to Δt. The deviations of the inductor current from the steady-state value are equal to ΔI0 and ΔI1 at time t0 and t3 , respectively. Second Cycle: The second switching cycle starts at time t3 and finishes at time t8 . Because the on time is constant, the increment of the inductor current during the on time is still equal to the peak-to-peak inductor current ripple at steady state ΔI. Therefore, the deviation of the inductor current from the steady-state value is still equal to ΔI1 at the end of the on time t5 . K · (Vref − vo ) reaches the compensation ramp at t7 . Then, with a delay of Δt, the switching cycle finishes at time t8 . Since K · (Vref − vo ) and the compensation ramp are equal at t2 and t7 , they have the same amount of changes during the interval of t2 −t7 . According to Fig. 2, the change of K · (Vref − vo ) is equal to K · [((ΔQ1 + ΔQ2 + ΔQ4 − ΔQ3 )/Co ) − (ΔI1 + ΔI2 ) · ESR], and the change of the compensation ramp is equal to ΔVc0 + ΔVc1 . Thus, the relation between charge variations and inductor current deviations can be derived ΔQ1 + ΔQ2 + ΔQ4 − ΔQ3 Co Mc 1 ΔVc0 · = (ΔI1 + ΔI2 ) · ESR + + K S2 K
(4)
where the charge variation divided by the capacitance value is equal to the capacitor ripple voltage. ESR represents the ESR of the output capacitor, and Co is the capacitance of the output capacitor.
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Fig. 2. Waveforms of a buck converter with constant on-time control and ramp compensation.
According to Fig. 2, the amounts of charge variations are derived as ΔI S2 · Δt + ΔI1 − ΔQ1 = · Δt (5) 2 2 ΔQ2 =
1 · 2
ΔQ3 =
1 · 2
ΔQ4 =
1 · 2
ΔI + ΔI1 2
2 ·
1 S1
2 ·
1 . S2
ΔI1 =
1+2·
ΔVc0 Mc Ton + Δt − · Co . · Co > K · S2 2 2 · K · ΔI1 (11)
Also, according to (1) and the demand of ΔI0 > ΔI1 > ΔI2 ΔVc0 (ΔI0 + ΔI1 ) · Mc Mc · Co = · Co > . 2 · K · ΔI1 2 · K · ΔI1 · S2 K · S2
(7)
(8)
Assume that N is equal to (ESR + (Mc /(K · S2 )) − (Δt/ Co )) · Co · S2 . By combining (4)–(8), (9) is derived, shown at the bottom of the page. Thus, the relation between ΔI1 and
ΔI12 −
ESR +
(6)
2 ΔI 1 1 − ΔI1 · + 2 S1 S2 ΔI − ΔI2 − S2 · Δt 2
ΔI2 can be represented as (10), also shown at the bottom of the page. According to (10), ΔI1 is larger than ΔI2 when
(12)
The value of (ΔVc0 /(2 · K · ΔI1 )) · Co is equal to (Mc / (K · S2 )) at critical condition (ΔI0 = ΔI1 = ΔI2 ). Also, based on (4)–(8), the decrease in ΔI2 leads to the increase in ESR + (Mc /(K · S2 )) with the same S1 , S2 , ΔI, ΔVc0 , and ΔI1 values.
S2 ΔVc0 ·Co ·S2 = 0 ·ΔI −2·N ·ΔI1 −ΔI22 +ΔI ·ΔI2 +2·N ·ΔI2 +2· S1 K
2 c0 1+2· SS21 ·ΔI −2·N −4· −ΔI22 +ΔI ·ΔI2 +2·N ·ΔI2 +2· ΔV 1+2· SS21 ·ΔI −2·N − K ·Co ·S2 2
(9)
(10)
QIAN: ANALYSIS FOR BUCK CONVERTERS WITH CONSTANT ON-TIME CONTROL AND RAMP COMPENSATION
As a result, the following formula is derived to satisfy the demand of ΔI0 > ΔI1 > ΔI2 by combining (11) and (12) ESR +
2Mc K · S2
· Co >
Ton + Δt. 2
(13)
Third Cycle: Similarly, the third switching cycle starts at time t8 and ends at time t13 . Due to the constant on time, the differences between the actual inductor current and the steadystate value are still equal to ΔI2 at both the beginning and the end of the on time (t8 and t10 ). K · (Vref − vo ) reaches the compensation ramp at t12 . Then, with a delay of Δt, the switching cycle finishes at time t13 . Since K · (Vref − vo ) and the compensation ramp are equal at t7 and t12 , they have the same amount of changes during the interval of t7 −t12 . From t7 to t12 , the change of K · (Vref − vo ) is equal to K · [((ΔQ5 + ΔQ6 + ΔQ8 − ΔQ7 )/Co ) − (ΔI2 + ΔI3 ) · ESR], and the change of the compensation ramp is equal to −(ΔVc1 + ΔVc2 ). Thus, the relation between charge variations and inductor current deviations is derived ΔQ5 + ΔQ6 + ΔQ8 − ΔQ7 Co Mc 1 ΔVc1 · . = (ΔI2 + ΔI3 ) · ESR − − K S2 K
(14)
According to Fig. 2, the amounts of charge variations are determined by ΔI S2 · Δt − ΔI2 − ΔQ5 = · Δt (15) 2 2 1 ΔQ6 = · 2 ΔQ7 =
1 · 2
ΔQ8 =
1 · 2
ΔI − ΔI2 2 ΔI + ΔI2 2
2 ·
1 S1
(16)
2 1 1 · + S1 S2
ΔI + ΔI3 − S2 · Δt 2
2 ·
1 . S2
(17)
(18)
Similar to the calculation for the Second Cycle, by combining (14)–(18), it is concluded that ΔI2 is larger than ΔI3 when ΔVc1 Mc Ton + Δt − ESR+ · Co . · Co > K · S2 2 2 · K · ΔI2 (19) Also, according to (2) and the demand of ΔI1 > ΔI2 > ΔI3 ΔVc1 (ΔI1 + ΔI2 ) · Mc Mc · Co = · Co > . 2 · K · ΔI2 2 · K · ΔI2 · S2 K · S2
(20)
Combining (19) and (20), ΔI1 > ΔI2 > ΔI3 is satisfied when
2Mc ESR + K · S2
· Co >
Ton + Δt. 2
(21)
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Summary: Based on (13) and (21), the demand for the slope of the compensation ramp is obtained to satisfy ΔI0 > ΔI1 > ΔI2 > ΔI3 K · S2 Ton + Δt − ESR · Co . Mc > · (22) 2 · Co 2 Alternatively, this implies that subharmonic can be avoided when the slope of the compensation ramp (Mc ) is higher than ((K · S2 )/(2 · Co )) · ((Ton /2) + Δt − ESR · Co ). By using (22), the minimum amount of compensation ramp to avoid subharmonic is calculated based on power stage and control circuit parameters, which are usually determined first for buck converter design. Then, the estimated result is utilized to choose proper compensation ramp. Generally, the actual slope of the compensation ramp is recommended to be two to four times of the estimated minimum value in order to keep some design margin. On the other hand, an increased compensation ramp is beneficial for stability at the penalty of slower load transient response. The upper limit of the compensation ramp is usually determined by the load transient requirement of the specific application and can be measured based on experimental or simulation results. The condition of “overcompensation” occurs when excessive ramp compensation prevents the converter from achieving the required load transient response. It should be noted that parameter redesign is needed if the desired load transient response is still not achievable with the estimated minimum compensation ramp. Increasing output capacitance and decreasing output inductance are effective solutions to improve the load transient response. III. E XPERIMENTAL R ESULTS To verify the proposed subharmonic analysis for constant on-time control with ramp compensation, a prototype of buck converter is built by using discrete components for the control circuit. The detailed specification is shown as follows: 1) input voltage: 12 V; 2) output voltage: 1.2 V; 3) load current: 3 A; 4) switching frequency: 200 kHz. Fig. 3 shows the detailed circuit diagram used for experimental verification. The value of K is equal to R1 /R2 , which is set to six. The inductor has 1-μH inductance with a direct current resistance of 5.6 mΩ. The total output capacitance value is 88 μF. ESR is adjusted by connecting various highprecision resistors (milliohm-level resistance) in series with the capacitors. The comparator utilizes MAX942 with 80-ns propagation delay. ISL6612 is utilized as the driver. The total circuit propagation delay (Δt) is shown as 118 ns in Fig. 4. The experimental results are summarized in Table I, and the detailed waveforms are shown in Figs. 5 and 6. Notice that all the results match the conclusion in (22). Fig. 5 shows the waveforms when the ESR is 1 mΩ. The value of ESR · Co is approximately 88 ns, and Ton is approximately 500 ns. S2 = vo /L is equal to 1.2 A/μs. According to (22), Mc is required to be higher than 11.5 mV/μs in order to
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Fig. 3. Circuit diagram of the prototype for experimental verification (buck converter using constant on-time control with ramp compensation).
Fig. 4. Waveforms to show the total circuit propagation delay. The measured circuit propagation delay is 118 ns (MAX942 was used as a comparator for off time regulation). CH1: Input pulse for the control circuit (1 V/div). CH2: Output pulse for the control circuit (5 V/div). TABLE I S TABILITY OF C ONSTANT O N -T IME C ONTROL W ITH E XTERNAL C OMPENSATION R AMP AT VARIOUS C ONDITIONS
Fig. 5. Waveforms to explain the subharmonic mechanism for constant ontime control with ramp compensation (ESR = 1 mΩ): (a) Mc = 6.4 mV/μs, (b) Mc = 9.2 mV/μs, and (c) Mc = 15 mV/μs. CH1: V out ripple (200 mV/div). CH2: switch node voltage (SW) (5 V/div). CH3: Inductor current (5 A/div). CH4: Output of the compensation ramp generator (200 mV/div). (2 μs/div.) Mc is the change rate of the external compensation ramp, which is connected to the inverting input of the comparator in Fig. 3. Mc can be derived by multiplying R4 /(R3 + R4 ) with the change rate of the compensation ramp generator output. R4 /(R3 + R4 ) is set to 0.2.
avoid subharmonic. The conclusion is demonstrated in various conditions by the following examples. Fig. 5(a) is measured when Mc is equal to 6.4 mV/μs, which is lower than the required 11.5 mV/μs. The perturbation is unable to decrease with time, and subharmonic occurs.
Fig. 5(b) shows the waveform when Mc is equal to 9.2 mV/μs, which is also lower than 11.5 mV/μs. Subharmonic still occurs in this case.
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Fig. 6 shows the waveforms when the ESR is 3 mΩ. The value of ESR · Co is approximately 264 ns, and Ton is approximately 500 ns. S2 = vo /L is equal to 1.2 A/μs. Based on (22), the value of Mc is required to be higher than 4.25 mV/μs in order to avoid subharmonic. Fig. 6(a) is measured when Mc is equal to 3 mV/μs, which is lower than the required 4.25 mV/μs. Thus, subharmonic occurs. Fig. 6(b) is measured when Mc is 4 mV/μs, which is also lower than 4.25 mV/μs. Therefore, subharmonic still occurs. Fig. 6(c) shows the waveform without subharmonic. In this case, Mc is equal to 6 mV/μs, which is higher than 4.25 mV/μs.
IV. C ONCLUSION This paper has provided detailed analysis to explore the subharmonic mechanism for buck converters with constant ontime control and ramp compensation. For constant on-time control, ramp compensation can be fulfilled by utilizing a ramp with a fixed slope during the off time and a fixed level during the on time. Based on the inductor current information and the charge variations of the output capacitor, the effect of the compensation ramp is quantified. Also, the effect of circuit propagation delay is considered. Experimental results demonstrate the subharmonic mechanism for constant on-time control with ramp compensation. R EFERENCES
Fig. 6. Waveforms to explain the subharmonic mechanism for constant on-time control with ramp compensation (ESR = 3 mΩ): (a) Mc = 3 mV/μs, (b) Mc = 4 mV/μs, and (c) Mc = 6 mV/μs. CH1: V out ripple (200 mV/div). CH2: SW (5 V/div). CH3: Inductor current (5 A/div). CH4: Output of the compensation ramp generator (100 mV/div). (2 μs/div.) Mc is the change rate of the external compensation ramp, which is connected to the inverting input of the comparator in Fig. 3. Mc can be derived by multiplying R4 /(R3 + R4 ) with the change rate of the compensation ramp generator output. R4 /(R3 + R4 ) is set to 0.2.
Fig. 5(c) shows the waveform when Mc is equal to 15 mV/μs, which is higher than 11.5 mV/μs. Therefore, no subharmonic occurs.
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[14] S. Qu, “Modeling and design considerations of V2 controlled buck regulator,” in Proc. IEEE APEC, 2001, pp. 507–513. [15] J. Sun, “Characterization and performance comparison of ripple-based control for voltage regulator modules,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 346–353, Mar. 2006. [16] J. Sun, “Small-signal modeling of variable-frequency pulsewidth modulators,” IEEE Trans. Aerosp. Electron. Syst., vol. 38, no. 3, pp. 1104–1108, Jul. 2002. [17] J. Li and F. C. Lee, “Modeling of V2 current-mode control,” in Proc. IEEE APEC, 2009, pp. 298–304. [18] J. Li and F. C. Lee, “New modeling approach and equivalent circuit representation for current-mode control,” IEEE Trans. Power Electron., vol. 25, no. 5, pp. 1218–1230, May 2010. [19] J. Wang, J. Xu, and B. Bao, “Analysis of pulse bursting phenomenon in constant on-time controlled buck converter,” IEEE Trans. Ind. Electron., vol. 58, no. 12, pp. 5406–5410, Dec. 2011. [20] L. K. Wong and T. K. Man, “Maximum frequency for hysteretic control COT buck converters,” in Proc. Power Electron. Motion Control Conf., 2008, pp. 475–478. [21] R. Redl and J. Sun, “Ripple-based control of switching regulators—An overview,” IEEE Trans. Power Electron., vol. 24, no. 12, pp. 2669–2680, Dec. 2009. [22] X. Duan and A. Q. Huang, “Current-mode variable-frequency control architecture for high-current low-voltage dc–dc converters,” IEEE Trans. Power Electron., vol. 21, no. 4, pp. 1133–1137, Jul. 2006. [23] Y.-F. Liu and X. Liu, “Recent developments in digital control strategies for dc/dc switching power converters,” in Proc. Power Electron. Motion Control Conf., 2009, pp. 307–314.
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Ting Qian received the B.S. and M.S. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 1999 and 2002, respectively, and the Ph.D. degree in electrical engineering from Northeastern University, Boston, MA, in 2007. He is currently with Texas Instruments, Warwick, RI. His research interests include power converter topologies, on-chip integration and control schemes of power converters, active power filters, and digital control on power electronics.
