Supporting Information for Simple interface engineering of graphene ...
Supporting Information for
Simple interface engineering of graphene transistors with hydrophobizing stamps
Soo Sang Chaea,§, Won Jin Choia,§, Cheol-Soo Yanga, Tae Il Leeb,* and Jeong-O Leea,* a
Advanced Materials Division, Korea Research Institute of Chemical Technology (KRICT), Daejeon 34114, South Korea
b
Department of BioNano Technology, Gachon University, Seongnam, Gyeonggi-Do 13120, South Korea
§
Both authors contributed equally to this work
Corresponding Author; [email protected], [email protected]
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Methods 1. Preparation of graphene films Graphene was grown, using the low-pressure chemical vapor deposition (LPCVD) method, on a Cu foil (Alfa Aesar, Item No. 46986, 99.8%) in a hot wall furnace consisting of a four-inch fused silica tube. Prior to CVD graphene synthesis, the foils were cleaned with a Ni etchant (Transene, TFB) for 10 min and then rinsed three times with DI water. The cleaned Cu foil was loaded into the chamber, heated to 1000°C in a vacuum, and then annealed for 20 min under a 100 sccm H2 flow (at a pressure of approximately 70–80 mTorr). To initiate the growth of graphene, 30 sccm CH4 and 30 sccm H2 were introduced in the chamber, and growth was allowed to continue for 40 min (60 mTorr). Then, the sample was cooled down in a vacuum. A poly (methyl methacrylate (PMMA) solution (950 K, 4% by volume dissolved in chlorobenzene) was spin-coated onto the top side of the sample at 2000 rpm for 30 s. The PMMA film (thickness of 200 nm) was then dried overnight at room temperature. The Cu under the graphene film was etched with an ice-cold copper etchant solution and washed with DI water three times. The floating PMMA/graphene sheet was then transferred to engineered (reference) substrates. Finally, the PMMA film was dissolved using acetone and rinsed three times with isopropyl alcohol (IPA). 2. Engineered graphene transistor fabrication and logic gates The CVD-grown graphene described in subsection 1 was transferred onto the engineered substrates described in subsection 2, and patterned using photolithography and oxygen plasma etching. Note that the oligomeric hydrophobizers were protected by graphene and photoresists from plasma-induced damage. Another application of photolithography and then metallization with Cr (5 nm)/Au (30 nm) were carried out to complete the fabrication of the graphene device. In the case of the logic gate device, only part of the substrate was engineered using the hydrophobizer, i.e., one part of the graphene transistor was located on the engineered substrate, while the other part was located on the untreated silicon substrates.
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Figure S1. Long term stability of PDMS-based hydrophobizer as evaluated by water contact angle, under the different condition: in air (black square) and in water (red dot). The water contact angles remained high even after 14 days under both conditions.
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(a)
(b)
(c)
(d)
Figure S2. AFM images showing the surface coverage of low molecular weight PDMS with different contact times. (a) 1 s, (b) 1 min, (c) 3 min, (d) 30 min.
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Figure S3. The deposition rate of the LMW PDMS layer depends on the mixing ratio of PDMS stamp : with 10:1 ratio (black square); and with 20:1 (red circle).
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Figure S4. XPS analysis that shows the evolution of C-H signals with hydrophobizer treatment. (a) Pristine oxidized silicon substrate without any treatment. (b) Hydrophobizer treated surface for 1 s, (c) 1 min, (d) 3 min, (e) 30 min. S-6
Figure S5. XPS analysis that shows the evolution of Si-C signals with hydrophobizer treatment. (a) Pristine oxidized silicon substrate without any treatment. (b) Hydrophobizer treated surface for 1 s, (c) 1 min, (d) 3 min, (e) 30 min. S-7
Figure S6. Contact resistance of graphene on surface engineered substrate measured by four-probe method.
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Figure S7. Mapping of Raman spectrum for the graphene on engineered substrate. a) Optical microscopy image of sample, for which the same graphene is placed on bare SiO2 (left-half) and on PDMS engineered SiO2 (right-half). (b-d) Deviation maps of the peaks for (b) ‘G’ position, (c) ‘G’ intensity and (d) ‘2D’ intensity of Raman band of graphene obtained from each region. S-9
Figure S8. A model that shows the change of surface composition with hydrophobizer treatment and measured (calculated) contact angle from them.
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Figure S9. . Demonstration of “rollable” process. The thickness of LMW PDMS layer with increasing number of repeated contact-printing with (a) 1min and (b) 1sec, respectively. (c) The deposition thickness as a function of contactprinting time with continuous contacting. (d) Schematic diagram of “rollable” hydrophobizer engineering technique.
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Simple interface engineering of graphene transistors with hydrophobizing stamps
Soo Sang Chaea,§, Won Jin Choia,§, Cheol-Soo Yanga, Tae Il Leeb,* and Jeong-O Leea,* a
Advanced Materials Division, Korea Research Institute of Chemical Technology (KRICT), Daejeon 34114, South Korea
b
Department of BioNano Technology, Gachon University, Seongnam, Gyeonggi-Do 13120, South Korea
§
Both authors contributed equally to this work
Corresponding Author; [email protected], [email protected]
S-1
Methods 1. Preparation of graphene films Graphene was grown, using the low-pressure chemical vapor deposition (LPCVD) method, on a Cu foil (Alfa Aesar, Item No. 46986, 99.8%) in a hot wall furnace consisting of a four-inch fused silica tube. Prior to CVD graphene synthesis, the foils were cleaned with a Ni etchant (Transene, TFB) for 10 min and then rinsed three times with DI water. The cleaned Cu foil was loaded into the chamber, heated to 1000°C in a vacuum, and then annealed for 20 min under a 100 sccm H2 flow (at a pressure of approximately 70–80 mTorr). To initiate the growth of graphene, 30 sccm CH4 and 30 sccm H2 were introduced in the chamber, and growth was allowed to continue for 40 min (60 mTorr). Then, the sample was cooled down in a vacuum. A poly (methyl methacrylate (PMMA) solution (950 K, 4% by volume dissolved in chlorobenzene) was spin-coated onto the top side of the sample at 2000 rpm for 30 s. The PMMA film (thickness of 200 nm) was then dried overnight at room temperature. The Cu under the graphene film was etched with an ice-cold copper etchant solution and washed with DI water three times. The floating PMMA/graphene sheet was then transferred to engineered (reference) substrates. Finally, the PMMA film was dissolved using acetone and rinsed three times with isopropyl alcohol (IPA). 2. Engineered graphene transistor fabrication and logic gates The CVD-grown graphene described in subsection 1 was transferred onto the engineered substrates described in subsection 2, and patterned using photolithography and oxygen plasma etching. Note that the oligomeric hydrophobizers were protected by graphene and photoresists from plasma-induced damage. Another application of photolithography and then metallization with Cr (5 nm)/Au (30 nm) were carried out to complete the fabrication of the graphene device. In the case of the logic gate device, only part of the substrate was engineered using the hydrophobizer, i.e., one part of the graphene transistor was located on the engineered substrate, while the other part was located on the untreated silicon substrates.
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Figure S1. Long term stability of PDMS-based hydrophobizer as evaluated by water contact angle, under the different condition: in air (black square) and in water (red dot). The water contact angles remained high even after 14 days under both conditions.
S-3
(a)
(b)
(c)
(d)
Figure S2. AFM images showing the surface coverage of low molecular weight PDMS with different contact times. (a) 1 s, (b) 1 min, (c) 3 min, (d) 30 min.
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Figure S3. The deposition rate of the LMW PDMS layer depends on the mixing ratio of PDMS stamp : with 10:1 ratio (black square); and with 20:1 (red circle).
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Figure S4. XPS analysis that shows the evolution of C-H signals with hydrophobizer treatment. (a) Pristine oxidized silicon substrate without any treatment. (b) Hydrophobizer treated surface for 1 s, (c) 1 min, (d) 3 min, (e) 30 min. S-6
Figure S5. XPS analysis that shows the evolution of Si-C signals with hydrophobizer treatment. (a) Pristine oxidized silicon substrate without any treatment. (b) Hydrophobizer treated surface for 1 s, (c) 1 min, (d) 3 min, (e) 30 min. S-7
Figure S6. Contact resistance of graphene on surface engineered substrate measured by four-probe method.
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Figure S7. Mapping of Raman spectrum for the graphene on engineered substrate. a) Optical microscopy image of sample, for which the same graphene is placed on bare SiO2 (left-half) and on PDMS engineered SiO2 (right-half). (b-d) Deviation maps of the peaks for (b) ‘G’ position, (c) ‘G’ intensity and (d) ‘2D’ intensity of Raman band of graphene obtained from each region. S-9
Figure S8. A model that shows the change of surface composition with hydrophobizer treatment and measured (calculated) contact angle from them.
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Figure S9. . Demonstration of “rollable” process. The thickness of LMW PDMS layer with increasing number of repeated contact-printing with (a) 1min and (b) 1sec, respectively. (c) The deposition thickness as a function of contactprinting time with continuous contacting. (d) Schematic diagram of “rollable” hydrophobizer engineering technique.
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