Switched-Capacitor Converter Configuration with ... - Semantic Scholar
Switched-Capacitor Converter Configuration with Low EMI Emission Obtained by Interleaving and Its Large-Signal Modeling Siew-Chong Tan∗, Member, IEEE, Moshe Nur† , Sitthisak Kiratipongvoot∗ , Svetlana Bronstein‡, Y. M. Lai∗ , Member, IEEE, C. K. Tse∗ , Fellow, IEEE, and Adrian Ioinovici† , Fellow, IEEE ∗ Department
of Electronic and Information Engineering Hong Kong Polytechnic University, Hong Kong E-mail: [email protected], [email protected], [email protected], [email protected] † Department of Electrical and Electronic Engineering, Holon Institute of Technology, Holon, Israel E-mail: [email protected], [email protected] ‡ Department of Electrical Engineering, Sami Shamoon College of Engineering, Beer-Sheva, Israel E-mail: [email protected]
Abstract— The switched-capacitor converters are ideal switching-mode power supplies for portable electronic consumers due to their light weight, small size, and high power density. However, they suffer from a discontinuous input current waveform with large di/dt, what leads to significant electromagnetic interference (EMI) emission. This paper proposes a configuration of switched-capacitor converters connected in parallel with their inputs and outputs interleaved. The interleaving times are calculated by taking into account the fast capacitor-charging characteristic, and the need to have the nominal operating point on its linear part for increasing the regulation range at changes in the input voltage and load. To improve control performance and avoid the use of small-signal linearization in the control design, a large-signal approach is adopted for modeling the converter, allowing for a design of a sliding mode control.
I. I NTRODUCTION With only switches and capacitors in the power stage, the switched-capacitor (SC) converters have the advantage of light weight, small size, and high power density [1]. Such features make them ideal power supplies for mobile electronic systems like cellular phones, personal digital assistants, and so forth. The electronic industry is seeing increasing usage of such converters in their products. Semiconductor companies like Maxim and National Semiconductor are already mass producing SC converters in IC packaged form, e.g. MAX828/829 and LM3351 etc., for commercial applications. The switching operation of the SC converters consists of capacitor charging and discharging stages. The input current is pulsating and discontinuous. Its peak magnitude in a circuit with n capacitors per stage is determined by the difference between vin /n and the minimum voltage on the capacitors, divided by the resistance in the charging path, r (given by the sum of the DC resistances of the capacitors and switches) [2]. As the parasitic resistances have a very low value, this peak is
978-1-4244-3828-0/09/$25.00 ©2009 IEEE
1081
very high. The charging characteristic of the capacitor (typically of a very small value) is very steep. The consequence of such a form of the input current is a large emission of EMI. By operating the main transistor as an amplifier, one can get a continuous input current [3]. However, such a method implies an input current-based control type, which presents a small regulation range. The usual SC converters are built for relatively low power. If more power is needed, a simple solution is to connect several SC modules in parallel. This paper proposes to use an interleaving operation of these modules, applied at both the input and output terminals. As a consequence, the input current and the load voltage present less ripple. Interleaving the discharging SC sub-cells for reducing the output voltage ripple is a straightforward design, which was already accomplished [4]. Interleaving the charging SC sub-cells for getting a continuous input current is far away from a straightforward technique. A special procedure will be described in the paper. In Section II, a discussion on SC converters is presented with a simple design example. In Section III, an interleaving operation will be designed by using four SC modules, the challenging point being how to deal with the fast charging characteristic of the capacitors: each module has to enter the charging phase before the preceding one finishes, otherwise the input current would become discontinuous. In order to keep a large regulation range, the nominal operating points of all the modules have to remain on the quasi-linear part of the capacitor charging characteristic. For assuring a good response even for large changes in the input voltage and load, a largesignal model of the converter will be used in Section IV for designing a sliding-mode controller. The experimental results will be shown in Section V. II. BASIC SC CONVERTER A typical step-down SC converter with one capacitor per stage [1], [2], and the timing diagram of the switches are shown in Figs. 1(a) and 1(b), respectively. It presents four
switching states per cycle (Fig. 2). In State 1, of duration Ton = DTS , capacitor C1 is in the charging phase, being charged by the input voltage, and C2 is in the discharging phase whereby it discharges to the load. In State 2, the charging of C1 is interrupted for regulation’s sake, but the discharging of C2 continues. In the second half-cycle (States 3 and 4), the role of the two capacitors is interchanged. The waveforms of the input current and output voltage are given in Figs. 3(a) and 3(b).
(a)
Following the design procedure of [2], CfS ≥
vo 0.5 . vC(ripple) rL + r
C and fS are designed in an iterative way for ensuring that the output voltage ripple vC(ripple) meets the desired specification, and that the steady-state Ton = DTS gives an operating point, ideally, around the center point X of the linear part of the charging capacitor characteristic (preferably Ton ≤ 0.25rC). See Fig. 4 for an exemplification.
(b)
Fig. 1. (a) Switched-capacitor converter and (b) the timing diagram. (vC(ripple) = vC1(max) − vC1(min) ; C1 = C2 = C).
(a) State 1
Fig. 4. Charging characteristic of a capacitor C = 47 µF, from a line voltage of 12 V, r (total resistance of the charging path) = 545 mΩ.
For example, for vin = 12 V, vo = 9 V, rL = 8 Ω (around 10 W), r = 545 mΩ, and a ripple of less than 5% of the output voltage, i.e., vC(ripple) < 0.45 V, it results in fS = 250 kHz, C = 47 µF, Ton = 0.51 µs (on linear part of charging characteristic), and D = 0.1275. Since the solution is not unique, many design outcomes are possible. Another possible design is fS = 200 kHz, C = 47 µF, Ton = 0.625 µs, and D = 0.125.
(b) State 2
III. P ROPOSED I NTERLEAVING C ONFIGURATION M ODULES
(c) State 3
(d) State 4
Fig. 2. The four operating states of the switched-capacitor converter (r = rS + rC represents the total parasitic resistance of the switch and capacitor). iin1 =
vi − vC 1(min) v −v iin2 = i C 2 (min) r r
vC 2 − riout1 vC1 − riout2
vo
vC ( ripple )
t
(a) Input Current Fig. 3.
(2)
t
(b) Output Voltage
(a) Input current and (b) output voltage waveforms.
According to Fig. 1(b), for getting the desired vo , Ton is calculated as " # vC(ripple) . Ton = −rC ln 1 − (1) v vi − vo + riout − C(ripple) 2
1082
FOR
n SC
When interleaving the charging SC cells, one has to redesign the converters, i.e., to recalculate fS and C (all the SC modules are identical) due to more constraints: (a) In order to ensure a continuous input current (iin = Σiin(k ) , iin(k ) being the input current of each converter), each charging-capacitor subcircuit has to enter in operation before the preceding charging-capacitor subcircuit finished its operation (which took a duration given by Ton ). This implies that the interleaving delay TD must be equal or smaller than Ton . (b) The total power of the paralleling configuration is given by the customer request, thus imposing a certain n. Therefore, in calculations, the new load will be rL /n. (c) In order to get a very small ripple in the input current, taking (a) into account too, the number of SC modules /2 in the interleaving configuration, n, has to be TTSon , or a TS /2 multiple of Ton . (d) The designed Ton has to ensure, by a suitable design of the C value, as in the case of a single module, that the operating point of each charging circuit is centered around the middle point of the linear part of the charging capacitor characteristic.
/2 (e) By choosing n as a multiple of TTSon , there are always n SC cells in the discharging phase (as shown in Fig. 1(b), the duration of the discharging phase is TS /2 for each converter); eqn. (2) becomes
nCfS ≥
vo
0.5 . vC(ripple) rL /n
(3)
(f) In order to ensure an almost ripple-free output voltage, without using large output capacitors (Co in Fig. 1(a)), the discharging characteristics have to be close to linear waveforms, ideally, in the middle of the linear part of the discharging characteristic, i.e, requring TS /2 ≤ 0.25rL C ⇒ TS ≤ 0.5rL C. (g) The given design of C has to result in a capacitor value that can be found in the market, as the availability range of multilayer ceramic capacitors, which are used in manufacturing SC converters, is quite restrained. Taking into account (1) and (3), and the conditions (a)– (g), for the required specifications: vin = 12 V, vo = 9 V, P = 40 W (i.e., rL = 2 Ω), an iterative procedure finally gives n = 4, fS = 200 kHz, C = 47 µF, Ton = 0.625 µs (i.e., D = 0.125), and TD = 0.625 µs. (a) Switching diagram 0+
1.25 0.625
2.5 1.875
3.75 3.125
5 4.375
6.25 5.625
7.5 6.875
8.75 8.125
10 9.375
C11 CHG
C11 CHG
C11 CHG
C12 DISCHG
C12 DISCHG
C12 DISCHG
C12 CHG
C12 CHG
C11 DISCHG
C11 DISCHG
C21 CHG
C22 DISCHG
C22 DISCHG C22 CHG
C21 DISCHG
Time (µs)
C21 CHG
C21 CHG
C22 DISCHG
11.25 12.5 10.625 11.875
C22 CHG
C21 DISCHG
C21 DISCHG
C31 CHG
C31 CHG
C31 CHG
C32 DISCHG
C32 DISCHG
C32 DISCHG
C31 DISCHG
C32 CHG
C32 CHG
C31 DISCHG
C31 DISCHG
C41 CHG
C41 CHG
C42 DISCHG
C41 DISCHG
C41 CHG
C42 DISCHG
C42 DISCHG
C42 CHG
C42 CHG
C41 DISCHG
C41 DISCHG
(b) Charging/discharging diagram Fig. 6. (a) Timing diagrams of switching signals and (b) the charging/discharging diagram of the proposed interleaved four SC converters.
Fig. 5.
input currents flowing from the source to C1 and C2 are ( dv iin1 = C1 C1(C) dt (4) dv iin2 = C2 C2(C) dt
Four-interleaved SC converters configuration.
The paralleling four converters configuration is given in Fig. 5, its switching diagram in Fig. 6(a), and the capacitors charging/discharging diagram in Fig. 6(b). IV. L ARGE -S IGNAL M ODELING
FOR
SM C ONTROL
Each SC module can be modeled by a system of differential equations, where the output current can be related to the charging operation. As explained in [5], the instantaneous
1083
dv
dv
where C1(C) and C2(C) are the rates of change of voltage dt dt of C1 and C2 , respectively, during charging. By using the principle of energy balance [5], the output currents flowing out from C1 and C2 can be related to the charging switches S1 and S4 with the following expressions: ( C1 ) iout1 = 2(viR−v uS1 in . (5) C2 ) iout2 = 2(viR−v uS4 in
where m = 1, 2, 3, ..., n is the converter module’s number.
Input current (2.5 A/DIV) Current Level (500 mA/Div)
Input current (2.5 A/DIV) Current Level (500 mA/Div)
No small-signal approximations have been required in obtaining this description of the switching operation of the SC converter. Based on it, an SM controller can be designed following the theory from [6]. The derived control law is ( vC(Sm4) = K [irm + γ(Vref − vo )] , (6) vˆramp(Sm4) = K [η(vi − vCm2 )]
(a) Single SC converter
V. E XPERIMENTAL R ESULTS
(b) Four-SC converter
(a) Single SC converter
Output current (2 A/DIV) Voltage ripple (100 mV/Div)
Voltage Ripple (100 mV /DIV)
Voltage Ripple (100 mV /DIV)
Input current (2.5 A/DIV)
Input current (2.5 A/DIV)
Fig. 9. Input current and the corresponding Fourier series components of (a) a single SC converter (without Co ) and (b) the four-SC converters (without Co ) in an interleaving configuration.
(b) Four-SC converter
Fig. 7. Input current and output voltage ripple waveforms of (a) a single SC converter (without Co ) and (b) the four-SC converters (without Co ) in an interleaving configuration.
The experimental results for the input current and output voltage ripple during a steady state are given in a comparative way in Fig. 7(a) for a single converter, and Fig. 7(b) for the designed four-interleaved-converters configuration. The same specifications are used in both cases (vin = 12 V and vo = 9 V). The prototypes are based on the design performed in Sections II and III. A comparison of the obtained results shows a significant reduction in the input current ripple and the output voltage ripple (from ±150 mV to ±50 mV) with the proposed configuration. The experimental input and output currents of each phase of the four-SC converters are shown in Figs. 8(a) and 8(b), respectively.
Fig. 10. Output current and output voltage ripple of the four-SC converters (without Co ) using an SM controller operating with step load changes alternating between 3.5 A and 5.5 A.
change alternating between 3.5 A and 5.5 A, the settling time of the controlled voltage is short, at around 100 µs. VI. C ONCLUSIONS A continuous (non-pulsating) input current with very small ripple was obtained, reducing substantially the typical EMI emission of the SC converters. As the output voltage contains very small ripple, the large output capacitors, typically used in SC converters, are no longer required, thus increasing the power density. An SC converter configuration of larger power is obtained, enlarging the range of its applications.
Four Phases of Input Current (6.66 A/DIV)
Four Phases of Output Current (2 A/DIV)
R EFERENCES
(a) Phasor input currents
(b) Phasor output currents
Fig. 8. Waveforms of (a) input currents and (b) output currents of each phase of the four-SC converters (without Co ) in an interleaving configuration.
Figs. 9(a) and 9(b) show the Fourier series components of the input currents. With the input current being continuous under the four-SC converters, the harmonic components (and therefore the EMI emissions) are significantly reduced. Fig. 10 shows the experimental transient response for the four-SC converters with the SM controller. For a step-load
1084
[1] A. Ioinovici, “Switched-capacitor power electronics circuits,” IEEE Circuits and Systems Magazine, vol. 1, no. 3, pp. 37–42, Sep. 2001. [2] G. Zhu and A. Ioinovici, “Switched-capacitor power supplies: DC voltage ratio, efficiency, ripple, regulation,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 553–556, May 1996. [3] H. S. H. Chung, “Design and analysis of a switched-capacitor-based step-up DC/DC converter with continuous input current,” IEEE Transactions on Circuits and Systems I, vol. 46, no. 6, pp. 722–731, Jun. 1999. [4] J. Han, A. V. Jouanne, and G. C. Temes, “A new approach to reducing output ripple in switched-capacitor-based step-down DC-DC converters,” IEEE Transactions on Power Electronics, vol. 21, no. 6, pp. 1548–1555, Nov. 2006. [5] S. C. Tan, S. Bronstein, M. Nur, Y. M. Lai, A. Ioinovici, and C. K. Tse, “Nonlinear control of switched-capacitor converters using sliding mode control approach,” IEEE Power Electronics Specialists Conference Record (PESC 2008), pp. 372–377, Jun. 2008. [6] S. C. Tan, Y. M. Lai, and C. K. Tse, “A unified approach to the design of PWM based sliding mode voltage controller for DC–DC converters in continuous conduction mode,” IEEE Transactions on Circuits and Systems I, vol. 53, no. 8, pp. 1816–1827, Aug. 2006.
of Electronic and Information Engineering Hong Kong Polytechnic University, Hong Kong E-mail: [email protected], [email protected], [email protected], [email protected] † Department of Electrical and Electronic Engineering, Holon Institute of Technology, Holon, Israel E-mail: [email protected], [email protected] ‡ Department of Electrical Engineering, Sami Shamoon College of Engineering, Beer-Sheva, Israel E-mail: [email protected]
Abstract— The switched-capacitor converters are ideal switching-mode power supplies for portable electronic consumers due to their light weight, small size, and high power density. However, they suffer from a discontinuous input current waveform with large di/dt, what leads to significant electromagnetic interference (EMI) emission. This paper proposes a configuration of switched-capacitor converters connected in parallel with their inputs and outputs interleaved. The interleaving times are calculated by taking into account the fast capacitor-charging characteristic, and the need to have the nominal operating point on its linear part for increasing the regulation range at changes in the input voltage and load. To improve control performance and avoid the use of small-signal linearization in the control design, a large-signal approach is adopted for modeling the converter, allowing for a design of a sliding mode control.
I. I NTRODUCTION With only switches and capacitors in the power stage, the switched-capacitor (SC) converters have the advantage of light weight, small size, and high power density [1]. Such features make them ideal power supplies for mobile electronic systems like cellular phones, personal digital assistants, and so forth. The electronic industry is seeing increasing usage of such converters in their products. Semiconductor companies like Maxim and National Semiconductor are already mass producing SC converters in IC packaged form, e.g. MAX828/829 and LM3351 etc., for commercial applications. The switching operation of the SC converters consists of capacitor charging and discharging stages. The input current is pulsating and discontinuous. Its peak magnitude in a circuit with n capacitors per stage is determined by the difference between vin /n and the minimum voltage on the capacitors, divided by the resistance in the charging path, r (given by the sum of the DC resistances of the capacitors and switches) [2]. As the parasitic resistances have a very low value, this peak is
978-1-4244-3828-0/09/$25.00 ©2009 IEEE
1081
very high. The charging characteristic of the capacitor (typically of a very small value) is very steep. The consequence of such a form of the input current is a large emission of EMI. By operating the main transistor as an amplifier, one can get a continuous input current [3]. However, such a method implies an input current-based control type, which presents a small regulation range. The usual SC converters are built for relatively low power. If more power is needed, a simple solution is to connect several SC modules in parallel. This paper proposes to use an interleaving operation of these modules, applied at both the input and output terminals. As a consequence, the input current and the load voltage present less ripple. Interleaving the discharging SC sub-cells for reducing the output voltage ripple is a straightforward design, which was already accomplished [4]. Interleaving the charging SC sub-cells for getting a continuous input current is far away from a straightforward technique. A special procedure will be described in the paper. In Section II, a discussion on SC converters is presented with a simple design example. In Section III, an interleaving operation will be designed by using four SC modules, the challenging point being how to deal with the fast charging characteristic of the capacitors: each module has to enter the charging phase before the preceding one finishes, otherwise the input current would become discontinuous. In order to keep a large regulation range, the nominal operating points of all the modules have to remain on the quasi-linear part of the capacitor charging characteristic. For assuring a good response even for large changes in the input voltage and load, a largesignal model of the converter will be used in Section IV for designing a sliding-mode controller. The experimental results will be shown in Section V. II. BASIC SC CONVERTER A typical step-down SC converter with one capacitor per stage [1], [2], and the timing diagram of the switches are shown in Figs. 1(a) and 1(b), respectively. It presents four
switching states per cycle (Fig. 2). In State 1, of duration Ton = DTS , capacitor C1 is in the charging phase, being charged by the input voltage, and C2 is in the discharging phase whereby it discharges to the load. In State 2, the charging of C1 is interrupted for regulation’s sake, but the discharging of C2 continues. In the second half-cycle (States 3 and 4), the role of the two capacitors is interchanged. The waveforms of the input current and output voltage are given in Figs. 3(a) and 3(b).
(a)
Following the design procedure of [2], CfS ≥
vo 0.5 . vC(ripple) rL + r
C and fS are designed in an iterative way for ensuring that the output voltage ripple vC(ripple) meets the desired specification, and that the steady-state Ton = DTS gives an operating point, ideally, around the center point X of the linear part of the charging capacitor characteristic (preferably Ton ≤ 0.25rC). See Fig. 4 for an exemplification.
(b)
Fig. 1. (a) Switched-capacitor converter and (b) the timing diagram. (vC(ripple) = vC1(max) − vC1(min) ; C1 = C2 = C).
(a) State 1
Fig. 4. Charging characteristic of a capacitor C = 47 µF, from a line voltage of 12 V, r (total resistance of the charging path) = 545 mΩ.
For example, for vin = 12 V, vo = 9 V, rL = 8 Ω (around 10 W), r = 545 mΩ, and a ripple of less than 5% of the output voltage, i.e., vC(ripple) < 0.45 V, it results in fS = 250 kHz, C = 47 µF, Ton = 0.51 µs (on linear part of charging characteristic), and D = 0.1275. Since the solution is not unique, many design outcomes are possible. Another possible design is fS = 200 kHz, C = 47 µF, Ton = 0.625 µs, and D = 0.125.
(b) State 2
III. P ROPOSED I NTERLEAVING C ONFIGURATION M ODULES
(c) State 3
(d) State 4
Fig. 2. The four operating states of the switched-capacitor converter (r = rS + rC represents the total parasitic resistance of the switch and capacitor). iin1 =
vi − vC 1(min) v −v iin2 = i C 2 (min) r r
vC 2 − riout1 vC1 − riout2
vo
vC ( ripple )
t
(a) Input Current Fig. 3.
(2)
t
(b) Output Voltage
(a) Input current and (b) output voltage waveforms.
According to Fig. 1(b), for getting the desired vo , Ton is calculated as " # vC(ripple) . Ton = −rC ln 1 − (1) v vi − vo + riout − C(ripple) 2
1082
FOR
n SC
When interleaving the charging SC cells, one has to redesign the converters, i.e., to recalculate fS and C (all the SC modules are identical) due to more constraints: (a) In order to ensure a continuous input current (iin = Σiin(k ) , iin(k ) being the input current of each converter), each charging-capacitor subcircuit has to enter in operation before the preceding charging-capacitor subcircuit finished its operation (which took a duration given by Ton ). This implies that the interleaving delay TD must be equal or smaller than Ton . (b) The total power of the paralleling configuration is given by the customer request, thus imposing a certain n. Therefore, in calculations, the new load will be rL /n. (c) In order to get a very small ripple in the input current, taking (a) into account too, the number of SC modules /2 in the interleaving configuration, n, has to be TTSon , or a TS /2 multiple of Ton . (d) The designed Ton has to ensure, by a suitable design of the C value, as in the case of a single module, that the operating point of each charging circuit is centered around the middle point of the linear part of the charging capacitor characteristic.
/2 (e) By choosing n as a multiple of TTSon , there are always n SC cells in the discharging phase (as shown in Fig. 1(b), the duration of the discharging phase is TS /2 for each converter); eqn. (2) becomes
nCfS ≥
vo
0.5 . vC(ripple) rL /n
(3)
(f) In order to ensure an almost ripple-free output voltage, without using large output capacitors (Co in Fig. 1(a)), the discharging characteristics have to be close to linear waveforms, ideally, in the middle of the linear part of the discharging characteristic, i.e, requring TS /2 ≤ 0.25rL C ⇒ TS ≤ 0.5rL C. (g) The given design of C has to result in a capacitor value that can be found in the market, as the availability range of multilayer ceramic capacitors, which are used in manufacturing SC converters, is quite restrained. Taking into account (1) and (3), and the conditions (a)– (g), for the required specifications: vin = 12 V, vo = 9 V, P = 40 W (i.e., rL = 2 Ω), an iterative procedure finally gives n = 4, fS = 200 kHz, C = 47 µF, Ton = 0.625 µs (i.e., D = 0.125), and TD = 0.625 µs. (a) Switching diagram 0+
1.25 0.625
2.5 1.875
3.75 3.125
5 4.375
6.25 5.625
7.5 6.875
8.75 8.125
10 9.375
C11 CHG
C11 CHG
C11 CHG
C12 DISCHG
C12 DISCHG
C12 DISCHG
C12 CHG
C12 CHG
C11 DISCHG
C11 DISCHG
C21 CHG
C22 DISCHG
C22 DISCHG C22 CHG
C21 DISCHG
Time (µs)
C21 CHG
C21 CHG
C22 DISCHG
11.25 12.5 10.625 11.875
C22 CHG
C21 DISCHG
C21 DISCHG
C31 CHG
C31 CHG
C31 CHG
C32 DISCHG
C32 DISCHG
C32 DISCHG
C31 DISCHG
C32 CHG
C32 CHG
C31 DISCHG
C31 DISCHG
C41 CHG
C41 CHG
C42 DISCHG
C41 DISCHG
C41 CHG
C42 DISCHG
C42 DISCHG
C42 CHG
C42 CHG
C41 DISCHG
C41 DISCHG
(b) Charging/discharging diagram Fig. 6. (a) Timing diagrams of switching signals and (b) the charging/discharging diagram of the proposed interleaved four SC converters.
Fig. 5.
input currents flowing from the source to C1 and C2 are ( dv iin1 = C1 C1(C) dt (4) dv iin2 = C2 C2(C) dt
Four-interleaved SC converters configuration.
The paralleling four converters configuration is given in Fig. 5, its switching diagram in Fig. 6(a), and the capacitors charging/discharging diagram in Fig. 6(b). IV. L ARGE -S IGNAL M ODELING
FOR
SM C ONTROL
Each SC module can be modeled by a system of differential equations, where the output current can be related to the charging operation. As explained in [5], the instantaneous
1083
dv
dv
where C1(C) and C2(C) are the rates of change of voltage dt dt of C1 and C2 , respectively, during charging. By using the principle of energy balance [5], the output currents flowing out from C1 and C2 can be related to the charging switches S1 and S4 with the following expressions: ( C1 ) iout1 = 2(viR−v uS1 in . (5) C2 ) iout2 = 2(viR−v uS4 in
where m = 1, 2, 3, ..., n is the converter module’s number.
Input current (2.5 A/DIV) Current Level (500 mA/Div)
Input current (2.5 A/DIV) Current Level (500 mA/Div)
No small-signal approximations have been required in obtaining this description of the switching operation of the SC converter. Based on it, an SM controller can be designed following the theory from [6]. The derived control law is ( vC(Sm4) = K [irm + γ(Vref − vo )] , (6) vˆramp(Sm4) = K [η(vi − vCm2 )]
(a) Single SC converter
V. E XPERIMENTAL R ESULTS
(b) Four-SC converter
(a) Single SC converter
Output current (2 A/DIV) Voltage ripple (100 mV/Div)
Voltage Ripple (100 mV /DIV)
Voltage Ripple (100 mV /DIV)
Input current (2.5 A/DIV)
Input current (2.5 A/DIV)
Fig. 9. Input current and the corresponding Fourier series components of (a) a single SC converter (without Co ) and (b) the four-SC converters (without Co ) in an interleaving configuration.
(b) Four-SC converter
Fig. 7. Input current and output voltage ripple waveforms of (a) a single SC converter (without Co ) and (b) the four-SC converters (without Co ) in an interleaving configuration.
The experimental results for the input current and output voltage ripple during a steady state are given in a comparative way in Fig. 7(a) for a single converter, and Fig. 7(b) for the designed four-interleaved-converters configuration. The same specifications are used in both cases (vin = 12 V and vo = 9 V). The prototypes are based on the design performed in Sections II and III. A comparison of the obtained results shows a significant reduction in the input current ripple and the output voltage ripple (from ±150 mV to ±50 mV) with the proposed configuration. The experimental input and output currents of each phase of the four-SC converters are shown in Figs. 8(a) and 8(b), respectively.
Fig. 10. Output current and output voltage ripple of the four-SC converters (without Co ) using an SM controller operating with step load changes alternating between 3.5 A and 5.5 A.
change alternating between 3.5 A and 5.5 A, the settling time of the controlled voltage is short, at around 100 µs. VI. C ONCLUSIONS A continuous (non-pulsating) input current with very small ripple was obtained, reducing substantially the typical EMI emission of the SC converters. As the output voltage contains very small ripple, the large output capacitors, typically used in SC converters, are no longer required, thus increasing the power density. An SC converter configuration of larger power is obtained, enlarging the range of its applications.
Four Phases of Input Current (6.66 A/DIV)
Four Phases of Output Current (2 A/DIV)
R EFERENCES
(a) Phasor input currents
(b) Phasor output currents
Fig. 8. Waveforms of (a) input currents and (b) output currents of each phase of the four-SC converters (without Co ) in an interleaving configuration.
Figs. 9(a) and 9(b) show the Fourier series components of the input currents. With the input current being continuous under the four-SC converters, the harmonic components (and therefore the EMI emissions) are significantly reduced. Fig. 10 shows the experimental transient response for the four-SC converters with the SM controller. For a step-load
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