Syndrome-testable design of combinational circuit
IEEE TRANSACTIONS ON COMPUTERS, VOL.
442
C-29, NO. 6, JUNE 1980
Syndrome-Testable Design of Combinational Circuits JACOB SAVIR, Abstract-Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size. In this paper we describe a method of designing combinational circuits in such a way that their test procedure will require the knowledge of only one characteristic of the fault-free circuit, called the syndrome. This solves the storage problem associated with the test procedure. The syndrome-test procedure does not require test vector generation, and thus the expensive stage of test generation and fault simulation is eliminated. Index Terms-Combinational circuit, fan-out-free circuit, minterm, prime implicant, single fault, stuck-at fault.
I. INTRODUCTION
I N THIS paper we restrict ourselves to the class of permanent stuck-at faults, i.e., a faulty line appears logically as if it is either stuck at a constant 0, or at a constant 1. The classical approach [6] to the problem of testing combinational circuits was to design a test set which detects all faults from a prescribed set, and store both the test set and the expected output to the individual test vectors. Whenever a circuit was tested, the actual response and the expected output were compared to determine whether or not the circuit under test (CUT) was fault-free. For most practical circuits manufactured today, this approach requires test generation, possibly coupled with fault simulation, and high data volumes for implementation. The cost and time required to implement the classical approach grows quickly with the levels of integration. In this paper we show that by using a new method it is possible to reduce the storage requirement considerably at a very low cost, and avoid the expensive stage of test generation. Recently, a few other approaches to the testing problem have been presented in the literature. In [3] the method of transition counts is described. This method has the advantage of drastically reducing the storage requirement, but it is difficult to determine a proper test input sequence. In [5] a referenceless testing method is described. Its disadvantage lies in requiring very long test patterns to achieve a reasonable detection probability. In [8], a practical test procedure which employs testing for some functional attributes of combinational
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circuits is described. It is shown in [8] that by testing for specific functional properties it is possible to determine whether or not some classes of combinational circuits suffer any stuck-at faults. In this paper we show a method of designing combinational circuits so that the storage requirement for implementing the test procedure will be restricted to only one number, called the syndrome of the circuit, which is based on the number of minterms realized by the switching function. Since a fault-free and faulty circuit do not necessarily have different syndromes, special design of the combinational circuit is required in order to make it syndrome-testable. We say that a circuit is syndrome-testable if the syndrome of any faulty version of a circuit, induced by a single stuck-at fault, does not equal the syndrome of the fault-free circuit. Thus, the test procedure consists of applying all input combinations to the CUT and recording its syndrome (usually implemented by a counter). If the actual syndrome equals the expected syndrome, the circuit is fault-free; otherwise a fault is detected and the procedure stops. This approach has both the advantage of requiring only one reference and the advantage of avoiding the test generation process. In order to reduce the test length for circuits with large number of inputs (for instance more than 20), the combinational circuit is partitioned into subcircuits and designed so that each subcircuit is syndrome-testable. In this way, each subcircuit can be tested separately in no more than 1 s. The penalty paid for producing a syndrome-testable design is a slight increase in the number of pins. In Section II various syndrome properties of combinational circuits are described. Section III describes the proposed testable design. The paper concludes with a brief summary.
II. SYNDROME-PROPERTIES OF COMBINATIONAL CIRCUITS Definition 1: The syndrome of a Boolean function is defined as S = K/2n, where K is the number of minterms realized by the function and n the number of binary input lines. The syndrome is a functional property. Thus, various realizations of the same function will have the same syndrome. Clearly, 0 < S < 1, where the boundaries are attained by the constant functions. The syndrome of various n-input gates is shown in Fig. 1. It is useful to find the input-output syndrome relations beManuscript received August 27, 1979; revised February 7, 1980. This work was initiated while the author held a post-doctoral position at Stanford Unitween various interconnected sections of a logic circuit. These versity, Stanford, CA 94305. input-output relations are especially simple when the associThe author is with IBM Thomas J. Watson Research Center, Yorktown ated sections have unshared (disjoint) inputs. Heights, NY 10598. 0018-9340/80/0600-0442$00.75 © 1980 IEEE
443
SAVIR: DESIGN OF COMBINATIONAL CIRCUITS
SI
S=2 -n
S=1-2
I
S=2
>
Fig. 1. Syndrome of various n-input gates. 5
-
Fig. 3. Example 1.
I-S
(a)
SI
=~~~~~~~~~S ~ IS +S2 S
Sp
(b)
Fig. 4. Two blocks having shared inputs.
_ St SIS2 I)
S2 (d)
Fig. 2. Input-output syndrome relations.
Lemma 1: When the inputs are unshared, the input-output syndrome relations of the networks terminating in an IN-
VERTER, OR gate, AND gate, or EXCLUSIVE-OR gate are
given in Fig. 2. Proof: We will prove the input-output syndrome relation of the network terminating in an OR gate. The other proofs are similar. Denote by (n, K, S) the three-tuple describing the number of inputs, the number of minterms, and the syndrome realized by a given logic block. Let (nI, K1, SI) and (n2, K2, S2) be the three-tuples describing the two interconnected blocks in Fig. 2(b). Since the network is terminated in an OR gate, its output is 1 whenever any of the inputs to the OR gate is 1. Thus, the number of minterms K realized by the network is K=
K,2n2 + K22n' - K1K2.
Hence, S=
K 2nl+n2
=
K1 2nl
+
K2
_ 2n2
S1 + S2-s1S2.
K1 K2 2nl
2n2
Q.E.D. Notice that the input-output syndrome relations shown in Fig. 2 are similar to the input-output signal probability relations reported in [9]. Lemma I is useful when determining the syndrome of a fan-out-free combinational circuit. It also provides an algebraic tool to find the number of minterms realized by a fan-out-free network. Traditionally, one had to use mapping tools or equivalent methods to find the number of minterms realized by a given function, which were quite cumbersome. Example 1: Find the syndrome and number of minterms realized by the fan-out-free circuit of Fig. 3 without using a S
=
Karnaugh map or equivalent-normal form. We have 3 SI -2 , S2 = 1-2- 2=3 = S,3 = 2-13 . S1= 1-~2-2= 4 4 ~~~~~~~~8 Hence, 7 21 S4= 1 -(S2 + S3 - S2S3)= 32 S = S1S4= 128 K= S- 2n 21. Let K(F) and S(F) denote the number of minterms and the syndrome of a switching function F, respectively. In the case of interconnected blocks with shared (conjoint) inputs, the following lemma is very useful. Lemma 2: Let two blocks be interconnected as shown in Fig. 4. Let the Boolean functions realized by blocks B 1 and B2 be F and G, respectively. Then S(F + G) = S(F) + S(G) -S(FG). (1) Proof: Consider the network of Fig. 4. Let the number of inputs to the blocks realizing the functions F and G be n, and n2, respectively. Also, let p be the number of inputs which are common to both blocks. Thus, K(F + G) = K(F) * 2n2-P + K(G) * 2n1-P- K(FG), K(F + G) - K(F) K(G) K(FG) =
S(F + G)
2nl+n2-P
2ni
+
2n2
2nl+n2P '
S(F + G) = S(F) + S(G) - S(FG). Q.E.D. Note, that Lemma 2 reduces to Lemma 1 in the disjoint case. From Lemma 2 the following relations are implied:
S(FG)
=
1 -S(FG) = S(F) + S(G) + S(FG)-1 (2)
S(F ED G) =S(FG) + S(FG) (3) the syndrome of any combinational circuit can now be calculated. Let xi be an input to a combinational circuit and let the sum of products of the output function be expressed in the form
IEEE TRANSACTIONS ON COMPUTERS, VOL.
444
F = Axi + BXi + C
SYNDROME REGISTER
where A, B, and C do not depend on the input xi. Using relations (I)-(3) and Lemma 1 we can easily show that S(AC) + S(BC) + S(C) 2 (4) S(F) = (4)
Thus, by repeatedly applying (4), and each time eliminating another input, the output syndrome can be calculated. Example 2: Find the syndrome of the function F = xyz + wxz + xy + vWyz-.
AIC, = wz + wy + yv + yz BiCi = YZ.
S(A1CO) + 1/4+
1 16
2 Now, we express A4C1 in the form AIC, = A2y + B2Y+ C2
; ~~~FAULT INDICATION
-
Fig. 5. The test procedure.
Thus,
A3C3 = WU, S(A3C3) = 4
S(A2C2)
Thus,
S(F)
C)
EQUALITY CHECKER
+1
iTWyZ.
Note that S(x*x _x*) = 2-n and S(x + x + 1- 2 wherexi E $xi,xi}, i = 1,2,.. ,n. Thus S(CI) = 1/16, S(BICI) = 1/4
REFERENCE SYNDROME
B3C3 = w, S(B3C3) - 2
B1 =yz =
CUTIn
4
Solution: We can describe F in the form F= A1x + B1x + C1 where A1 =wz+y C1
C-29, NO. 6, JUNE 1980
+ x") =
(5)
where
42 (7) 2 +14 +5 88(7
By using (7), (6), and (5) we derive the desired syndrome to be 15 S(F) = 332 The syndrome calculation is described in the following recursive procedure. Procedure 1 Step 1: Express the output function in a sum of products form. Step 2: Use (4) to eliminate one input variable from the syndrome calculation. Step 3: If all the input variables have been eliminated accumulate the partial syndrome calculations and calculate the desired syndrome, otherwise go to Step 2. III. THE TESTABLE DESIGN
A2
=
W+V+Z
B2
=
0
C2
=
wz.
Thus
A2C2 = wz +wv+wz B2C2 = 0
S(AlCl)
=
S(A2C2) 2
4
Now we express A2C2 in the form
A2C2h+eA3z+B+ C3 where A3
= W
B2
=
C3
= Wv.
W
(6)
We are given a switching function to be realized with logic gates. Our purpose is to reach a syndrome-testable realization, namely, to have a design such that no fault can cause the circuit to have the same syndrome as the fault-free circuit. We would like to achieve this goal while inserting the minimum number of extra inputs. The class of faults we consider in this paper is the single stuck-at type. However, many multiple faults will be covered by the proposed design. In Section Ill-A we consider two-level circuits which are the most simple to design. Here, whenever we refer to a two-level circuit we implicitly imply an AND-OR circuit. The results can be easily extended to OR-AND circuits. As a consequence, our design will be applicable to t-he important class of programmable logic arrays (PLA's). In Section Ill-B we treat the class of general combinational circuits. The test procedure for the syndrome-testable circuits is shown in Fig. 5. Each possible input combination is applied to the CUT exactly once. The syndrome-register is a counter which counts the number of ones appearing on the output of the CUT. The equality checker checks the register's contents
SAVIR: DESIGN OF COMBINATIONAL CIRCUITS
with the expected syndrome. If the syndromes are equal, the CUT is reported to be fault-free; otherwise a fault is detected and the CUT is declared faulty. Note that the only difference between the syndrome and the ones-count is the implicit location of the binary point in the syndrome register. If the binary point is considered to be on the left-hand side of the number stored in the syndrome register, that number represents the syndrome, while if the binary point is viewed as being on the right-hand side of the number, this number represents the ones-count.
445
Proof: By Lemma 3, a circuit which is not syndrometestable can not be unate in all its variables. Hence, there exists at least one input, say xi, from which at least two reconverging paths emanate with nonequal inversion parties. Thus, the function F can be expressed in the form F = Ax1 + BY, + C where A, B, and C do not depend on variable xi, and both A and B include at least one term. Thus, a stuck-at fault (stuck-at-0 or stuck-at- I) at the fan-out branch xi will cause the faulty syndrome to be identical to the fault-free syndrome A. Syndrome- Testable Design of Two-Level Circuits if and only if Definition 2: The function F(x,, x2, . Xi,-i, , xn) is said S(AC) = S(BC), (8) to be positive (negative) in the variable xi, if there exists a disjunctive or conjunctive expression for it in which xi appears i.e., if and only if the number of minterms added by the growth only in uncomplemented (complemented) form. terms equal the number of minterms eliminated by the vanDefinition 3: The function F(x,, x2, ,Xi, xi, , x") is said ishing terms. Only stuck-at faults at input fan-out lines which to be unate in xi, if it is either positive or negative in xi. have property (8) can make the circuit syndrome-untestable. Q.E.D. Lemma 3: A two-level irredundant circuit which realizes a unate function in all its variables is syndrome-testable. Example 3: Consider the function Proof: It is sufficient to consider the set of stuck-at faults F = xz + y-. at the inputs to the AND gates and the fan-out branches. Any stuck-at-0 fault at the input to an AND gate causes the prime the fault-free syndrome is 1/2. The faulty syndrome induced by implicant (PI) realized by the AND gate to vanish. Any the fault z/O (we denote by b/O line b stuck-at-0 and by b/i stuck-at- I fault at the input of an AND gate corresponds to a line b stuck-at-1) is also 1/2. Thus, F is not syndrome-testgrowth term which covers the original PI and its adjacent able. It is already obvious at this point that two-level combinaneighbor. Since we assume that the circuit is irredundant both faults change the number of minterms realized by the function, tional circuits can be made syndrome-testable by controlling the "size" of the PI's with extra input insertion. For example, and thus change its syndrome. In order to complete the proof we have to consider the in- the function F of Example 3 may be made syndrome-testable fluence of stuck-at faults at the fan-out branches on the syn- by inserting one extra input w to realize the new function F = drome. Assume without loss of generality that the function is wxz + yz-. During normal operation the input w is fed with a positive in xi and that xi is a fan-out branch. Thus, the function constant logic 1, while for testing purposes it is used as a valid F can be expressed in the form input. The function F is now syndrome-testable since S(wx) # S(y). F = Axi + B Lemma 5: Every two-level irredundant combinational cirwhere both A and B do not depend on xi. The expression A has cuit can be made syndrome-testable by attaching control two or more terms. A stuck-at-0 at the input xi causes all the (extra) inputs to the AND gates. Proof: See Appendix A. PI's associated with xi to vanish. A stuck-at-I at input xi From Lemmas 3 and 4 it is evident that the candidates for causes all the PI's associated with xi to cover a greater number of minterms. By similar argument to that presented earlier we syndrome-untestability are the nonunate input lines. In order conclude that a fault at input xi changes the syndrome of the to keep track of the actual lines in which the function F is function. Q.E.D. syndrome-untestable we define the set Definition 4: Two paths that emanate from a common line T = {xi IF is syndrome-untestable in xi. and reconverge at some forward point are said to be reconClearly, verging paths [1]. Definition 5: The inversion parity [4] of a reconverging path T c {xi IF is nonunate in xi} is equal to the number of inversions modulo 2 in the path, i.e., Our goal is to reach a syndrome-testable realization of a the number of inversions modulo 2 between the point of digiven function while adding the minimum number of extra vergence and the point of reconvergence. In the case of two-level circuits, the points of divergence can inputs. We choose to add the control inputs in an uncompleonly be at the input branches, and the point of reconvergence mented form (complemented inputs are acceptable as well). at the output line.-The inverters can appear only at the inputs By Lemma 3 the modified function will always be syndrometestable in the control inputs. to the AND gates. Procedure 2 describes an algorithm for designing synLemma 4: There exist two-level irredundant circuits which drome-testable two-level combinational circuits. The synare not syndrome-testable.
446
IEEE TRANSACTIONS ON COMPUTERS, VOL.
drome-testable design is achieved by modifying the original irredundant sum of products. The modification requires an introduction of a nearly minimal number of control inputs. We use the following notation in describing the algorithm: set of control lines. C prime implicant number i. PIi PI set of prime implicants. j a number specifying how many times the function has been modified so far. F(1) the jth modified function. the set T which corresponds to function F(j). TU) FLAG an identifier describing whether the function should.be modified with an existing control variable or with a new one.
PI = IPI1, P12, Derive T(°)
X4X5,
, PIk
k
(Z denotes Boolean sum).
i=l
If T(J) stop, F(j) is syndrome-testable. If C = 0 go to Step 4. Step 3: For each cn C and Plj E PI derive function
4: Add
new
For each PIJ
E
input:
TOPI'
for
If I
=
u
{cb).
PI derive TO6iD for the function i#j
Let I T(O)
C
Phi
+
c, * PIj.
min{I TQ4)IO I
T()I then FLAG
=
=
0, otherwise FLAG
=
1.
Step 5: j~j+1 If FLAG = T(i)
=
0 then
T(a1); PI:
If FLAG
= 1
then
ca
Pl,
c, PIi, T(i) T(O$); PIz Go to Step 2. By Lemma 5. Procedure 1 is guaranteed to halt. Although, =
I
CIX1X2 + X1X3 + X2X3 + X4X5 + X4X5.
T(2)
=
{X3}
=
C1X1x2 + X1X3 + X2X3 + C1X4X5 + X4X5.
Third pass of Procedure 1 yields T(33) g
I (when the minimum is attained
C
=
Second pass of the algorithm gives
by several members choose one arbitrarily). If I T(a I = I T()| go to Step 4. Otherwise FLAG = 0, go to Step 5. Step
= X4X5.
F()
E Pli + cn * P1I.
min I I T(DI)
P15
=
isj n.j
X1X2 + X1X3 + X2X3 + X4X5 + x4x5.
First pass of Procedure 1 yields T(°) = IX1, X2, x3, X4, x5} FM = F TO1) X3, X4, X5}
-
=
at each iteration of the algorithm the optimal input insertion (or one of the optimal insertions in the case of multiple choices) is obtained, an overall optimal solution is not guaranteed. The reason for that is that local optimization does not necessarily lead to global optimization.
Solution: Let PI1 = x1I2, P12 = Y1x3, P13 = X2X3, P14 =
F(j) = E Pli
Let | Tag) I
Fig. 6. The syndrome-testable design for Example 4.
F=
Step 2:
=
C,
Example 4: Find the syndrome-testable design with nearly minimum number of control inputs for the function
Procedure 2 Step I -Initialization: j=O C='k FLAG = 0
C-29, NO. 6, JUNE 1980
F
= CiXX2 + C2X1X3 + X2X3 + C1X4X5 + X4X5.
The testable design is shown in Fig. 6. The only difficulty involving the design arises when n is large. Since~the test procedure requires the application of all 2 n input combinations, the design will be worthwhile for n < 20 (which is equivalent to about 1 s of testing with a 1 MHz machine). However, for n > 20, the problem can be overcome by designing the circuit with subcircuits, as shown in Fig. 7, such that every subcircuit has no more than 20 inputs. This improvement will cost in m = rq/201 extra outputs, where q is the number of inputs to the AND gates (the extra OR gates do not constitute a problem in present day technology). Each subcircuit must be designed to be syndrome-testable, and can be tested by no more than 220 inputs. Thus, the total test length will be approximately m220, which is equivalent to about m seconds of testing. Note that faults at the inputs of the OR gate generating the objective functions are not covered when the individual subcircuits are syndrome-tested. However, if we let the OR gates of the individual subcircuits have a tristate capability we can syndrome-test the OR gate which generates the objective function by directly exercising its inputs and thus test for the uncovered faults mentioned above.
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SAVIR: DESIGN OF COMBINATIONAL CIRCUITS
Using Lemmas I and 2, we have S(F) = S(ACg) + S(BCg) + S(C) S(B + C) = S(BC) + S(C). Thus, the fault g/O is syndrome-untestable if and only if S(ACg) + S(BCg) = S(BC), or Q.E.D. S(ACg) = S(BCg). Corollary 1: Let g be any line in an irredundant combinaFig. 7. The proposed partition for large two-level circuits. The input lines may be shared between subcircuits, although not shown explicitly. tional circuit composed of AND, OR, NAND, NOR, and NOT gates. If there exists only one path from g to the circuit output, the function F is syndrome-testable with respect to faults in B. Syndrome- Testable Design of General Combinational g. Circuits Proof: Directly from Lemmas 6 and 7. EXCLUSIVE-OR and EQUIVALENCE gates are source of Lemma 6: Every fan-out-free inrredundant combinational circuit, composed of AND, OR, NAND, NOR, and NOT gates problems to syndrome testing because of their inherent nonunateness. The following lemma displays the conditions is syndrome-testable. Proof: In a fan-out-free circuit there is a unique path from necessary so that the faults on the inputs of an EXCLUSIVE-OR any line to the circuit output. Thus, if we label a given line by gate be syndrome-untestable. The corresponding conditions g, the output F will be either positive or negative in g, de- for an EQUIVALENCE gate can be obtained from Lemmas 1 pending on the inversion parity of the path originating at g and and 8. , x,) and Lemma 8: Let F = g @ h, where g = g(xI, x2, terminating at the output line. Assume without loss of generality that F is positive in g. We can, therefore, represent F h = h(xI, x2, , xn). The fault h/O is syndrome-untestable if and only if as F = Ag + b
S(gh) = S(gh)
where
(11)
and the fault h/I is syndrome-untestable if and only if
g = g(xil, x,2, , and both A and B do not depend on xi1, xi2, ,xii A stuck-at-0 fault on line g eliminates all the minterms associated with Ag, and does not create any new ones. Therefore, the circuit is syndrome-testable with respect to g/0. In order to prove that g/ 1 is syndrome-testable, we use a contrapositive approach. Assume that g/ 1 is syndrome-untestable. Thus, all the minterms covered by Ag are already covered by F. Therefore F can be represented by F=Ag + Ag + B = A + B which is independent of g, contradicting the previous asQ.E.D. sumption that F is positive in g. Lemma 7: Let g = g(xi , xiI,.. ,xin) be a line in a general combinational circuit. Let the equivalent sum of products of the function F with respect to line g be F = Ag + Bg + C. Then the fault g/0 is syndrome-untestable if and only if
S(ACg)
=
S(BCg)
(9)
and, the fault g/ 1 is syndrome-untestable if and only if S(ACg) = S(BCg). (10) Proof: We prove relation (9). The proof of (10) is similar. The fault g/O is syndrome-untestable if and only if S(F) = S(B + C).
S(gh) = S(kh).
(12) Proof: We prove (1 1). The proof of relation (1 2) is similar. The fault h/0 is syndrome-untestable if and only if S(g @ h) = S(g). Thus, S(gh) + S(gh) = S(g) Q.E.D. S(kh) = S(gh). Corollary 2: Let F = g CD h, where g = g(xi , xi2, ... Xiu), h = h(yi,, MI , , yi,) and {xi,, , Xi"} n tyi1, , yiuj = X. Then, faults on line h(h/O or h/I) are syndrome-untestable if and only if
S(g)
=
1/2.
(13)
Proof: Directly from Lemmas 1 and 8. It is evident from Corollary 2 that attaching an extra input to an EXCLUSIVE-OR gate will not fix the syndrome-untestable condition since relation (13) will hold for the new input. There are two basic approaches to fix the syndrome-untestable condition with respect to inputs of an EXCLUSIVE-OR gate. One way of handling the problem is by breaking the inherent symmetry of the gate. This can be done when the actual implementation of the gate is known. For example, in the case where the EXCLUSIVE-OR gate is implemented by NAND gates, the output can be made syndrome-testable with respect
IEEE TRANSACTIONS ON COMPUTERS, VOL. C-29, NO. 6, JUNE 1980
448 c
%F
F=cx x- -+X X
1
Fig. 8. A syndrome-testable modification of an EXCLUSIVE-OR gate. h ,-
g C
Fig. 9. Using an extra AND gate and an extra input to fix the syndromeuntestable condition in h(h/O or h/ I).
to faults at the inputs by adding a control input c as shown in Fig. 8. The second approach is to add a control input via an extra AND gate to the input lines of the EXCLUSIVE-OR gate as shown in Fig. 9. The problem is how to modify the design of a general combinational circuit so that it will be syndrome-testable. We try to do it by means of control input insertion and/or a small amount of extra logic. The control inputs connected to AND and NAND gates should be applied with a constant 1 under normal operation, while the control inputs attached to OR anid NOR gates should be applied with a constant 0 under normal operation. Any control input connected to AND or NAND gates cannot also be connected to OR or NOR gates. From the previous lemmas and corollaries it is clear that the candidate lines for syndrome-untestability are the fan-out lines, which have unequal inversion parities along its reconverging branches, the lines that feed them (directly or indirectly) and inputs and outputs of EXCLUSIVE-OR gates. The following procedure describes the modification algorithm.
Procedure 3 Step 1: Find the set of lines in which the function is syndrome-untestable by finding the equivalent sum of products with respect to the candidate lines for syndrome-untestability. Step 2: Use Procedure 2 with the following modifications: PI - Set of AND, NAND, OR, NOR gates. ij PIi + c. Pbj -The function obtained by attaching the control input c to gate number j. For the faults at the inputs of EXCLUSIVE-OR gates, use either the method of Fig. 8 or Fig. 9. As of today the author still lacks a proof that every multilevel combinational circuit can be modified to be syndrometestable by extra input insertions. However, our experience with small size circuits show that Procedure 3 does generate a syndrome-testable design. In order to make the syndrome-test procedure feasible it is necessary to partition the general combinational circuit to subcircuits, in such a way that the total testing time will be of reasonable size. In order to do that we use the previous concept that the time required for exhaustive testing of a subcircuit
which has no more than 20 inputs is acceptable. Fig. 10 shows the partitioning method. Fig. 10 shows an imbedded subcircuit Mk and its interconnection with previous subcircuits. Subcircuit Mk might in general receive inputs from two sources: primary inputs to the circuit and output from some other subcircuits (like Mi and Mj in Fig. 10). Since the inputs of the latter kind, namely those which are outputs of previous subcircuits, may in general depend on more than 20 inputs, an exhaustive exercise of subcircuit Mk will require more testing time than what we consider to be acceptable. Therefore, for those cases where the subcircuit Mk depends directly or indirectly on more than 20 inputs, the outputs of subcircuits like Mi and Mj in Fig. 10, may be designed to have a tristate capability. Thus, if we provide an extra I/O pin at these tristate outputs, we may have the capability of both observing the syndrome-test results when subcircuits like Mi and Mj are tested, and of directly exercising the input lines of subcircuit Mk when the outputs of Mi and Mj are held at the high impedance state. In this way, every subcircuit can be tested in no more than 220 inputs, which is equivalent to about 1 s of testing time. Therefore, a circuit which is partitioned to m subcircuits may be syndrome-tested in no more than m seconds. The pin-penalty paid for this partitioning is one pin for each tristate output. We have calculated the partitioning pin-penalty for uniform trees [2] of up to 1024 inputs and found it to be no more than 7 percent. Since the conditions of syndrome-untestability are very strict [i.e., relations (9) and (10)] it is believed that, in general, very few lines will meet them. Thus, only a few extra inputs will be required to achieve a syndrome-testable design. Table I displays a few MSI combinational logic, their number of pins and the number of extra pins needed to make them syndrometestable. As seen from Table I, the number of extra pins does not exceed 1 (or 5 percent) for these functions. This is not surprising because one extra input can invalidate the syndrome-untestable condition in various portions of the circuit. Because of the strictness of the syndrome-untestable condition, it is feasible to correct untestable conditions of several faults by means of only one additional input. Fig. 11 shows a syndrome-testable modification of SN74,181. The modification requires one extra input and two extra AND gates. Note that the extra AND gates could have been avoided if we assumed a certain realization of the EXCLUSIVE-OR gates (see Fig. 8).
449
SAVIR: DESIGN OF COMBINATIONAL CIRCUITS Extra output I
TABLE I THE NUMBER OF CONTROL INPUTS NECESSARY IN ORDER TO MAKE THE CIRCUITS SYNDROME-TESTABLE AS A FUNCTION OF NUMBER OF PINS FOR VARIOUS MSI COMBINATIONAL LOGIC
Function
Extra output
Fig. 10. The proposed partitioning for general combinational circuits. The outputs of Mi and Mj are designed to have a tristate capability.
-
Dual 4-line-to-I-line Data selectors/Mux SN74153 Data selectors/ Mux SN74150 Mux SN74151 Dual carry save adders SN74183 Look-ahead carry generators SN74182 Arithmetic logic units SN74181 Total
Pins
# Control inputs
16
1
24
1
16 14
1 1
16
0
24
1
110
5
Fig. 11. Syndrome-testable design of arithmetic logic units, SN741 81, requiring one extra input C and two extra gates (marked). The output syndromes are rounded to four decimal digits.
IV. SUMMARY AND CONCLUSIONS A new approach to the design of testable combinational circuits was presented in this paper. The design method is to modify given realizations by inserting extra I/O so that the final circuit will be syndrome-testable. A procedure that produces a nearly minimal number of extra input insertions was described. It was also shown how to partition very large combinational circuits to subcircuits such that the total testing time
will be of acceptable length. Although we restricted ourselves, in this paper, to single-output networks, the ideas easily generalize to multiple-output networks as well. It is well known that one of the most severe restrictions on IC manufacturers is the number of pins per chip. Although the testable design requires an increase in the number of pins, it is believed that the pin overhead is very low because of the strictness of the syndrome-untestable condition. In this paper we have mainly used extra input lines to
IEEE TRANSACTIONS ON COMPUTERS, VOL. c-29, NO. 6, JUNE 1980
450
achieve a syndrome-testable design. It may be possible, though, to use also extra logic in producing the testable design. This, in fact, may be very attractive since, in general, chip area is more available than I/O pins. We are currently investigating the possibility of trading off some of the extra I/O pins with extra logic. It is important to mention that the syndrometestable design can be superimposed on LSSD (level-sensitive scan design) [101. If this is done, the extra I/O pins required by the syndrome-testable design are actually implemented by extra SRL's (shift register latches) connected to the scan path. Thus, the I/O pin-penalty paid by the syndrome-testable design is traded off with extra logic.
S[(a1 + a5)3a9] + S[(a1 + a6)49] -
= alxi + a2Oi +
a3Xj + a4xj + a5xixj + a6XiX + a7X X +
8XiXj
+ a9
where ak do not depend on xi and xj for all k = 1, 2, , 9. Since xi E T(°), then- as a consequence of Lemma 4 we have
S[(a1 + a5)&39] + S[(al + a06)469]
S[(a3 + °5)a9] + -S[(a3 + 2
Since have
xi
i
T(°), then
+
as a consequence of Lemma 4 we
S[(a3 + a5s)0a9] + S[(a3 + aa7)9] $ S[(a4 + a6)a1a9] + S[(a4 + a8)2a9]
In order to correct the syndrome-untestable condition in xi we modify the function in the form (other ways are possible
also)
FO) =
c1laix
+
a2Xi
+
a3Xj + a4Xj + a5XiXj + a6XiXj + a7-iXj + a8xiyj + ag.
According to the assumption stated in the Lemma, FM') is syndrome-testable in xi and untestable in xj. This is translated to the following two conditions (by applying relation (8) to F(1)): Since xi $ TO1) we have
+ S[(a3 +
a7)09J
a5)(1al9]
IS[(a4 + a6)ala9]
(17)
2
by combining relations (14) and (16) we get that
(18) ala3a5°a mil 0 or a la4a°6a°l9 X 0 by combining relations (15) and (17) we get that (19) S[(a3 + a5)ajag] z S[(a4 + 6)aal9]. We have to show now that if the function is modified again as
(2)= c1c2x + +
ajx- + a3X1 +
a4+ a5XiXj a6Xix + a-7yiXj + a8XiXj + ag
it will be syndrome-testable in both xi and xj. In order to do this we show that the condition for syndrome-untestability in xi and xj does not hold for F(2). The condition for syndromeuntestability in xi for the function F(2) becomes
S[(al + a5)a3a9] + S[(a1 + a6)a4a9] -34 [S(a030509) + S(ajal4a 6a19)] S[(a2 + a7)39] + S[(a2 + a8)a4a9].
(20)
From relations (14) and (18) we easily see that (20) is false. The condition for syndrome-untestability in xj for the function F(2) becomes
S[(a3 + a5) (15)
(16)
S[(a4 + a6)a1a9] + S[(a4 + a8)29]
=
=
S[(a2 a7)a3a9] S[(a2 a8)i4a9]. (14) +
+
469)]
Since xi ET&) we have
+
Before proving Lemma 5, we first prove the following lemma. Lemma 9: Let T be the set of syndrome-untestable input lines. Let T(j) denote the set T of the jth modified function, j = 0, 1, 2,... , as defined previously in the paper. Let xi E T(°) and xi $ T(°), be two input lines to the two-level circuit. If, by attaching a control input cl to a (set of) PI('s), the condition of syndrome-untestability in xi is corrected and in xj is spoiled, namely xi $ T(1) and xj E T(O), then by attaching another control input c2 to the same (set of) PI('s) the spoiled condition in xj is corrected again, namely, xi, xj1 T(2). Proof: The function F can be expressed in the form
[S(al a5a9) + S(al
$£ S[(a2 + a7)&3a9] + S[(a2 + a8)a4a9].
APPENDIX A
F(°)
2
+ =
+
4
1
9] + S[(a3 +
a7)a2ag9]
S[(a3 + a5)a°1a9]
S[(a4 + a6)aia9] + S[(a4 + a8)a2a] 4
S[(a4 + a6)a°1a9].
(21)
From relations (17) and (19) we can easily see that (21) is also false. Thus, F(2) is syndrome-testable in both xi and xj. Q.E.D. Proofof Lemma 5: Let T be the set of syndrome-untestable input lines. From Lemma 9 we know that by adding at most 2 extra inputs we can reduce the cardinality of T by at least one. Thus, by adding at most 21 TI control inputs the function can be modified to be syndrome-testable. Q.E.D.
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ACKNOWLEDGMENT
The aLithor wishes to thank Prof. E. J. McCluskey, and the members of the Center for Reliable Computing at Stanford University for their helpful criticism. Thanks are also due to the members of the VLSI DA Group at the T.J. Watson Research Center, Yorktown Heights, NY. The referees comments are, also, greatly appreciated. REFERENCES [1] D. E. Armstrong, "On finding a nearly minimal set of fault detection tests for combinational logic nets," IEEE Trans. Electron. Comput., vol. EC-15, pp. 66-73, Feb. 1966. [2] J. P. Hayes, "On realization of Boolean functions requiring a minimal or near-minimal number of tests," IEEE Trans. Comput., vol. C-20, pp. 1506-1513, Dec. 1971. [3] --, "Transition count testing of combinational circuits," IEEE Trans. Comput., vol. C-25, pp. 613-620, June 1976. [4] I. Kohavi and Z. Kohavi, "Detection of multiple faults in combinational logic networks," IEEE Trans. Comput., vol. C-21, pp. 556-568, June 1972. [5] J. Losq, "Referenceless random testing," in Proc. 6th Ann. Symp. on Fault-Tolerant Comput., Pittsburgh, PA, pp. 108-113, June 21-23, 1976. [6] J. P. Roth, W. G. Bouricius, and P. R. Schneider, "Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits," IEEE Trans. Electron. Comput., vol. EC-16, pp. 567-580, Oct. 1967. [7] J. Savir, "Syndrome-testable design of combinational circuit," in Proc. 9th Ann. Int. Symp. on Fault-Tolerant Computing, June 1979, pp. 137-140.
[8] A. Tzidon, l. Berger, and M. Yoeli, "A practical approach to fault detection in combinational networks," IEEE Trans. Comput., vol. C-27, pp. 968-971, Oct. 1978. [9] K. P. Parker and E. J. McCluskey, "Probabilistic treatment of general combinational networks," IEEE Trans. Comput., vol. C-24, pp. 668-670, June 1975. [10] E. B. Eichelberger and T. W. Williams, "A logic design structure for LSI testability," in Proc. 14th Ann. Design Automation Conf., June 1977, pp.,462-468. Jacob Savir (M'78) was born in Bucharest, Romania, on December 13, 1946. He received the B.Sc. (cum laude) and M.Sc. degrees in electrical engineering from the Technion-Israel Institute of Technology, Haifa, Israel, in 1968 and 4973, respectively, the M.S. degree in statistics and Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 1977 and 1978, re-
spectively.
In the summer of 1967 he was a student trainee in ASEA, Sweden, working on high-power control systems. From 1968 to 1972 he served as an electronic engineer in the Israel Defence Forces. From 1972 to 1974 he worked as a Research Assistant at the Department of Electrical Engineering, Technion, Israel. From 1974 to 1975 he was a project engineer in the Israel Ministry of Defence. From 1975 to 1978 he worked, first as a Ph.D. student and later as an IBM Post-Doctoral Fellow, with Prof. E. J. McCluskey on intermittent fault test strategies and testable design of digital systems. He joined IBM in 1978 at the T. J. Watson Research Center, Yorktown Heights, NY, where he is currently a research staff member, investigating DA approaches to VLSI. His research interests include, testing and diagnosis of failures, testable design, fault simulation and reliability of digital systems. He authored several papers in the field of testing for logic faults and testable design of digital circuits. Dr. Savir is a member of Sigma Xi.
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis MIRON ABRAMOVICI, STUDENT MEMBER, IEEE, AND MELVIN A. BREUER, SENIOR MEMBER, IEEE
Abstract-In this paper we present a new approach to multiple fault diagnosis in combinational circuits based on an effect-cause analysis. The main vehicle of our approach is the deduction of internal line values in a circuit under test N*. The knowledge of these values allows us to Manuscript received August 6, 1979; revised January 21, 1980. This work was supported in part by the National Science Foundation under NSF Grant MCS78-26 153. M. Abramovici was with the Department of Eleclrical Engineering, University of Southern California, Los Angeles, CA 90007. He is now with Bell Laboratories, Naperville, IL 60540. M. A. Breuer is with the Departments of Electrical Engineering and Computer Science, University of Southern California, Los Angeles, CA 90007.
identify fault situations in N* (causes) which are compatible with the applied test and the obtained response (the effect). A fault situation specifies faulty as well as fault-free lines. Other applications include identifying the existence of nonstuck faults in N* and determination of faults not detected by a given test, including redundant faults. The latter application allows for the generation of tests for multiple faults without performing fault enumeration. Our technique does not require a fault dictionary, fault enumeration or even the knowledge of the expected values in the fault-free circuit. Index Terms-Combinational networks, deduction of internal values, effect-cause analysis, fault diagnosis, multiple redundant faults, multiple stuck-at faults.
0018-9340/80/0600-0451$00.75 (D 1980 IEEE
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C-29, NO. 6, JUNE 1980
Syndrome-Testable Design of Combinational Circuits JACOB SAVIR, Abstract-Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size. In this paper we describe a method of designing combinational circuits in such a way that their test procedure will require the knowledge of only one characteristic of the fault-free circuit, called the syndrome. This solves the storage problem associated with the test procedure. The syndrome-test procedure does not require test vector generation, and thus the expensive stage of test generation and fault simulation is eliminated. Index Terms-Combinational circuit, fan-out-free circuit, minterm, prime implicant, single fault, stuck-at fault.
I. INTRODUCTION
I N THIS paper we restrict ourselves to the class of permanent stuck-at faults, i.e., a faulty line appears logically as if it is either stuck at a constant 0, or at a constant 1. The classical approach [6] to the problem of testing combinational circuits was to design a test set which detects all faults from a prescribed set, and store both the test set and the expected output to the individual test vectors. Whenever a circuit was tested, the actual response and the expected output were compared to determine whether or not the circuit under test (CUT) was fault-free. For most practical circuits manufactured today, this approach requires test generation, possibly coupled with fault simulation, and high data volumes for implementation. The cost and time required to implement the classical approach grows quickly with the levels of integration. In this paper we show that by using a new method it is possible to reduce the storage requirement considerably at a very low cost, and avoid the expensive stage of test generation. Recently, a few other approaches to the testing problem have been presented in the literature. In [3] the method of transition counts is described. This method has the advantage of drastically reducing the storage requirement, but it is difficult to determine a proper test input sequence. In [5] a referenceless testing method is described. Its disadvantage lies in requiring very long test patterns to achieve a reasonable detection probability. In [8], a practical test procedure which employs testing for some functional attributes of combinational
MEMBER, IEEE
circuits is described. It is shown in [8] that by testing for specific functional properties it is possible to determine whether or not some classes of combinational circuits suffer any stuck-at faults. In this paper we show a method of designing combinational circuits so that the storage requirement for implementing the test procedure will be restricted to only one number, called the syndrome of the circuit, which is based on the number of minterms realized by the switching function. Since a fault-free and faulty circuit do not necessarily have different syndromes, special design of the combinational circuit is required in order to make it syndrome-testable. We say that a circuit is syndrome-testable if the syndrome of any faulty version of a circuit, induced by a single stuck-at fault, does not equal the syndrome of the fault-free circuit. Thus, the test procedure consists of applying all input combinations to the CUT and recording its syndrome (usually implemented by a counter). If the actual syndrome equals the expected syndrome, the circuit is fault-free; otherwise a fault is detected and the procedure stops. This approach has both the advantage of requiring only one reference and the advantage of avoiding the test generation process. In order to reduce the test length for circuits with large number of inputs (for instance more than 20), the combinational circuit is partitioned into subcircuits and designed so that each subcircuit is syndrome-testable. In this way, each subcircuit can be tested separately in no more than 1 s. The penalty paid for producing a syndrome-testable design is a slight increase in the number of pins. In Section II various syndrome properties of combinational circuits are described. Section III describes the proposed testable design. The paper concludes with a brief summary.
II. SYNDROME-PROPERTIES OF COMBINATIONAL CIRCUITS Definition 1: The syndrome of a Boolean function is defined as S = K/2n, where K is the number of minterms realized by the function and n the number of binary input lines. The syndrome is a functional property. Thus, various realizations of the same function will have the same syndrome. Clearly, 0 < S < 1, where the boundaries are attained by the constant functions. The syndrome of various n-input gates is shown in Fig. 1. It is useful to find the input-output syndrome relations beManuscript received August 27, 1979; revised February 7, 1980. This work was initiated while the author held a post-doctoral position at Stanford Unitween various interconnected sections of a logic circuit. These versity, Stanford, CA 94305. input-output relations are especially simple when the associThe author is with IBM Thomas J. Watson Research Center, Yorktown ated sections have unshared (disjoint) inputs. Heights, NY 10598. 0018-9340/80/0600-0442$00.75 © 1980 IEEE
443
SAVIR: DESIGN OF COMBINATIONAL CIRCUITS
SI
S=2 -n
S=1-2
I
S=2
>
Fig. 1. Syndrome of various n-input gates. 5
-
Fig. 3. Example 1.
I-S
(a)
SI
=~~~~~~~~~S ~ IS +S2 S
Sp
(b)
Fig. 4. Two blocks having shared inputs.
_ St SIS2 I)
S2 (d)
Fig. 2. Input-output syndrome relations.
Lemma 1: When the inputs are unshared, the input-output syndrome relations of the networks terminating in an IN-
VERTER, OR gate, AND gate, or EXCLUSIVE-OR gate are
given in Fig. 2. Proof: We will prove the input-output syndrome relation of the network terminating in an OR gate. The other proofs are similar. Denote by (n, K, S) the three-tuple describing the number of inputs, the number of minterms, and the syndrome realized by a given logic block. Let (nI, K1, SI) and (n2, K2, S2) be the three-tuples describing the two interconnected blocks in Fig. 2(b). Since the network is terminated in an OR gate, its output is 1 whenever any of the inputs to the OR gate is 1. Thus, the number of minterms K realized by the network is K=
K,2n2 + K22n' - K1K2.
Hence, S=
K 2nl+n2
=
K1 2nl
+
K2
_ 2n2
S1 + S2-s1S2.
K1 K2 2nl
2n2
Q.E.D. Notice that the input-output syndrome relations shown in Fig. 2 are similar to the input-output signal probability relations reported in [9]. Lemma I is useful when determining the syndrome of a fan-out-free combinational circuit. It also provides an algebraic tool to find the number of minterms realized by a fan-out-free network. Traditionally, one had to use mapping tools or equivalent methods to find the number of minterms realized by a given function, which were quite cumbersome. Example 1: Find the syndrome and number of minterms realized by the fan-out-free circuit of Fig. 3 without using a S
=
Karnaugh map or equivalent-normal form. We have 3 SI -2 , S2 = 1-2- 2=3 = S,3 = 2-13 . S1= 1-~2-2= 4 4 ~~~~~~~~8 Hence, 7 21 S4= 1 -(S2 + S3 - S2S3)= 32 S = S1S4= 128 K= S- 2n 21. Let K(F) and S(F) denote the number of minterms and the syndrome of a switching function F, respectively. In the case of interconnected blocks with shared (conjoint) inputs, the following lemma is very useful. Lemma 2: Let two blocks be interconnected as shown in Fig. 4. Let the Boolean functions realized by blocks B 1 and B2 be F and G, respectively. Then S(F + G) = S(F) + S(G) -S(FG). (1) Proof: Consider the network of Fig. 4. Let the number of inputs to the blocks realizing the functions F and G be n, and n2, respectively. Also, let p be the number of inputs which are common to both blocks. Thus, K(F + G) = K(F) * 2n2-P + K(G) * 2n1-P- K(FG), K(F + G) - K(F) K(G) K(FG) =
S(F + G)
2nl+n2-P
2ni
+
2n2
2nl+n2P '
S(F + G) = S(F) + S(G) - S(FG). Q.E.D. Note, that Lemma 2 reduces to Lemma 1 in the disjoint case. From Lemma 2 the following relations are implied:
S(FG)
=
1 -S(FG) = S(F) + S(G) + S(FG)-1 (2)
S(F ED G) =S(FG) + S(FG) (3) the syndrome of any combinational circuit can now be calculated. Let xi be an input to a combinational circuit and let the sum of products of the output function be expressed in the form
IEEE TRANSACTIONS ON COMPUTERS, VOL.
444
F = Axi + BXi + C
SYNDROME REGISTER
where A, B, and C do not depend on the input xi. Using relations (I)-(3) and Lemma 1 we can easily show that S(AC) + S(BC) + S(C) 2 (4) S(F) = (4)
Thus, by repeatedly applying (4), and each time eliminating another input, the output syndrome can be calculated. Example 2: Find the syndrome of the function F = xyz + wxz + xy + vWyz-.
AIC, = wz + wy + yv + yz BiCi = YZ.
S(A1CO) + 1/4+
1 16
2 Now, we express A4C1 in the form AIC, = A2y + B2Y+ C2
; ~~~FAULT INDICATION
-
Fig. 5. The test procedure.
Thus,
A3C3 = WU, S(A3C3) = 4
S(A2C2)
Thus,
S(F)
C)
EQUALITY CHECKER
+1
iTWyZ.
Note that S(x*x _x*) = 2-n and S(x + x + 1- 2 wherexi E $xi,xi}, i = 1,2,.. ,n. Thus S(CI) = 1/16, S(BICI) = 1/4
REFERENCE SYNDROME
B3C3 = w, S(B3C3) - 2
B1 =yz =
CUTIn
4
Solution: We can describe F in the form F= A1x + B1x + C1 where A1 =wz+y C1
C-29, NO. 6, JUNE 1980
+ x") =
(5)
where
42 (7) 2 +14 +5 88(7
By using (7), (6), and (5) we derive the desired syndrome to be 15 S(F) = 332 The syndrome calculation is described in the following recursive procedure. Procedure 1 Step 1: Express the output function in a sum of products form. Step 2: Use (4) to eliminate one input variable from the syndrome calculation. Step 3: If all the input variables have been eliminated accumulate the partial syndrome calculations and calculate the desired syndrome, otherwise go to Step 2. III. THE TESTABLE DESIGN
A2
=
W+V+Z
B2
=
0
C2
=
wz.
Thus
A2C2 = wz +wv+wz B2C2 = 0
S(AlCl)
=
S(A2C2) 2
4
Now we express A2C2 in the form
A2C2h+eA3z+B+ C3 where A3
= W
B2
=
C3
= Wv.
W
(6)
We are given a switching function to be realized with logic gates. Our purpose is to reach a syndrome-testable realization, namely, to have a design such that no fault can cause the circuit to have the same syndrome as the fault-free circuit. We would like to achieve this goal while inserting the minimum number of extra inputs. The class of faults we consider in this paper is the single stuck-at type. However, many multiple faults will be covered by the proposed design. In Section Ill-A we consider two-level circuits which are the most simple to design. Here, whenever we refer to a two-level circuit we implicitly imply an AND-OR circuit. The results can be easily extended to OR-AND circuits. As a consequence, our design will be applicable to t-he important class of programmable logic arrays (PLA's). In Section Ill-B we treat the class of general combinational circuits. The test procedure for the syndrome-testable circuits is shown in Fig. 5. Each possible input combination is applied to the CUT exactly once. The syndrome-register is a counter which counts the number of ones appearing on the output of the CUT. The equality checker checks the register's contents
SAVIR: DESIGN OF COMBINATIONAL CIRCUITS
with the expected syndrome. If the syndromes are equal, the CUT is reported to be fault-free; otherwise a fault is detected and the CUT is declared faulty. Note that the only difference between the syndrome and the ones-count is the implicit location of the binary point in the syndrome register. If the binary point is considered to be on the left-hand side of the number stored in the syndrome register, that number represents the syndrome, while if the binary point is viewed as being on the right-hand side of the number, this number represents the ones-count.
445
Proof: By Lemma 3, a circuit which is not syndrometestable can not be unate in all its variables. Hence, there exists at least one input, say xi, from which at least two reconverging paths emanate with nonequal inversion parties. Thus, the function F can be expressed in the form F = Ax1 + BY, + C where A, B, and C do not depend on variable xi, and both A and B include at least one term. Thus, a stuck-at fault (stuck-at-0 or stuck-at- I) at the fan-out branch xi will cause the faulty syndrome to be identical to the fault-free syndrome A. Syndrome- Testable Design of Two-Level Circuits if and only if Definition 2: The function F(x,, x2, . Xi,-i, , xn) is said S(AC) = S(BC), (8) to be positive (negative) in the variable xi, if there exists a disjunctive or conjunctive expression for it in which xi appears i.e., if and only if the number of minterms added by the growth only in uncomplemented (complemented) form. terms equal the number of minterms eliminated by the vanDefinition 3: The function F(x,, x2, ,Xi, xi, , x") is said ishing terms. Only stuck-at faults at input fan-out lines which to be unate in xi, if it is either positive or negative in xi. have property (8) can make the circuit syndrome-untestable. Q.E.D. Lemma 3: A two-level irredundant circuit which realizes a unate function in all its variables is syndrome-testable. Example 3: Consider the function Proof: It is sufficient to consider the set of stuck-at faults F = xz + y-. at the inputs to the AND gates and the fan-out branches. Any stuck-at-0 fault at the input to an AND gate causes the prime the fault-free syndrome is 1/2. The faulty syndrome induced by implicant (PI) realized by the AND gate to vanish. Any the fault z/O (we denote by b/O line b stuck-at-0 and by b/i stuck-at- I fault at the input of an AND gate corresponds to a line b stuck-at-1) is also 1/2. Thus, F is not syndrome-testgrowth term which covers the original PI and its adjacent able. It is already obvious at this point that two-level combinaneighbor. Since we assume that the circuit is irredundant both faults change the number of minterms realized by the function, tional circuits can be made syndrome-testable by controlling the "size" of the PI's with extra input insertion. For example, and thus change its syndrome. In order to complete the proof we have to consider the in- the function F of Example 3 may be made syndrome-testable fluence of stuck-at faults at the fan-out branches on the syn- by inserting one extra input w to realize the new function F = drome. Assume without loss of generality that the function is wxz + yz-. During normal operation the input w is fed with a positive in xi and that xi is a fan-out branch. Thus, the function constant logic 1, while for testing purposes it is used as a valid F can be expressed in the form input. The function F is now syndrome-testable since S(wx) # S(y). F = Axi + B Lemma 5: Every two-level irredundant combinational cirwhere both A and B do not depend on xi. The expression A has cuit can be made syndrome-testable by attaching control two or more terms. A stuck-at-0 at the input xi causes all the (extra) inputs to the AND gates. Proof: See Appendix A. PI's associated with xi to vanish. A stuck-at-I at input xi From Lemmas 3 and 4 it is evident that the candidates for causes all the PI's associated with xi to cover a greater number of minterms. By similar argument to that presented earlier we syndrome-untestability are the nonunate input lines. In order conclude that a fault at input xi changes the syndrome of the to keep track of the actual lines in which the function F is function. Q.E.D. syndrome-untestable we define the set Definition 4: Two paths that emanate from a common line T = {xi IF is syndrome-untestable in xi. and reconverge at some forward point are said to be reconClearly, verging paths [1]. Definition 5: The inversion parity [4] of a reconverging path T c {xi IF is nonunate in xi} is equal to the number of inversions modulo 2 in the path, i.e., Our goal is to reach a syndrome-testable realization of a the number of inversions modulo 2 between the point of digiven function while adding the minimum number of extra vergence and the point of reconvergence. In the case of two-level circuits, the points of divergence can inputs. We choose to add the control inputs in an uncompleonly be at the input branches, and the point of reconvergence mented form (complemented inputs are acceptable as well). at the output line.-The inverters can appear only at the inputs By Lemma 3 the modified function will always be syndrometestable in the control inputs. to the AND gates. Procedure 2 describes an algorithm for designing synLemma 4: There exist two-level irredundant circuits which drome-testable two-level combinational circuits. The synare not syndrome-testable.
446
IEEE TRANSACTIONS ON COMPUTERS, VOL.
drome-testable design is achieved by modifying the original irredundant sum of products. The modification requires an introduction of a nearly minimal number of control inputs. We use the following notation in describing the algorithm: set of control lines. C prime implicant number i. PIi PI set of prime implicants. j a number specifying how many times the function has been modified so far. F(1) the jth modified function. the set T which corresponds to function F(j). TU) FLAG an identifier describing whether the function should.be modified with an existing control variable or with a new one.
PI = IPI1, P12, Derive T(°)
X4X5,
, PIk
k
(Z denotes Boolean sum).
i=l
If T(J) stop, F(j) is syndrome-testable. If C = 0 go to Step 4. Step 3: For each cn C and Plj E PI derive function
4: Add
new
For each PIJ
E
input:
TOPI'
for
If I
=
u
{cb).
PI derive TO6iD for the function i#j
Let I T(O)
C
Phi
+
c, * PIj.
min{I TQ4)IO I
T()I then FLAG
=
=
0, otherwise FLAG
=
1.
Step 5: j~j+1 If FLAG = T(i)
=
0 then
T(a1); PI:
If FLAG
= 1
then
ca
Pl,
c, PIi, T(i) T(O$); PIz Go to Step 2. By Lemma 5. Procedure 1 is guaranteed to halt. Although, =
I
CIX1X2 + X1X3 + X2X3 + X4X5 + X4X5.
T(2)
=
{X3}
=
C1X1x2 + X1X3 + X2X3 + C1X4X5 + X4X5.
Third pass of Procedure 1 yields T(33) g
I (when the minimum is attained
C
=
Second pass of the algorithm gives
by several members choose one arbitrarily). If I T(a I = I T()| go to Step 4. Otherwise FLAG = 0, go to Step 5. Step
= X4X5.
F()
E Pli + cn * P1I.
min I I T(DI)
P15
=
isj n.j
X1X2 + X1X3 + X2X3 + X4X5 + x4x5.
First pass of Procedure 1 yields T(°) = IX1, X2, x3, X4, x5} FM = F TO1) X3, X4, X5}
-
=
at each iteration of the algorithm the optimal input insertion (or one of the optimal insertions in the case of multiple choices) is obtained, an overall optimal solution is not guaranteed. The reason for that is that local optimization does not necessarily lead to global optimization.
Solution: Let PI1 = x1I2, P12 = Y1x3, P13 = X2X3, P14 =
F(j) = E Pli
Let | Tag) I
Fig. 6. The syndrome-testable design for Example 4.
F=
Step 2:
=
C,
Example 4: Find the syndrome-testable design with nearly minimum number of control inputs for the function
Procedure 2 Step I -Initialization: j=O C='k FLAG = 0
C-29, NO. 6, JUNE 1980
F
= CiXX2 + C2X1X3 + X2X3 + C1X4X5 + X4X5.
The testable design is shown in Fig. 6. The only difficulty involving the design arises when n is large. Since~the test procedure requires the application of all 2 n input combinations, the design will be worthwhile for n < 20 (which is equivalent to about 1 s of testing with a 1 MHz machine). However, for n > 20, the problem can be overcome by designing the circuit with subcircuits, as shown in Fig. 7, such that every subcircuit has no more than 20 inputs. This improvement will cost in m = rq/201 extra outputs, where q is the number of inputs to the AND gates (the extra OR gates do not constitute a problem in present day technology). Each subcircuit must be designed to be syndrome-testable, and can be tested by no more than 220 inputs. Thus, the total test length will be approximately m220, which is equivalent to about m seconds of testing. Note that faults at the inputs of the OR gate generating the objective functions are not covered when the individual subcircuits are syndrome-tested. However, if we let the OR gates of the individual subcircuits have a tristate capability we can syndrome-test the OR gate which generates the objective function by directly exercising its inputs and thus test for the uncovered faults mentioned above.
447
SAVIR: DESIGN OF COMBINATIONAL CIRCUITS
Using Lemmas I and 2, we have S(F) = S(ACg) + S(BCg) + S(C) S(B + C) = S(BC) + S(C). Thus, the fault g/O is syndrome-untestable if and only if S(ACg) + S(BCg) = S(BC), or Q.E.D. S(ACg) = S(BCg). Corollary 1: Let g be any line in an irredundant combinaFig. 7. The proposed partition for large two-level circuits. The input lines may be shared between subcircuits, although not shown explicitly. tional circuit composed of AND, OR, NAND, NOR, and NOT gates. If there exists only one path from g to the circuit output, the function F is syndrome-testable with respect to faults in B. Syndrome- Testable Design of General Combinational g. Circuits Proof: Directly from Lemmas 6 and 7. EXCLUSIVE-OR and EQUIVALENCE gates are source of Lemma 6: Every fan-out-free inrredundant combinational circuit, composed of AND, OR, NAND, NOR, and NOT gates problems to syndrome testing because of their inherent nonunateness. The following lemma displays the conditions is syndrome-testable. Proof: In a fan-out-free circuit there is a unique path from necessary so that the faults on the inputs of an EXCLUSIVE-OR any line to the circuit output. Thus, if we label a given line by gate be syndrome-untestable. The corresponding conditions g, the output F will be either positive or negative in g, de- for an EQUIVALENCE gate can be obtained from Lemmas 1 pending on the inversion parity of the path originating at g and and 8. , x,) and Lemma 8: Let F = g @ h, where g = g(xI, x2, terminating at the output line. Assume without loss of generality that F is positive in g. We can, therefore, represent F h = h(xI, x2, , xn). The fault h/O is syndrome-untestable if and only if as F = Ag + b
S(gh) = S(gh)
where
(11)
and the fault h/I is syndrome-untestable if and only if
g = g(xil, x,2, , and both A and B do not depend on xi1, xi2, ,xii A stuck-at-0 fault on line g eliminates all the minterms associated with Ag, and does not create any new ones. Therefore, the circuit is syndrome-testable with respect to g/0. In order to prove that g/ 1 is syndrome-testable, we use a contrapositive approach. Assume that g/ 1 is syndrome-untestable. Thus, all the minterms covered by Ag are already covered by F. Therefore F can be represented by F=Ag + Ag + B = A + B which is independent of g, contradicting the previous asQ.E.D. sumption that F is positive in g. Lemma 7: Let g = g(xi , xiI,.. ,xin) be a line in a general combinational circuit. Let the equivalent sum of products of the function F with respect to line g be F = Ag + Bg + C. Then the fault g/0 is syndrome-untestable if and only if
S(ACg)
=
S(BCg)
(9)
and, the fault g/ 1 is syndrome-untestable if and only if S(ACg) = S(BCg). (10) Proof: We prove relation (9). The proof of (10) is similar. The fault g/O is syndrome-untestable if and only if S(F) = S(B + C).
S(gh) = S(kh).
(12) Proof: We prove (1 1). The proof of relation (1 2) is similar. The fault h/0 is syndrome-untestable if and only if S(g @ h) = S(g). Thus, S(gh) + S(gh) = S(g) Q.E.D. S(kh) = S(gh). Corollary 2: Let F = g CD h, where g = g(xi , xi2, ... Xiu), h = h(yi,, MI , , yi,) and {xi,, , Xi"} n tyi1, , yiuj = X. Then, faults on line h(h/O or h/I) are syndrome-untestable if and only if
S(g)
=
1/2.
(13)
Proof: Directly from Lemmas 1 and 8. It is evident from Corollary 2 that attaching an extra input to an EXCLUSIVE-OR gate will not fix the syndrome-untestable condition since relation (13) will hold for the new input. There are two basic approaches to fix the syndrome-untestable condition with respect to inputs of an EXCLUSIVE-OR gate. One way of handling the problem is by breaking the inherent symmetry of the gate. This can be done when the actual implementation of the gate is known. For example, in the case where the EXCLUSIVE-OR gate is implemented by NAND gates, the output can be made syndrome-testable with respect
IEEE TRANSACTIONS ON COMPUTERS, VOL. C-29, NO. 6, JUNE 1980
448 c
%F
F=cx x- -+X X
1
Fig. 8. A syndrome-testable modification of an EXCLUSIVE-OR gate. h ,-
g C
Fig. 9. Using an extra AND gate and an extra input to fix the syndromeuntestable condition in h(h/O or h/ I).
to faults at the inputs by adding a control input c as shown in Fig. 8. The second approach is to add a control input via an extra AND gate to the input lines of the EXCLUSIVE-OR gate as shown in Fig. 9. The problem is how to modify the design of a general combinational circuit so that it will be syndrome-testable. We try to do it by means of control input insertion and/or a small amount of extra logic. The control inputs connected to AND and NAND gates should be applied with a constant 1 under normal operation, while the control inputs attached to OR anid NOR gates should be applied with a constant 0 under normal operation. Any control input connected to AND or NAND gates cannot also be connected to OR or NOR gates. From the previous lemmas and corollaries it is clear that the candidate lines for syndrome-untestability are the fan-out lines, which have unequal inversion parities along its reconverging branches, the lines that feed them (directly or indirectly) and inputs and outputs of EXCLUSIVE-OR gates. The following procedure describes the modification algorithm.
Procedure 3 Step 1: Find the set of lines in which the function is syndrome-untestable by finding the equivalent sum of products with respect to the candidate lines for syndrome-untestability. Step 2: Use Procedure 2 with the following modifications: PI - Set of AND, NAND, OR, NOR gates. ij PIi + c. Pbj -The function obtained by attaching the control input c to gate number j. For the faults at the inputs of EXCLUSIVE-OR gates, use either the method of Fig. 8 or Fig. 9. As of today the author still lacks a proof that every multilevel combinational circuit can be modified to be syndrometestable by extra input insertions. However, our experience with small size circuits show that Procedure 3 does generate a syndrome-testable design. In order to make the syndrome-test procedure feasible it is necessary to partition the general combinational circuit to subcircuits, in such a way that the total testing time will be of reasonable size. In order to do that we use the previous concept that the time required for exhaustive testing of a subcircuit
which has no more than 20 inputs is acceptable. Fig. 10 shows the partitioning method. Fig. 10 shows an imbedded subcircuit Mk and its interconnection with previous subcircuits. Subcircuit Mk might in general receive inputs from two sources: primary inputs to the circuit and output from some other subcircuits (like Mi and Mj in Fig. 10). Since the inputs of the latter kind, namely those which are outputs of previous subcircuits, may in general depend on more than 20 inputs, an exhaustive exercise of subcircuit Mk will require more testing time than what we consider to be acceptable. Therefore, for those cases where the subcircuit Mk depends directly or indirectly on more than 20 inputs, the outputs of subcircuits like Mi and Mj in Fig. 10, may be designed to have a tristate capability. Thus, if we provide an extra I/O pin at these tristate outputs, we may have the capability of both observing the syndrome-test results when subcircuits like Mi and Mj are tested, and of directly exercising the input lines of subcircuit Mk when the outputs of Mi and Mj are held at the high impedance state. In this way, every subcircuit can be tested in no more than 220 inputs, which is equivalent to about 1 s of testing time. Therefore, a circuit which is partitioned to m subcircuits may be syndrome-tested in no more than m seconds. The pin-penalty paid for this partitioning is one pin for each tristate output. We have calculated the partitioning pin-penalty for uniform trees [2] of up to 1024 inputs and found it to be no more than 7 percent. Since the conditions of syndrome-untestability are very strict [i.e., relations (9) and (10)] it is believed that, in general, very few lines will meet them. Thus, only a few extra inputs will be required to achieve a syndrome-testable design. Table I displays a few MSI combinational logic, their number of pins and the number of extra pins needed to make them syndrometestable. As seen from Table I, the number of extra pins does not exceed 1 (or 5 percent) for these functions. This is not surprising because one extra input can invalidate the syndrome-untestable condition in various portions of the circuit. Because of the strictness of the syndrome-untestable condition, it is feasible to correct untestable conditions of several faults by means of only one additional input. Fig. 11 shows a syndrome-testable modification of SN74,181. The modification requires one extra input and two extra AND gates. Note that the extra AND gates could have been avoided if we assumed a certain realization of the EXCLUSIVE-OR gates (see Fig. 8).
449
SAVIR: DESIGN OF COMBINATIONAL CIRCUITS Extra output I
TABLE I THE NUMBER OF CONTROL INPUTS NECESSARY IN ORDER TO MAKE THE CIRCUITS SYNDROME-TESTABLE AS A FUNCTION OF NUMBER OF PINS FOR VARIOUS MSI COMBINATIONAL LOGIC
Function
Extra output
Fig. 10. The proposed partitioning for general combinational circuits. The outputs of Mi and Mj are designed to have a tristate capability.
-
Dual 4-line-to-I-line Data selectors/Mux SN74153 Data selectors/ Mux SN74150 Mux SN74151 Dual carry save adders SN74183 Look-ahead carry generators SN74182 Arithmetic logic units SN74181 Total
Pins
# Control inputs
16
1
24
1
16 14
1 1
16
0
24
1
110
5
Fig. 11. Syndrome-testable design of arithmetic logic units, SN741 81, requiring one extra input C and two extra gates (marked). The output syndromes are rounded to four decimal digits.
IV. SUMMARY AND CONCLUSIONS A new approach to the design of testable combinational circuits was presented in this paper. The design method is to modify given realizations by inserting extra I/O so that the final circuit will be syndrome-testable. A procedure that produces a nearly minimal number of extra input insertions was described. It was also shown how to partition very large combinational circuits to subcircuits such that the total testing time
will be of acceptable length. Although we restricted ourselves, in this paper, to single-output networks, the ideas easily generalize to multiple-output networks as well. It is well known that one of the most severe restrictions on IC manufacturers is the number of pins per chip. Although the testable design requires an increase in the number of pins, it is believed that the pin overhead is very low because of the strictness of the syndrome-untestable condition. In this paper we have mainly used extra input lines to
IEEE TRANSACTIONS ON COMPUTERS, VOL. c-29, NO. 6, JUNE 1980
450
achieve a syndrome-testable design. It may be possible, though, to use also extra logic in producing the testable design. This, in fact, may be very attractive since, in general, chip area is more available than I/O pins. We are currently investigating the possibility of trading off some of the extra I/O pins with extra logic. It is important to mention that the syndrometestable design can be superimposed on LSSD (level-sensitive scan design) [101. If this is done, the extra I/O pins required by the syndrome-testable design are actually implemented by extra SRL's (shift register latches) connected to the scan path. Thus, the I/O pin-penalty paid by the syndrome-testable design is traded off with extra logic.
S[(a1 + a5)3a9] + S[(a1 + a6)49] -
= alxi + a2Oi +
a3Xj + a4xj + a5xixj + a6XiX + a7X X +
8XiXj
+ a9
where ak do not depend on xi and xj for all k = 1, 2, , 9. Since xi E T(°), then- as a consequence of Lemma 4 we have
S[(a1 + a5)&39] + S[(al + a06)469]
S[(a3 + °5)a9] + -S[(a3 + 2
Since have
xi
i
T(°), then
+
as a consequence of Lemma 4 we
S[(a3 + a5s)0a9] + S[(a3 + aa7)9] $ S[(a4 + a6)a1a9] + S[(a4 + a8)2a9]
In order to correct the syndrome-untestable condition in xi we modify the function in the form (other ways are possible
also)
FO) =
c1laix
+
a2Xi
+
a3Xj + a4Xj + a5XiXj + a6XiXj + a7-iXj + a8xiyj + ag.
According to the assumption stated in the Lemma, FM') is syndrome-testable in xi and untestable in xj. This is translated to the following two conditions (by applying relation (8) to F(1)): Since xi $ TO1) we have
+ S[(a3 +
a7)09J
a5)(1al9]
IS[(a4 + a6)ala9]
(17)
2
by combining relations (14) and (16) we get that
(18) ala3a5°a mil 0 or a la4a°6a°l9 X 0 by combining relations (15) and (17) we get that (19) S[(a3 + a5)ajag] z S[(a4 + 6)aal9]. We have to show now that if the function is modified again as
(2)= c1c2x + +
ajx- + a3X1 +
a4+ a5XiXj a6Xix + a-7yiXj + a8XiXj + ag
it will be syndrome-testable in both xi and xj. In order to do this we show that the condition for syndrome-untestability in xi and xj does not hold for F(2). The condition for syndromeuntestability in xi for the function F(2) becomes
S[(al + a5)a3a9] + S[(a1 + a6)a4a9] -34 [S(a030509) + S(ajal4a 6a19)] S[(a2 + a7)39] + S[(a2 + a8)a4a9].
(20)
From relations (14) and (18) we easily see that (20) is false. The condition for syndrome-untestability in xj for the function F(2) becomes
S[(a3 + a5) (15)
(16)
S[(a4 + a6)a1a9] + S[(a4 + a8)29]
=
=
S[(a2 a7)a3a9] S[(a2 a8)i4a9]. (14) +
+
469)]
Since xi ET&) we have
+
Before proving Lemma 5, we first prove the following lemma. Lemma 9: Let T be the set of syndrome-untestable input lines. Let T(j) denote the set T of the jth modified function, j = 0, 1, 2,... , as defined previously in the paper. Let xi E T(°) and xi $ T(°), be two input lines to the two-level circuit. If, by attaching a control input cl to a (set of) PI('s), the condition of syndrome-untestability in xi is corrected and in xj is spoiled, namely xi $ T(1) and xj E T(O), then by attaching another control input c2 to the same (set of) PI('s) the spoiled condition in xj is corrected again, namely, xi, xj1 T(2). Proof: The function F can be expressed in the form
[S(al a5a9) + S(al
$£ S[(a2 + a7)&3a9] + S[(a2 + a8)a4a9].
APPENDIX A
F(°)
2
+ =
+
4
1
9] + S[(a3 +
a7)a2ag9]
S[(a3 + a5)a°1a9]
S[(a4 + a6)aia9] + S[(a4 + a8)a2a] 4
S[(a4 + a6)a°1a9].
(21)
From relations (17) and (19) we can easily see that (21) is also false. Thus, F(2) is syndrome-testable in both xi and xj. Q.E.D. Proofof Lemma 5: Let T be the set of syndrome-untestable input lines. From Lemma 9 we know that by adding at most 2 extra inputs we can reduce the cardinality of T by at least one. Thus, by adding at most 21 TI control inputs the function can be modified to be syndrome-testable. Q.E.D.
451
IEEE TRANSACTIONS ON COMPUTERS, VOL. c-29, NO. 6, JUNE 1980
ACKNOWLEDGMENT
The aLithor wishes to thank Prof. E. J. McCluskey, and the members of the Center for Reliable Computing at Stanford University for their helpful criticism. Thanks are also due to the members of the VLSI DA Group at the T.J. Watson Research Center, Yorktown Heights, NY. The referees comments are, also, greatly appreciated. REFERENCES [1] D. E. Armstrong, "On finding a nearly minimal set of fault detection tests for combinational logic nets," IEEE Trans. Electron. Comput., vol. EC-15, pp. 66-73, Feb. 1966. [2] J. P. Hayes, "On realization of Boolean functions requiring a minimal or near-minimal number of tests," IEEE Trans. Comput., vol. C-20, pp. 1506-1513, Dec. 1971. [3] --, "Transition count testing of combinational circuits," IEEE Trans. Comput., vol. C-25, pp. 613-620, June 1976. [4] I. Kohavi and Z. Kohavi, "Detection of multiple faults in combinational logic networks," IEEE Trans. Comput., vol. C-21, pp. 556-568, June 1972. [5] J. Losq, "Referenceless random testing," in Proc. 6th Ann. Symp. on Fault-Tolerant Comput., Pittsburgh, PA, pp. 108-113, June 21-23, 1976. [6] J. P. Roth, W. G. Bouricius, and P. R. Schneider, "Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits," IEEE Trans. Electron. Comput., vol. EC-16, pp. 567-580, Oct. 1967. [7] J. Savir, "Syndrome-testable design of combinational circuit," in Proc. 9th Ann. Int. Symp. on Fault-Tolerant Computing, June 1979, pp. 137-140.
[8] A. Tzidon, l. Berger, and M. Yoeli, "A practical approach to fault detection in combinational networks," IEEE Trans. Comput., vol. C-27, pp. 968-971, Oct. 1978. [9] K. P. Parker and E. J. McCluskey, "Probabilistic treatment of general combinational networks," IEEE Trans. Comput., vol. C-24, pp. 668-670, June 1975. [10] E. B. Eichelberger and T. W. Williams, "A logic design structure for LSI testability," in Proc. 14th Ann. Design Automation Conf., June 1977, pp.,462-468. Jacob Savir (M'78) was born in Bucharest, Romania, on December 13, 1946. He received the B.Sc. (cum laude) and M.Sc. degrees in electrical engineering from the Technion-Israel Institute of Technology, Haifa, Israel, in 1968 and 4973, respectively, the M.S. degree in statistics and Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 1977 and 1978, re-
spectively.
In the summer of 1967 he was a student trainee in ASEA, Sweden, working on high-power control systems. From 1968 to 1972 he served as an electronic engineer in the Israel Defence Forces. From 1972 to 1974 he worked as a Research Assistant at the Department of Electrical Engineering, Technion, Israel. From 1974 to 1975 he was a project engineer in the Israel Ministry of Defence. From 1975 to 1978 he worked, first as a Ph.D. student and later as an IBM Post-Doctoral Fellow, with Prof. E. J. McCluskey on intermittent fault test strategies and testable design of digital systems. He joined IBM in 1978 at the T. J. Watson Research Center, Yorktown Heights, NY, where he is currently a research staff member, investigating DA approaches to VLSI. His research interests include, testing and diagnosis of failures, testable design, fault simulation and reliability of digital systems. He authored several papers in the field of testing for logic faults and testable design of digital circuits. Dr. Savir is a member of Sigma Xi.
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis MIRON ABRAMOVICI, STUDENT MEMBER, IEEE, AND MELVIN A. BREUER, SENIOR MEMBER, IEEE
Abstract-In this paper we present a new approach to multiple fault diagnosis in combinational circuits based on an effect-cause analysis. The main vehicle of our approach is the deduction of internal line values in a circuit under test N*. The knowledge of these values allows us to Manuscript received August 6, 1979; revised January 21, 1980. This work was supported in part by the National Science Foundation under NSF Grant MCS78-26 153. M. Abramovici was with the Department of Eleclrical Engineering, University of Southern California, Los Angeles, CA 90007. He is now with Bell Laboratories, Naperville, IL 60540. M. A. Breuer is with the Departments of Electrical Engineering and Computer Science, University of Southern California, Los Angeles, CA 90007.
identify fault situations in N* (causes) which are compatible with the applied test and the obtained response (the effect). A fault situation specifies faulty as well as fault-free lines. Other applications include identifying the existence of nonstuck faults in N* and determination of faults not detected by a given test, including redundant faults. The latter application allows for the generation of tests for multiple faults without performing fault enumeration. Our technique does not require a fault dictionary, fault enumeration or even the knowledge of the expected values in the fault-free circuit. Index Terms-Combinational networks, deduction of internal values, effect-cause analysis, fault diagnosis, multiple redundant faults, multiple stuck-at faults.
0018-9340/80/0600-0451$00.75 (D 1980 IEEE
