Synthesis of high-density PtSi nanocrystals for memory application - QSL
APPLIED PHYSICS LETTERS 96, 172104 共2010兲
Synthesis of high-density PtSi nanocrystals for memory application Bei Li, Jingjian Ren, and Jianlin Liua兲 Department of Electrical Engineering, Quantum Structures Laboratory, University of California, Riverside, California 92521, USA
共Received 19 February 2010; accepted 2 April 2010; published online 27 April 2010兲 Vapor-solid-solid growth mechanism was employed to synthesize PtSi nanocrystals with density of 1.5⫻ 1012 cm−2 by introducing SiH4 onto Pt-catalyzed SiO2 / Si substrate. The nanocrystal density and average size were measured by scanning electron microscope and the nanocrystal chemical nature was determined by x-ray photoelectron spectroscope. Metal-oxide-semiconductor memory with PtSi nanocrystals was fabricated and characterized, showing very good memory performance. © 2010 American Institute of Physics. 关doi:10.1063/1.3421546兴 Nonvolatile memory with discrete-trap type storage nodes attracts much attention as a promising candidate for future low power electronics. Si nanocrystal 共NC兲 memory, introduced by Tiwari,1 has been investigated tremendously at both academia and industry due to its potential to exceed the performance limits of conventional flash memories. Although superior performance was demonstrated in Si NC memory, the device reliability remains an issue because of the defect-related charge storage in Si NCs. It is difficult to control the trap levels and densities to achieve a consistency in retention because trap formation and annihilation are sensitive to high-temperature processes such as source/drain dopant activation annealing. To solve this problem, many other NCs,2–5 and engineered gate structures6,7 were proposed. In this paper, we report the fabrication and characterization of high-density PtSi NC metal-oxide-semiconductor 共MOS兲 memories. PtSi NCs were formed by vapor-solidsolid 共VSS兲 growth mechanism, where Si precursor was introduced into Pt thin film-covered SiO2 / Si substrate at a subeutectic temperature. Traditionally, VSS was only used for nanowire 共NW兲 research,8 however the initial stage of the VSS growth to form silicide dots before the formation of NWs can be interesting for NC memory applications. Figure 1 shows energy band diagram of the memory device with PtSi NCs as floating gate. The work function of bulk PtSi, 4.9 eV,9 is used to draw the diagram. Therefore, the Fermi level of PtSi is within the band gap of Si and the conduction band offset between PtSi and SiO2 is 3.95 eV, 0.85 eV higher than that of Si NC memory, leading to longer retention time for electron storage. Other advantages of using PtSi NCs as floating gate for memory include easy and simple fabrication procedure, good thermal stability, high storage capability, and fast operation. These merits play important roles in future scaled memory technologies. The device fabrication starts with a p-Si 共100兲 substrate. Prediffusion cleaning was carried out and a thin thermal oxide of 3 nm was grown on the substrate at 850 ° C. A very thin layer of metal catalyst film was deposited by e-beam evaporator on the tunnel oxide at room temperature. Then the wafer was transferred into a low pressure chemical vapor deposition 共LPCVD兲 system for VSS Si growth. Typical
growth temperature used in our experiment is 600 ° C, which is much lower than the eutectic temperature of 979 ° C 共Ref. 10兲 between Pt and Si, indicating that the growth mode is VSS rather than vapor-liquid-solid. Si growth rate calibration experiments were carried out in order to control the growth time to avoid the growth of Si NWs and form high-density PtSi NCs for device fabrication. After PtSi NCs were formed, control oxide of 20 nm was deposited in another LPCVD furnace. Finally, Al was evaporated on the front and back of the wafer as contacts of MOS memories. X-ray photoelectron spectroscopy 共XPS兲 was used to study the chemical nature of the NCs. Figure 2 shows highresolution XPS data for Pt 4f of the sample with the NC average size of 5 nm and density of 1.5⫻ 1012 cm−2 关scanning electron microscopy 共SEM兲 image in the inset of Fig. 2兴. The binding energy of Pt 4f was obtained at 73.1 and 76.4 eV,11 indicating the nature of the NCs is PtSi, confirming the Si diffusion into Pt catalysts to form silicide NCs. A reference sample running the same temperature ramping process with this PtSi NCs sample except the introduction of the SiH4 exhibits Pt NC average size of about 4 nm and the same density as PtSi NCs. The larger size of PtSi NC further confirms the Si growth into Pt catalyst. Figure 3 shows the capacitance-voltage 共C-V兲 sweep characteristics of PtSi NC MOS memory sample with the dot density of 1.5⫻ 1012 cm−2. The scanning gate voltage changes from ⫾2 to ⫾10 V and the observed memory window increases from 0.26 to 8.2 V, indicating that the memory effect is due to the NC storage rather than defect/interface state charging. C-V sweep experiments of a reference sample without NCs between control and tunnel oxide were also
a兲
FIG. 1. Energy band diagram of floating gate memory with PtSi NCs. Deep quantum well of 3.95 eV exists between PtSi and SiO2.
Author to whom correspondence should be addressed. Electronic mail: [email protected].
0003-6951/2010/96共17兲/172104/3/$30.00
96, 172104-1
© 2010 American Institute of Physics
Author complimentary copy. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp
172104-2
Li, Ren, and Liu
Appl. Phys. Lett. 96, 172104 共2010兲
FIG. 2. XPS result of PtSi NCs on SiO2 / Si substrate and Pt 4f peak position confirms the chemical nature of NCs is PtSi. The inset is the SEM image of PtSi NCs on SiO2 / Si substrate. The density and average size of PtSi NCs is 1.5⫻ 1012 cm−2 and 5 nm, respectively.
carried out and no hysteresis behavior was found 共not shown here兲. This further confirms the fact that no defect/interface charging contributes to the memory effect, observed in PtSi NC memory. Figure 4 shows the dependence of flat band voltage 共VFB兲 shift and number of electrons and holes stored in each NC on the programming voltage. The writing of electrons was conducted by biasing a positive voltage, while for programming with holes 共erasing兲, a negative bias was applied on the gate. The charges in a single device is calculated from: Q = SiO2 / dSiO2⌬VFB, where Q is the charges stored in a MOS device, SiO2 is the dielectric constant of SiO2, dSiO2 is the thickness of control oxide, which is 20 nm in this work, and ⌬VFB is the VFB shift between fresh state and programmed/erased state. The charge number per NC is calculated from: Number/ dot= Q / Dq, where D is the NC density, which is 1.5⫻ 1012 cm−2 here and q is the electron charge. As the programming/erasing voltage increases, the threshold voltage shift and stored charges increase until saturated. Figure 5 shows retention characteristics of PtSi NC memory at programmed and erased states, respectively. The programming and erasing conditions are gate voltage of 10 V/5 s and ⫺10 V/5 s, respectively. After programming, transient capacitance at the same read voltage is recorded intermittently. After 105 s, the charges remained in the NCs at both programmed and erased states are about 70%, which is reasonable for a tunnel oxide of 3 nm. Endurance characteristics of PtSi NC memory is shown in Fig. 6. Two sets of
FIG. 3. C-V sweep of MOS memory device with PtSi NCs under different scanning gate voltage from ⫾2 to ⫾10 V.
FIG. 4. Plots of flatband voltage shift and corresponding electrons 共a兲 and holes 共b兲 per NC as a function of programming/erasing voltage.
FIG. 5. Retention characteristics of PtSi NC memory at programmed and erased states.
FIG. 6. Endurance performance of PtSi NC memory.
Author complimentary copy. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp
172104-3
Appl. Phys. Lett. 96, 172104 共2010兲
Li, Ren, and Liu
programming/erasing conditions, ⫾6 and ⫾10 V, were used to measure the cycling performance. It is found that up to 105 times of operation, the memory window, i.e., VFB difference between programmed and erased states, shows insignificant change for both sets of operation. In summary, VSS mechanism was used to synthesize PtSi NCs with high density and small size. MOS memory with PtSi NCs embedded in SiO2 was fabricated and characterized. Large memory window, long retention time, and good endurance performance were demonstrated in PtSi NC memory. The authors acknowledge the financial and program support of the Focus Center Research Program 共FCRP兲 on Function Engineered NanoArchitectonics 共FENA兲, the National Science Foundation 共Grant Nos. ECCS-0725630 and DMR-0807232兲, and the Defense Microelectronics Activity 共DMEA兲 under Agreement No. H94003-09-2-0901.
1
S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, Appl. Phys. Lett. 69, 1232 共1996兲. 2 M. Yang, T. P. Chen, J. I. Wong, C. Y. Ng, Y. Liu, L. Ding, S. Fung, A. D. Trigg, C. H. Tung, and C. M. Li, J. Appl. Phys. 101, 124313 共2007兲. 3 H. Liu, W. Winkenwerder, Y. Liu, D. Ferrer, D. Shahrjerdi, S. K. Stanley, J. G. Ekerdt, and S. K. Banerjee, IEEE Trans. Electron Devices 55, 3610 共2008兲. 4 M. She and T.-J. King, IEEE Trans. Electron Devices 50, 1934 共2003兲. 5 B. Li and J. L. Liu, J. Appl. Phys. 105, 084905 共2009兲. 6 Y. S. Lo, K. C. Liu, J. Y. Wu, C. H. Hou, and T. B. Wu, Appl. Phys. Lett. 93, 132907 共2008兲. 7 J. Jang, C. Choi, J. S. Lee, K. S. Min, J. Lee, D. M. Kim, and D. H. Kim, Semicond. Sci. Technol. 24, 115009 共2009兲. 8 A. I. Persson, M. W. Larsson, S. Stenstrom, B. J. Ohlsson, L. Samuelson, and L. R. Wallenberg, Nature Mater. 3, 677 共2004兲. 9 E. Bucher, S. Schulz, M. Ch. Lux-Steiner, P. Munz, U. Gubler, and F. Greuter, Appl. Phys. A: Mater. Sci. Process. 40, 71 共1986兲. 10 T. Baron, M. Gordon, F. Dhalluin, C. Ternon, P. Ferret, and P. Gentile, Appl. Phys. Lett. 89, 233111 共2006兲. 11 C. Y. Kang, C. H. Chao, S. C. Shiu, L. J. Chou, M. T. Chang, G. R. Lin, and C. F. Lin, J. Appl. Phys. 102, 073508 共2007兲.
Author complimentary copy. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp
Synthesis of high-density PtSi nanocrystals for memory application Bei Li, Jingjian Ren, and Jianlin Liua兲 Department of Electrical Engineering, Quantum Structures Laboratory, University of California, Riverside, California 92521, USA
共Received 19 February 2010; accepted 2 April 2010; published online 27 April 2010兲 Vapor-solid-solid growth mechanism was employed to synthesize PtSi nanocrystals with density of 1.5⫻ 1012 cm−2 by introducing SiH4 onto Pt-catalyzed SiO2 / Si substrate. The nanocrystal density and average size were measured by scanning electron microscope and the nanocrystal chemical nature was determined by x-ray photoelectron spectroscope. Metal-oxide-semiconductor memory with PtSi nanocrystals was fabricated and characterized, showing very good memory performance. © 2010 American Institute of Physics. 关doi:10.1063/1.3421546兴 Nonvolatile memory with discrete-trap type storage nodes attracts much attention as a promising candidate for future low power electronics. Si nanocrystal 共NC兲 memory, introduced by Tiwari,1 has been investigated tremendously at both academia and industry due to its potential to exceed the performance limits of conventional flash memories. Although superior performance was demonstrated in Si NC memory, the device reliability remains an issue because of the defect-related charge storage in Si NCs. It is difficult to control the trap levels and densities to achieve a consistency in retention because trap formation and annihilation are sensitive to high-temperature processes such as source/drain dopant activation annealing. To solve this problem, many other NCs,2–5 and engineered gate structures6,7 were proposed. In this paper, we report the fabrication and characterization of high-density PtSi NC metal-oxide-semiconductor 共MOS兲 memories. PtSi NCs were formed by vapor-solidsolid 共VSS兲 growth mechanism, where Si precursor was introduced into Pt thin film-covered SiO2 / Si substrate at a subeutectic temperature. Traditionally, VSS was only used for nanowire 共NW兲 research,8 however the initial stage of the VSS growth to form silicide dots before the formation of NWs can be interesting for NC memory applications. Figure 1 shows energy band diagram of the memory device with PtSi NCs as floating gate. The work function of bulk PtSi, 4.9 eV,9 is used to draw the diagram. Therefore, the Fermi level of PtSi is within the band gap of Si and the conduction band offset between PtSi and SiO2 is 3.95 eV, 0.85 eV higher than that of Si NC memory, leading to longer retention time for electron storage. Other advantages of using PtSi NCs as floating gate for memory include easy and simple fabrication procedure, good thermal stability, high storage capability, and fast operation. These merits play important roles in future scaled memory technologies. The device fabrication starts with a p-Si 共100兲 substrate. Prediffusion cleaning was carried out and a thin thermal oxide of 3 nm was grown on the substrate at 850 ° C. A very thin layer of metal catalyst film was deposited by e-beam evaporator on the tunnel oxide at room temperature. Then the wafer was transferred into a low pressure chemical vapor deposition 共LPCVD兲 system for VSS Si growth. Typical
growth temperature used in our experiment is 600 ° C, which is much lower than the eutectic temperature of 979 ° C 共Ref. 10兲 between Pt and Si, indicating that the growth mode is VSS rather than vapor-liquid-solid. Si growth rate calibration experiments were carried out in order to control the growth time to avoid the growth of Si NWs and form high-density PtSi NCs for device fabrication. After PtSi NCs were formed, control oxide of 20 nm was deposited in another LPCVD furnace. Finally, Al was evaporated on the front and back of the wafer as contacts of MOS memories. X-ray photoelectron spectroscopy 共XPS兲 was used to study the chemical nature of the NCs. Figure 2 shows highresolution XPS data for Pt 4f of the sample with the NC average size of 5 nm and density of 1.5⫻ 1012 cm−2 关scanning electron microscopy 共SEM兲 image in the inset of Fig. 2兴. The binding energy of Pt 4f was obtained at 73.1 and 76.4 eV,11 indicating the nature of the NCs is PtSi, confirming the Si diffusion into Pt catalysts to form silicide NCs. A reference sample running the same temperature ramping process with this PtSi NCs sample except the introduction of the SiH4 exhibits Pt NC average size of about 4 nm and the same density as PtSi NCs. The larger size of PtSi NC further confirms the Si growth into Pt catalyst. Figure 3 shows the capacitance-voltage 共C-V兲 sweep characteristics of PtSi NC MOS memory sample with the dot density of 1.5⫻ 1012 cm−2. The scanning gate voltage changes from ⫾2 to ⫾10 V and the observed memory window increases from 0.26 to 8.2 V, indicating that the memory effect is due to the NC storage rather than defect/interface state charging. C-V sweep experiments of a reference sample without NCs between control and tunnel oxide were also
a兲
FIG. 1. Energy band diagram of floating gate memory with PtSi NCs. Deep quantum well of 3.95 eV exists between PtSi and SiO2.
Author to whom correspondence should be addressed. Electronic mail: [email protected].
0003-6951/2010/96共17兲/172104/3/$30.00
96, 172104-1
© 2010 American Institute of Physics
Author complimentary copy. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp
172104-2
Li, Ren, and Liu
Appl. Phys. Lett. 96, 172104 共2010兲
FIG. 2. XPS result of PtSi NCs on SiO2 / Si substrate and Pt 4f peak position confirms the chemical nature of NCs is PtSi. The inset is the SEM image of PtSi NCs on SiO2 / Si substrate. The density and average size of PtSi NCs is 1.5⫻ 1012 cm−2 and 5 nm, respectively.
carried out and no hysteresis behavior was found 共not shown here兲. This further confirms the fact that no defect/interface charging contributes to the memory effect, observed in PtSi NC memory. Figure 4 shows the dependence of flat band voltage 共VFB兲 shift and number of electrons and holes stored in each NC on the programming voltage. The writing of electrons was conducted by biasing a positive voltage, while for programming with holes 共erasing兲, a negative bias was applied on the gate. The charges in a single device is calculated from: Q = SiO2 / dSiO2⌬VFB, where Q is the charges stored in a MOS device, SiO2 is the dielectric constant of SiO2, dSiO2 is the thickness of control oxide, which is 20 nm in this work, and ⌬VFB is the VFB shift between fresh state and programmed/erased state. The charge number per NC is calculated from: Number/ dot= Q / Dq, where D is the NC density, which is 1.5⫻ 1012 cm−2 here and q is the electron charge. As the programming/erasing voltage increases, the threshold voltage shift and stored charges increase until saturated. Figure 5 shows retention characteristics of PtSi NC memory at programmed and erased states, respectively. The programming and erasing conditions are gate voltage of 10 V/5 s and ⫺10 V/5 s, respectively. After programming, transient capacitance at the same read voltage is recorded intermittently. After 105 s, the charges remained in the NCs at both programmed and erased states are about 70%, which is reasonable for a tunnel oxide of 3 nm. Endurance characteristics of PtSi NC memory is shown in Fig. 6. Two sets of
FIG. 3. C-V sweep of MOS memory device with PtSi NCs under different scanning gate voltage from ⫾2 to ⫾10 V.
FIG. 4. Plots of flatband voltage shift and corresponding electrons 共a兲 and holes 共b兲 per NC as a function of programming/erasing voltage.
FIG. 5. Retention characteristics of PtSi NC memory at programmed and erased states.
FIG. 6. Endurance performance of PtSi NC memory.
Author complimentary copy. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp
172104-3
Appl. Phys. Lett. 96, 172104 共2010兲
Li, Ren, and Liu
programming/erasing conditions, ⫾6 and ⫾10 V, were used to measure the cycling performance. It is found that up to 105 times of operation, the memory window, i.e., VFB difference between programmed and erased states, shows insignificant change for both sets of operation. In summary, VSS mechanism was used to synthesize PtSi NCs with high density and small size. MOS memory with PtSi NCs embedded in SiO2 was fabricated and characterized. Large memory window, long retention time, and good endurance performance were demonstrated in PtSi NC memory. The authors acknowledge the financial and program support of the Focus Center Research Program 共FCRP兲 on Function Engineered NanoArchitectonics 共FENA兲, the National Science Foundation 共Grant Nos. ECCS-0725630 and DMR-0807232兲, and the Defense Microelectronics Activity 共DMEA兲 under Agreement No. H94003-09-2-0901.
1
S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, Appl. Phys. Lett. 69, 1232 共1996兲. 2 M. Yang, T. P. Chen, J. I. Wong, C. Y. Ng, Y. Liu, L. Ding, S. Fung, A. D. Trigg, C. H. Tung, and C. M. Li, J. Appl. Phys. 101, 124313 共2007兲. 3 H. Liu, W. Winkenwerder, Y. Liu, D. Ferrer, D. Shahrjerdi, S. K. Stanley, J. G. Ekerdt, and S. K. Banerjee, IEEE Trans. Electron Devices 55, 3610 共2008兲. 4 M. She and T.-J. King, IEEE Trans. Electron Devices 50, 1934 共2003兲. 5 B. Li and J. L. Liu, J. Appl. Phys. 105, 084905 共2009兲. 6 Y. S. Lo, K. C. Liu, J. Y. Wu, C. H. Hou, and T. B. Wu, Appl. Phys. Lett. 93, 132907 共2008兲. 7 J. Jang, C. Choi, J. S. Lee, K. S. Min, J. Lee, D. M. Kim, and D. H. Kim, Semicond. Sci. Technol. 24, 115009 共2009兲. 8 A. I. Persson, M. W. Larsson, S. Stenstrom, B. J. Ohlsson, L. Samuelson, and L. R. Wallenberg, Nature Mater. 3, 677 共2004兲. 9 E. Bucher, S. Schulz, M. Ch. Lux-Steiner, P. Munz, U. Gubler, and F. Greuter, Appl. Phys. A: Mater. Sci. Process. 40, 71 共1986兲. 10 T. Baron, M. Gordon, F. Dhalluin, C. Ternon, P. Ferret, and P. Gentile, Appl. Phys. Lett. 89, 233111 共2006兲. 11 C. Y. Kang, C. H. Chao, S. C. Shiu, L. J. Chou, M. T. Chang, G. R. Lin, and C. F. Lin, J. Appl. Phys. 102, 073508 共2007兲.
Author complimentary copy. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp
