Synthesis of self-testable controllers - European ... - Semantic Scholar
Synthesis of Self-Testable Controllers Sybille Hellebrand, Hans-Joachim Wunderlic h Institute of Computer Structures
University of Siegen Germany Abstract The paper presents a synthesis approach for pipelinelike controller structures. These structures allow 10 implement a built-in sdf-tesl in h\:O sessions without allY a tra test registers. Hence the additional dewy imposed by the test circuitry is reduced, thefault coverage is increased, and in many cases the overall area is minimal. too. The sd/-Iutilbfe structure for a given finite state machine specification is derived/rom all appropriate reaiiwtion of the
machine. A theorem is prowm rhot such realiz.ations can be constructed by lManJ of partition pairs. An algorithm to dettmnine optimal realitJltions is developed and benchmark aperimenrs are presented /0 demonstrate the applicability althe prtsel1ted approach.
Usually the BlST is implemented by so-called multifunctional test registers like the well-known BILBO which are able to work as a system register, to generate test patterns and to compress the test responses by signature analysis. Such test registers have been developed for mndom, detenninislic, pseudo-exhaustive and weighted random patterns (19, 10, 4,25, 171. However, the circuit structure obtained from conventional synthesis procedures as shown in figure I is not a priori compatible with BIST, as during self-testing the register should genernte patterns and evaluate test responses concurrently. inpulS
combinational circuit
c 1 Introduction The application of microelectronic systems in safetycritical areas, e.g. in avio nics or medicine, demands extremely high quality standards, and thus refined testing techniques. The problem of implementing efficient tests providing a complete or very high fault coverage is panicularly difficult fo r controllers because of their irregular structure and the reduced observabi lity and controllability of internal states. Conventio na lly the circuit structure for a controller is synthesized from a finite state machine specification performing state coding and logic minimization (5 ,6, 12.23,221. But even if advanced synthesis techniques are used to generate sequentially irredundant controllers, the necessary tes t sequences might be prohibitivel y long lll, 2. 21 ). To overcome this problem either additional test functions have to be considered during synthesis or testabi lity feat ures such as built-in self-test (BIST) have to be added to the synthesized structure (7. 9, I J. With respect to safety-critical applications BIST is of special importance. since the c apabilities for test pallern generatio n and test response evaluation on chip can also be used for periodic maintenance tests. 11Iis work was supported by EP 7107 ARCHIMEDES.
1066-1409194 $3.00 e 1994 IEEE
Figure I : Result of convenlional synlhesis procedure. This kind of parallel self-test, where the signatures are used as test patterns, is only feasible in a few cases, but in general the required properties of the test patterns cannot be guaranteed 11 8, 13]. In most cases the signatures arc not exhaustive, (weighted) random or even detenninistic, and an additional test register is usually required (figure 2). inputs
....
£
.~ ii
outputs comb!~ national , --~1" '" circuit r E ~ C ~.~
l--===---=:=J ::;- ~
Figure 2: Typical controller structure with BIST. The test register T is o nl y incorporated for test purposes, and it must be transparent during system mode. This is a common self-test architecture, for variations see also II J. But all these configurations have some serious drawbacks:
1) 2)
The number of flipflops must be doubled. In system mode the test register T must be transparen t o r bypassed. This prolongs the critical path and may s low down the system speed of the controller. 3) There are faults on the feedback lines from R to the inputs of C which are not detected, as these lines arc not completely exercised duri ng self-test . This holds, even if the connections between R and T are tested in an additional ste p. The last two disadvantages can be circumvented by doubling no t only the Oipflops but also the combinational circuitry (see fi gure 3). If both copies of R are initialized to the same values, the struc ture of fig ure 3 implements the same machine as the structure of fig ure I. No ne of the registers needs to be transpare nt d uring syste m mode a nd thc rc is no additio nal delay imposed this way. The self-test can be perfonned in two sessions by alternatively usi ng o ne of the registers for pattern generation and the other for s ignature analysis. Moreover, as there is no transparency mode o r bypassing a complete faul t coverage is possible. outputs
,, ~
....
overhead for integrati ng a self-test is reduced. In addition to that this architecture is also compati ble with synthesis techniq ues which use autonomous transitions of the test register as system transitions (14]. It is important to note that this structure is different from structures provided by decomposition techniques where the resulting submachines contai n internal feedback loops [16, 3, 15). In contrast to known approaches tryi ng to reduce dependencies between state variables by appropriate state coding the presented work add resses the problem already at the fi nite state machi ne level (24. 8), Based on algebraic structure theory fo r a given fi nite state machi ne specification a realizatio n is constructed which suppons a self-testable s truc ture as shown in figure 4. S tate coding and logic mi nimization are then applied to this realization. The res t of the paper is organized as follo ws: In section 2 the notion of fi nite stale machines supporting selftestable structures is introduced and the proble m of synthes izing optimal se1f·testable controllers is staled as an optimiUl tion problem at the fi nite state machi ne level. Subsequently in section 3 the existence of s uitable finite state mochine realizations is related to the existence of partition pairs wi th addi tional propenies, and a n algorithm is developed which solves the pro blem staled in section 2. Section 4 provides experimental results. Conclusions and comments on future work arc given in section 5 .
combinational circuit
c
- -r:;-
~
~ ..e!1"
,,.
combinational ~ circuit
c
~ 'Q
."
l! ~ e!1
••
;;
-
~
.~
I IS!~I
- I
I is minimal for all pairs satisfyi ng (i).
To solve this problem a search procedure has bcen developed which makes use of the lattice structure of the set
583
JY' new is a successor of a node JY' old, if and only if JY' new JY' old u {mkJ with k > max(i I 'fI'\.i e Jr old}, i. e.: V :/'(J't) E {(JY',. JY'2) E V x V I JY'2 JY', u {mk} with k > max{i I mi e Jrl J } The root of the search tree is 0. For each node Jr in the search tree '" :: (U JY')I and M('I\) are calculated. where ",I denotes the transilille closure of a relation "'. By (16] (M(",,). "") is an Mm-pair. If (fI., M('I\» is also a partition pair and M(1'.) n 1'. c e, then (M('I\),1\.> prOllides a solution for DSTR and the costs
=
,=
,=
r log2 IS1M(fI.)ll+rlog2IS/fl.lland
=
I
ISIM(""~
IS/""I
-II
are calculated. If M(1\.) n fI. a. e. then m(",,) is calculated. By theorem 2 (m(fI,). "") is a symmetric partition pair with m(",,) n '" c M(",,) n "'. IfmC"") n '" c e, then (m(",,), "") is a solution for OSTR and the costs are calculated for this pair. Finally the solution with minimal costs is selected to realize the specification. This basic search procedure is of lIery high complexity, since the number of nodes in the searchtree is I V I = 0(2 IS12 ). But the follow ing lemma provides a criterion 10 prune the search tree. Le mmH I; LeI M = (S, I, 0, 6, A) be 1I finite ::;tllle machine, and let (V, E) be the search Iree defined above. For a node (JY'I, JY'Z) e E let"" I := (U Jr' 1)t and '1\02 ;= (U JY'2)t. Ifm('I\oI) n '1'101 a. e, then m('I'Io2) n ""2 a. e. 11roof: By definition of the searchtree "" Ie"" Z' and by [16] this implies m(n I) C m(""2), and thus 01("" I) n '1\0 1 cm(""Z)n'l'lo2. 0 As a consequence of lemma I, once a node JY' in the searchtrec with M(",,) n "" a. e is reached, all of its successor~ have this property and the subtree rooted at Jr' can be diS{;arded. As demonstrated by the experimental results described in the next section this leads to an enonnous reduction of the computational effort.
4 Experimenta l results The algorithm for problem OSTR described in section 3 has been implemented as a depth first procedure and has been applied to most of the fully specified finite state machine benchmarks distributed for the International Workshop on Logic Synthesis '93 [ZO]. The results are shown in table I. Column 2 contains the number of states in the original finite state machine, and columns 3 and 4 contai n the number of stales in the factors S I and S2 of the best realization found. Columns 5 and 6 list the required number of flipflops for a conventional BIST and for a BIST with the optimized structure by the presented synthesis approach. Except for tbk, for all examples the exact solu-
.... ....
tion for OSTR could be calculated. For tbk the solution obtained within a given timelimit is shown. Name
lSI
I Sli
I S21
eonll. BIST
pipeline structure
bbara bblas dkl4 dkl5 dkl6 dkl7 dk27 dk512
to
7 6 7 4 24 8 6 14 4 20 4 2
7 6 7 4 24 8 7
8 6 6 4 10 6 6 8 4 10 6 4 10
6 6 6 4 10 6 6 8 4 10 3 2 8
'"'
,I
shiftre to.
tbk*) Table I:
6 7 4 27 8 7 15 4 20 8 4 32
"
4 20 2 2
" "
Results of deplhfirst search procedure for OSTR. *) timeout
The practical impact of lemma I on the computational effort is demonstrated in table 2. Column 3 lisls the Ollerall number IV I of nodes in the searchtree for OSTR in cuntra.sl to Ihe: number uf nudes that had 10 be investigated when pruning the searchtree according to lemma I (column 4). Name
151
IVI
# nodes inllestigated
bbara bbtas dkl4 dkl5 dk l6 dk l7 dk27 dk512 mo
10
243
815
6
2" 2 '0
J75
"shiftreg ,,. Table 2:
7 4 27
24 206 2
8
220
7
2" 2 56
15 4 20 8 4
27
2 162 28 27
"7 337041 63 203 343853 13 323
4' 47
Impact of lemma I on the computational effon.
The results in table I show that for eight examples a non trivial solution for OSTR, i.e. a solution with IS I I < IS lor IS21 < IS I, could be found. For shiftreg and tav even the lower bound IS I I IS21 = IS I is achieved. In these eight examples the combined networks C I and C2 need to implement less state transitions Ihan
the original network C. Dependi ng on the im plementation sty le significant hardware savings are obtained compared to si mp ly doubling C as shown in fi gure 3, whereby th e advantages wi th respect to fau lt coverage a nd speed are retained. In four examples even the number of flipflops required for a self~lestable p ipelined controller is smaller than the numbe r required for a conventional BIST.
8
K.-T. Cheng. V. D. Ag rawa l: State Assignment for Testable DeSign, Inl. 10urnal of Computer Aided VLS I Design, Vol. 3., March 1991 9 S. T. Chakradar_ S. Kanji laJ, V. D. Agrawal: Finite State Machine Synthesis wi th Fault Tolerant Test Function, Proc. 29th Automation Conf., Anaheim. Ca .. 1992, pp. 562-567 l OW. Daehll. J. Mucha: Hardware Test Pattern Generation for Built-In Test, Proe. [EEE Int. Test Conf.. Philadelphia, [98 1, pp. 100· 113 I I S. Devadas. K. Keu tzer: A Unified Approach to the Syn· thesis of Fully Testable Sequential Machines, rEEE Trans. on CA D, Vol. 10, No. I. Jan. 1991. pp. 39·50 12 S. Devadas el al.: MUSTANG: Slate Assignment of Finite State Machines Targeting Mu litlevel Logic Implemerllations, IEEE Trans. on CAD. Vol. 7. No. 12. Dec. 1988. pp. 1290-1300 13 B. Esehermann. H.-1. Wunderlich: Parallel Sel f-Test il nd thc Synthesis of Control Units. Proc. 2nd European Test Conf.. Munich, 1991 14 B. Eschermann, H.-J. Wunderlich: Optimized Synthesis Techniques for Testable Sequential Circuits, IEEE Trans. on CAD. Vol. II. No.3. March 1992. pp. 30 1-3 12 15 Manin Geiger, Thomas MOller·WipperfOrth: FSM Decomposition Revisi ted: Algebraic Structure Theory Applied to MCNC Benchmark FSMs. Proc. 28th Design AutOmation Conf., San Francisco. 1991. pp. 182-185 16 1. Hartmanis. R. E. Stearns: Algebraic Structure Theory of Sequential Machines, Prentice Hall. Englewood Cliffs, 1966 17 S. Hellebrand, H.-1. Wunderlich, O. Haberl: Generating Pseudo·E~haust i ve Vectors for External Testing. Proc. Inl. Test Conf., Washingtion. D. C .• 1990, pp. 670·679 18 K. Kim. D. Ha, J . Tront: On Using Signature Registers as Pseudorandom Pattern Generators in Built-in Self Testing. IEEE Trans. on CAD. Vol. 7, 1988. pp. 919-928 19 B. Koenemann. 1. Muc ha, G. Zwiehoff: Built-in Logic Block Observalion Techniques, Proc. IEEE Int. Test Conf., Cherry Hill. N. J., 1979, pp. 37·4 1 20 K. McElvain: IWLS'93 Benchmark Set: Version 4.0, distributed as pan of the JWLS'93 benchmark distribution 21 I. Pomeran7., S. M. Reddy: Design and Synthesis fo r Testabi lity of SynchronoUS Sequential Circuits Based on Strong-Connectivity, Proc. IEEE 23rd Int. Symp. on Fault-Tolerant Computing. Toulouse. 1993. pp. 492-50 1 22 G. Saucier, M. C. De Pau let. P. Sicard: ASYL: A RuleBased System for Controller Synthesis. IEEE Trans. on CAD, Vol. CAD-6. No.6. Nov. 1987, pp. 1088-1097 23 T. Vil la, A. Sangiovanni·Vincen telli: NOVA: State Assignment of Finite State Machines fo r Optimal TwoLevel Logic Implementations, Proc. 26th Design Automation Conf., Las Vegas. 1989. pp. 327-332 24 P. Weiner, E. J. Smith: Optimization of Reduc«l Depende ncies for Synchronous Sequential Machi nes, IEEE Trans. 011 Elect ronic Comp .. Vol. EC·16. No.6. Dec. 1967, pp. 835-847 25 H.-J. Wunde rl ich: Self Test Using Uncquiprobable Random Patterns, Proc. IEEE 17th 1m. Symp. on FaultTolerant Computing. Pittsburgh. 1987. pp. 258-263
5 Conclusions and fu ture work A method has been presented for implementi ng self~ testable contro llers wi thout doubli ng the system reg isters duri ng test mode. The proposed pipeli ne- like structure does not contain any d irec t feedbac k loops and is partitioned by two system registe rs. During self-test these reg isters perform test pattern generat ion and signature analys is a lternatively. This arc hitecture reduces the delay imposed by bypassing test rcg isters and increases the fault coverage. A synthesis procedure has been presented for generati ng min imal pipelined rea lizations from state transition diagrams. In most cases th is o ptim ized solution is superior to simply doubli ng the reg isters and combinational networks, and in many cases the number o f flip fl ops is less tha n il is requ ired for a conventional SIST. This indicates that not o nly hig her speed and fau lt coverage is obtainable this way, but also area can be saved. Fultire work w ill concentrate on modifyi ng the state trans ition d iagram to obtain func tionally cquivalent mac hines whose self-testable rea li7.ations lead to better solulions of problem OSTR.
6 References
2
3
4
5
6
7
V. D. Agrawal, C. R. Kime. K. K. Saluja: A Tu toriat on Bui lt- In Self-Test. Part I: Principles, IEEE Design and Test ofComp.• Vol. 10, No. I, March 1993, pp. 73·82 P. Ashar. S. Devadas: Irredu ndant Interacting Sequential Machines Via Optimal Logic Synthesi~, IEEE Tran$. on CAD, Vol. 10, No.3, March 1991, pp. 311-325 P. Ashar. S. Oevadas, A. R. Newton: A Unified Approach to the DecompOSition and Re-decomposition of Sequen. tial Machines, Proe. 27th Design Automation Conf.. 1990. pp. 601-606 Z. IJarzilai. D. Coppersmith. A. L. Rosenberg: E~haustive Generation of Bit Patterns with Applications to VLS I Self-Testing, IEEE Trans. on Comp., Vol. c-32. No.2, Feb. 1983. pp. 190 - 194 R. K. Brayton. G. D. Hac htel, C. T. McMullen: Logic Minimi7.ation Algorithms for VLS I Synthesis. Kluwe r Academic Publishers. Boston 1984 R. K. Brayton et al.: MIS: A Multiple-Level Logic Optimization Systcm, IEEE Trans. on CAD. Vol. CAD-6, No. 6. 1987, pp. 1062-1081 V. D. Agrawal. K.-T. Cheng: Finite State Machine Synthesis with Embedded Tesl Function. Journal of Electronic Testi ng Theory and Applications, Vol. I. No.3, Oct. 1990. pp. 221-228
'"
University of Siegen Germany Abstract The paper presents a synthesis approach for pipelinelike controller structures. These structures allow 10 implement a built-in sdf-tesl in h\:O sessions without allY a tra test registers. Hence the additional dewy imposed by the test circuitry is reduced, thefault coverage is increased, and in many cases the overall area is minimal. too. The sd/-Iutilbfe structure for a given finite state machine specification is derived/rom all appropriate reaiiwtion of the
machine. A theorem is prowm rhot such realiz.ations can be constructed by lManJ of partition pairs. An algorithm to dettmnine optimal realitJltions is developed and benchmark aperimenrs are presented /0 demonstrate the applicability althe prtsel1ted approach.
Usually the BlST is implemented by so-called multifunctional test registers like the well-known BILBO which are able to work as a system register, to generate test patterns and to compress the test responses by signature analysis. Such test registers have been developed for mndom, detenninislic, pseudo-exhaustive and weighted random patterns (19, 10, 4,25, 171. However, the circuit structure obtained from conventional synthesis procedures as shown in figure I is not a priori compatible with BIST, as during self-testing the register should genernte patterns and evaluate test responses concurrently. inpulS
combinational circuit
c 1 Introduction The application of microelectronic systems in safetycritical areas, e.g. in avio nics or medicine, demands extremely high quality standards, and thus refined testing techniques. The problem of implementing efficient tests providing a complete or very high fault coverage is panicularly difficult fo r controllers because of their irregular structure and the reduced observabi lity and controllability of internal states. Conventio na lly the circuit structure for a controller is synthesized from a finite state machine specification performing state coding and logic minimization (5 ,6, 12.23,221. But even if advanced synthesis techniques are used to generate sequentially irredundant controllers, the necessary tes t sequences might be prohibitivel y long lll, 2. 21 ). To overcome this problem either additional test functions have to be considered during synthesis or testabi lity feat ures such as built-in self-test (BIST) have to be added to the synthesized structure (7. 9, I J. With respect to safety-critical applications BIST is of special importance. since the c apabilities for test pallern generatio n and test response evaluation on chip can also be used for periodic maintenance tests. 11Iis work was supported by EP 7107 ARCHIMEDES.
1066-1409194 $3.00 e 1994 IEEE
Figure I : Result of convenlional synlhesis procedure. This kind of parallel self-test, where the signatures are used as test patterns, is only feasible in a few cases, but in general the required properties of the test patterns cannot be guaranteed 11 8, 13]. In most cases the signatures arc not exhaustive, (weighted) random or even detenninistic, and an additional test register is usually required (figure 2). inputs
....
£
.~ ii
outputs comb!~ national , --~1" '" circuit r E ~ C ~.~
l--===---=:=J ::;- ~
Figure 2: Typical controller structure with BIST. The test register T is o nl y incorporated for test purposes, and it must be transparent during system mode. This is a common self-test architecture, for variations see also II J. But all these configurations have some serious drawbacks:
1) 2)
The number of flipflops must be doubled. In system mode the test register T must be transparen t o r bypassed. This prolongs the critical path and may s low down the system speed of the controller. 3) There are faults on the feedback lines from R to the inputs of C which are not detected, as these lines arc not completely exercised duri ng self-test . This holds, even if the connections between R and T are tested in an additional ste p. The last two disadvantages can be circumvented by doubling no t only the Oipflops but also the combinational circuitry (see fi gure 3). If both copies of R are initialized to the same values, the struc ture of fig ure 3 implements the same machine as the structure of fig ure I. No ne of the registers needs to be transpare nt d uring syste m mode a nd thc rc is no additio nal delay imposed this way. The self-test can be perfonned in two sessions by alternatively usi ng o ne of the registers for pattern generation and the other for s ignature analysis. Moreover, as there is no transparency mode o r bypassing a complete faul t coverage is possible. outputs
,, ~
....
overhead for integrati ng a self-test is reduced. In addition to that this architecture is also compati ble with synthesis techniq ues which use autonomous transitions of the test register as system transitions (14]. It is important to note that this structure is different from structures provided by decomposition techniques where the resulting submachines contai n internal feedback loops [16, 3, 15). In contrast to known approaches tryi ng to reduce dependencies between state variables by appropriate state coding the presented work add resses the problem already at the fi nite state machi ne level (24. 8), Based on algebraic structure theory fo r a given fi nite state machi ne specification a realizatio n is constructed which suppons a self-testable s truc ture as shown in figure 4. S tate coding and logic mi nimization are then applied to this realization. The res t of the paper is organized as follo ws: In section 2 the notion of fi nite stale machines supporting selftestable structures is introduced and the proble m of synthes izing optimal se1f·testable controllers is staled as an optimiUl tion problem at the fi nite state machi ne level. Subsequently in section 3 the existence of s uitable finite state mochine realizations is related to the existence of partition pairs wi th addi tional propenies, and a n algorithm is developed which solves the pro blem staled in section 2. Section 4 provides experimental results. Conclusions and comments on future work arc given in section 5 .
combinational circuit
c
- -r:;-
~
~ ..e!1"
,,.
combinational ~ circuit
c
~ 'Q
."
l! ~ e!1
••
;;
-
~
.~
I IS!~I
- I
I is minimal for all pairs satisfyi ng (i).
To solve this problem a search procedure has bcen developed which makes use of the lattice structure of the set
583
JY' new is a successor of a node JY' old, if and only if JY' new JY' old u {mkJ with k > max(i I 'fI'\.i e Jr old}, i. e.: V :/'(J't) E {(JY',. JY'2) E V x V I JY'2 JY', u {mk} with k > max{i I mi e Jrl J } The root of the search tree is 0. For each node Jr in the search tree '" :: (U JY')I and M('I\) are calculated. where ",I denotes the transilille closure of a relation "'. By (16] (M(",,). "") is an Mm-pair. If (fI., M('I\» is also a partition pair and M(1'.) n 1'. c e, then (M('I\),1\.> prOllides a solution for DSTR and the costs
=
,=
,=
r log2 IS1M(fI.)ll+rlog2IS/fl.lland
=
I
ISIM(""~
IS/""I
-II
are calculated. If M(1\.) n fI. a. e. then m(",,) is calculated. By theorem 2 (m(fI,). "") is a symmetric partition pair with m(",,) n '" c M(",,) n "'. IfmC"") n '" c e, then (m(",,), "") is a solution for OSTR and the costs are calculated for this pair. Finally the solution with minimal costs is selected to realize the specification. This basic search procedure is of lIery high complexity, since the number of nodes in the searchtree is I V I = 0(2 IS12 ). But the follow ing lemma provides a criterion 10 prune the search tree. Le mmH I; LeI M = (S, I, 0, 6, A) be 1I finite ::;tllle machine, and let (V, E) be the search Iree defined above. For a node (JY'I, JY'Z) e E let"" I := (U Jr' 1)t and '1\02 ;= (U JY'2)t. Ifm('I\oI) n '1'101 a. e, then m('I'Io2) n ""2 a. e. 11roof: By definition of the searchtree "" Ie"" Z' and by [16] this implies m(n I) C m(""2), and thus 01("" I) n '1\0 1 cm(""Z)n'l'lo2. 0 As a consequence of lemma I, once a node JY' in the searchtrec with M(",,) n "" a. e is reached, all of its successor~ have this property and the subtree rooted at Jr' can be diS{;arded. As demonstrated by the experimental results described in the next section this leads to an enonnous reduction of the computational effort.
4 Experimenta l results The algorithm for problem OSTR described in section 3 has been implemented as a depth first procedure and has been applied to most of the fully specified finite state machine benchmarks distributed for the International Workshop on Logic Synthesis '93 [ZO]. The results are shown in table I. Column 2 contains the number of states in the original finite state machine, and columns 3 and 4 contai n the number of stales in the factors S I and S2 of the best realization found. Columns 5 and 6 list the required number of flipflops for a conventional BIST and for a BIST with the optimized structure by the presented synthesis approach. Except for tbk, for all examples the exact solu-
.... ....
tion for OSTR could be calculated. For tbk the solution obtained within a given timelimit is shown. Name
lSI
I Sli
I S21
eonll. BIST
pipeline structure
bbara bblas dkl4 dkl5 dkl6 dkl7 dk27 dk512
to
7 6 7 4 24 8 6 14 4 20 4 2
7 6 7 4 24 8 7
8 6 6 4 10 6 6 8 4 10 6 4 10
6 6 6 4 10 6 6 8 4 10 3 2 8
'"'
,I
shiftre to.
tbk*) Table I:
6 7 4 27 8 7 15 4 20 8 4 32
"
4 20 2 2
" "
Results of deplhfirst search procedure for OSTR. *) timeout
The practical impact of lemma I on the computational effort is demonstrated in table 2. Column 3 lisls the Ollerall number IV I of nodes in the searchtree for OSTR in cuntra.sl to Ihe: number uf nudes that had 10 be investigated when pruning the searchtree according to lemma I (column 4). Name
151
IVI
# nodes inllestigated
bbara bbtas dkl4 dkl5 dk l6 dk l7 dk27 dk512 mo
10
243
815
6
2" 2 '0
J75
"shiftreg ,,. Table 2:
7 4 27
24 206 2
8
220
7
2" 2 56
15 4 20 8 4
27
2 162 28 27
"7 337041 63 203 343853 13 323
4' 47
Impact of lemma I on the computational effon.
The results in table I show that for eight examples a non trivial solution for OSTR, i.e. a solution with IS I I < IS lor IS21 < IS I, could be found. For shiftreg and tav even the lower bound IS I I IS21 = IS I is achieved. In these eight examples the combined networks C I and C2 need to implement less state transitions Ihan
the original network C. Dependi ng on the im plementation sty le significant hardware savings are obtained compared to si mp ly doubling C as shown in fi gure 3, whereby th e advantages wi th respect to fau lt coverage a nd speed are retained. In four examples even the number of flipflops required for a self~lestable p ipelined controller is smaller than the numbe r required for a conventional BIST.
8
K.-T. Cheng. V. D. Ag rawa l: State Assignment for Testable DeSign, Inl. 10urnal of Computer Aided VLS I Design, Vol. 3., March 1991 9 S. T. Chakradar_ S. Kanji laJ, V. D. Agrawal: Finite State Machine Synthesis wi th Fault Tolerant Test Function, Proc. 29th Automation Conf., Anaheim. Ca .. 1992, pp. 562-567 l OW. Daehll. J. Mucha: Hardware Test Pattern Generation for Built-In Test, Proe. [EEE Int. Test Conf.. Philadelphia, [98 1, pp. 100· 113 I I S. Devadas. K. Keu tzer: A Unified Approach to the Syn· thesis of Fully Testable Sequential Machines, rEEE Trans. on CA D, Vol. 10, No. I. Jan. 1991. pp. 39·50 12 S. Devadas el al.: MUSTANG: Slate Assignment of Finite State Machines Targeting Mu litlevel Logic Implemerllations, IEEE Trans. on CAD. Vol. 7. No. 12. Dec. 1988. pp. 1290-1300 13 B. Esehermann. H.-1. Wunderlich: Parallel Sel f-Test il nd thc Synthesis of Control Units. Proc. 2nd European Test Conf.. Munich, 1991 14 B. Eschermann, H.-J. Wunderlich: Optimized Synthesis Techniques for Testable Sequential Circuits, IEEE Trans. on CAD. Vol. II. No.3. March 1992. pp. 30 1-3 12 15 Manin Geiger, Thomas MOller·WipperfOrth: FSM Decomposition Revisi ted: Algebraic Structure Theory Applied to MCNC Benchmark FSMs. Proc. 28th Design AutOmation Conf., San Francisco. 1991. pp. 182-185 16 1. Hartmanis. R. E. Stearns: Algebraic Structure Theory of Sequential Machines, Prentice Hall. Englewood Cliffs, 1966 17 S. Hellebrand, H.-1. Wunderlich, O. Haberl: Generating Pseudo·E~haust i ve Vectors for External Testing. Proc. Inl. Test Conf., Washingtion. D. C .• 1990, pp. 670·679 18 K. Kim. D. Ha, J . Tront: On Using Signature Registers as Pseudorandom Pattern Generators in Built-in Self Testing. IEEE Trans. on CAD. Vol. 7, 1988. pp. 919-928 19 B. Koenemann. 1. Muc ha, G. Zwiehoff: Built-in Logic Block Observalion Techniques, Proc. IEEE Int. Test Conf., Cherry Hill. N. J., 1979, pp. 37·4 1 20 K. McElvain: IWLS'93 Benchmark Set: Version 4.0, distributed as pan of the JWLS'93 benchmark distribution 21 I. Pomeran7., S. M. Reddy: Design and Synthesis fo r Testabi lity of SynchronoUS Sequential Circuits Based on Strong-Connectivity, Proc. IEEE 23rd Int. Symp. on Fault-Tolerant Computing. Toulouse. 1993. pp. 492-50 1 22 G. Saucier, M. C. De Pau let. P. Sicard: ASYL: A RuleBased System for Controller Synthesis. IEEE Trans. on CAD, Vol. CAD-6. No.6. Nov. 1987, pp. 1088-1097 23 T. Vil la, A. Sangiovanni·Vincen telli: NOVA: State Assignment of Finite State Machines fo r Optimal TwoLevel Logic Implementations, Proc. 26th Design Automation Conf., Las Vegas. 1989. pp. 327-332 24 P. Weiner, E. J. Smith: Optimization of Reduc«l Depende ncies for Synchronous Sequential Machi nes, IEEE Trans. 011 Elect ronic Comp .. Vol. EC·16. No.6. Dec. 1967, pp. 835-847 25 H.-J. Wunde rl ich: Self Test Using Uncquiprobable Random Patterns, Proc. IEEE 17th 1m. Symp. on FaultTolerant Computing. Pittsburgh. 1987. pp. 258-263
5 Conclusions and fu ture work A method has been presented for implementi ng self~ testable contro llers wi thout doubli ng the system reg isters duri ng test mode. The proposed pipeli ne- like structure does not contain any d irec t feedbac k loops and is partitioned by two system registe rs. During self-test these reg isters perform test pattern generat ion and signature analys is a lternatively. This arc hitecture reduces the delay imposed by bypassing test rcg isters and increases the fault coverage. A synthesis procedure has been presented for generati ng min imal pipelined rea lizations from state transition diagrams. In most cases th is o ptim ized solution is superior to simply doubli ng the reg isters and combinational networks, and in many cases the number o f flip fl ops is less tha n il is requ ired for a conventional SIST. This indicates that not o nly hig her speed and fau lt coverage is obtainable this way, but also area can be saved. Fultire work w ill concentrate on modifyi ng the state trans ition d iagram to obtain func tionally cquivalent mac hines whose self-testable rea li7.ations lead to better solulions of problem OSTR.
6 References
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V. D. Agrawal, C. R. Kime. K. K. Saluja: A Tu toriat on Bui lt- In Self-Test. Part I: Principles, IEEE Design and Test ofComp.• Vol. 10, No. I, March 1993, pp. 73·82 P. Ashar. S. Devadas: Irredu ndant Interacting Sequential Machines Via Optimal Logic Synthesi~, IEEE Tran$. on CAD, Vol. 10, No.3, March 1991, pp. 311-325 P. Ashar. S. Oevadas, A. R. Newton: A Unified Approach to the DecompOSition and Re-decomposition of Sequen. tial Machines, Proe. 27th Design Automation Conf.. 1990. pp. 601-606 Z. IJarzilai. D. Coppersmith. A. L. Rosenberg: E~haustive Generation of Bit Patterns with Applications to VLS I Self-Testing, IEEE Trans. on Comp., Vol. c-32. No.2, Feb. 1983. pp. 190 - 194 R. K. Brayton. G. D. Hac htel, C. T. McMullen: Logic Minimi7.ation Algorithms for VLS I Synthesis. Kluwe r Academic Publishers. Boston 1984 R. K. Brayton et al.: MIS: A Multiple-Level Logic Optimization Systcm, IEEE Trans. on CAD. Vol. CAD-6, No. 6. 1987, pp. 1062-1081 V. D. Agrawal. K.-T. Cheng: Finite State Machine Synthesis with Embedded Tesl Function. Journal of Electronic Testi ng Theory and Applications, Vol. I. No.3, Oct. 1990. pp. 221-228
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