Tessent MemoryBIST Shell Student Workbook

Tessent MemoryBIST Shell Student Workbook

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Table of Contents Module 1 Introduction to Tessent MemoryBIST Tessent MemoryBIST Solution Components .............................................................................6 Tessent MemoryBIST Implementation .......................................................................................7 Memory BIST Hardware: Architecture ......................................................................................8 Comparator Placement ................................................................................................................9 Tessent MemoryBIST Operating Protocol ...............................................................................11 Scannable Memory Interface (Optional) ...................................................................................14 Supported Memory Types .........................................................................................................15 Key Features..............................................................................................................................16 Test Algorithms.........................................................................................................................18 Built-In Standard Algorithms....................................................................................................19 Base Capabilities: Fault Coverage Summary ...........................................................................20 Memory Library File for Each Memory (.tcd_mem_lib)..........................................................22 Memory Library Example .........................................................................................................23 Hierarchical Bottom Up Flow Advantages ..............................................................................25 Tessent MemoryBIST Block Flow ...........................................................................................26 Example: Design Architecture and Clocking ............................................................................27 Generic Block Architecture.......................................................................................................29 Tessent MemoryBIST Flow ......................................................................................................30 Prerequisites ..............................................................................................................................31 Tessent Shell Database (TSDB) ................................................................................................32 Typical TSDB Structure (First 2 Levels) ..................................................................................33 Getting Help With Tessent Tools..............................................................................................34 SupportNet ................................................................................................................................37 Lab1...........................................................................................................................................38

Module 2 Standard Memory BIST Flow Tessent MemoryBIST Flow ......................................................................................................42 Tool Invocation .........................................................................................................................44 Load Design: Contexts and Modes ...........................................................................................45 Load Design: System Modes ....................................................................................................46 Load Design: Reading Design Netlists .....................................................................................47 Load Design: Reading Libraries ...............................................................................................48 Load Design: Elaborating the Design .......................................................................................49 Load Design: Optional Data (after set_current_design) ...........................................................50 Tessent MBIST Shell

Table of Contents Useful Design Data Reporting Commands ...............................................................................51 Load Design (Review) ..............................................................................................................52 Specify Requirements: Design Level ........................................................................................53 Specify Requirements: Memory BIST Options ........................................................................55 Specify Requirements: Memory Instance Options ...................................................................56 add_inputs_constraints ..............................................................................................................57 set_attribute_value ....................................................................................................................58 Specify Requirements: Clocks ..................................................................................................59 Specify Requirements: DRCs ...................................................................................................60 Specify Requirements: Review .................................................................................................61 Tessent MemoryBIST Flow ......................................................................................................62 Create the DftSpecification .......................................................................................................63 DFTSpecification: report_config_data......................................................................................64 DFTSpecification: display_specification ..................................................................................65 DFTSpecification: Insert Test Logic .........................................................................................66 blockA: Design .........................................................................................................................67 blockA: DFTSpecification ........................................................................................................68 blockA: Post DFTSpecification Processing Block Diagram ....................................................69 blockB: Design ..........................................................................................................................70 blockB: DFTSpecification ........................................................................................................71 blockB: Block Diagram.............................................................................................................72 DFTSpecification: Review ........................................................................................................73 Tessent MemoryBIST Flow ......................................................................................................74 Extract ICL ................................................................................................................................75 Patterns Specification ................................................................................................................76 Extract ICL and PatternsSpecification Review .........................................................................77 Tessent MemoryBIST Flow ......................................................................................................78 Simulation Validation ...............................................................................................................79 Basic Flow Review ...................................................................................................................80 Lab 2..........................................................................................................................................81

Module 3 Clocks and Clock DRCs Typical Clocking Network for Memories .................................................................................84 Defining Clocks ........................................................................................................................85 Defining and Managing Clocks – Option 1 ..............................................................................86 Defining and Managing Clocks – Option 2 ..............................................................................87 Tessent MBIST Shell

Table of Contents Add / Define Clocks ..................................................................................................................88 Clock Gating Cells ....................................................................................................................89 Clock Muxes .............................................................................................................................91 Defining and Managing Clocks – Option 3 ..............................................................................92 Clock Divider / ICL .................................................................................................................93 Clock Divider / PDL .................................................................................................................94 DFT Specification .....................................................................................................................95 Core: Design .............................................................................................................................96 Core: DFTSpecification ............................................................................................................97 Core: Block Diagram ................................................................................................................98 PatternsSpecification .................................................................................................................99 Pre-DFT Clock Rules (DFT_C rules) .....................................................................................102 Pre-DFT Clock Rule DFT_C1 ................................................................................................103 Pre-DFT Clock Rule DFT_C2 ................................................................................................104 Pre-DFT Clock Rule DFT_C3 ................................................................................................105 Pre-DFT Clock Rule DFT_C4 ................................................................................................106 Pre-DFT Clock Rule DFT_C5 ................................................................................................107 Lab 3........................................................................................................................................108

Module 4 DefaultsSpecification and DFTSpecification Specifications ..........................................................................................................................112 DefaultsSpecification ..............................................................................................................113 DefaultsSpecification Wrappers..............................................................................................114 DefaultsSpecification: PatternsSpecification ..........................................................................115 DefaultsSpecification: DftSpecification..................................................................................116 DefaultsSpecification: IjtagNetwork .......................................................................................117 DefaultsSpecification: BoundaryScan ....................................................................................119 DefaultsSpecification: MemoryBISR .....................................................................................122 DefaultsSpecification: MemoryBIST......................................................................................123 DefaultsSpecification: DiagnosisOptions ...............................................................................124 DefaultsSpecification: RepairOptions .....................................................................................125 DefaultsSpecification: AlgorithmResourceOptions ................................................................126 DefaultsSpecification: MemoryInterfaceOptions ...................................................................127 DefaultsSpecifications Editing Options ..................................................................................128 Specification Editing Options ................................................................................................129 Editing in the GUI ...................................................................................................................130 Tessent MBIST Shell

Table of Contents Editing Using Command Line ................................................................................................133 Command Line / Dofile ..........................................................................................................135 Lab 4........................................................................................................................................137

Module 5 Memory BIST Hierarchical Top Level Flow Top Level Tessent MemoryBIST Flow ..................................................................................140 Top Level Flow Differences ...................................................................................................141 TAP Features ...........................................................................................................................142 BoundaryScan Requirements ..................................................................................................143 TAP/Boundary Scan Interface ................................................................................................144 Boundary Scan Cells ...............................................................................................................145 BoundaryScan Insertion ..........................................................................................................146 BoundaryScan: Additional Attributes .....................................................................................147 Pin Order File ..........................................................................................................................150 BoundaryScan in DftSpecification .........................................................................................153 Bonding Configurations ..........................................................................................................154 BoundaryScan in PatternsSpecification ..................................................................................156 Top Level Tessent MemoryBIST Flow ..................................................................................157 Load Design ............................................................................................................................158 Specify Requirements .............................................................................................................159 Top Level Tessent MemoryBIST Flow ..................................................................................160 DftSpecification ......................................................................................................................161 Top: Design .............................................................................................................................162 Top: DFTSpecification............................................................................................................163 Top: Block Diagram ................................................................................................................164 Top Level Tessent MemoryBIST Flow ..................................................................................165 Extract ICL ..............................................................................................................................166 Top Level Tessent MemoryBIST Flow ..................................................................................167 PatternsSpecification ...............................................................................................................168 PatternsSpecification ...............................................................................................................169 PatternsSpecification ...............................................................................................................170 PatternsSpecification ...............................................................................................................171 Tessent MemoryBIST Flow ....................................................................................................172 Simulation Validation .............................................................................................................173 Manufacturing Patterns ...........................................................................................................174 Manufacturing Patterns ...........................................................................................................175 Tessent MBIST Shell

Table of Contents Lab 5: The Memory BIST Hierarchical Top Flow ................................................................178

Module 6 Memory BIST Debug Patterns Debug and Characterization Patterns ......................................................................................182 PatternsSpecification: Default .................................................................................................183 Creating Debug Patterns: Design loading ...............................................................................184 Creating Debug Patterns: Design loading ...............................................................................185 Testing a Single Test Step .......................................................................................................186 Testing a Single Memory ........................................................................................................188 Review: Define Alternate Algorithms in DftSpecification .....................................................190 Apply Alternate Algorithms ....................................................................................................191 Testing Single Memory and Alternate Algorithm ..................................................................192 Test Time Multiplier ...............................................................................................................193 Diagnosis and Debug ..............................................................................................................194 Identify Failing Memory .........................................................................................................195 Memory-Level Only: comparator_location : per_interface ....................................................196 Identify Failing Memory: comparator_location : shared_in_controller ...........................................................................197 Identify Failing Memory : comparator_location : shared_in_controller ...........................................................................198 Memory Address Level / Offline Bit Mapping .......................................................................199 Lab 6: Debug Patterns ............................................................................................................201

Module 7 Built-in Self Repair Tessent MemoryBIST Solution Components: BIRA and BISR .............................................205 Self-Repair Architecture .........................................................................................................206 Self-Repair Benefits ................................................................................................................210 Repair Analysis .......................................................................................................................211 Repair Analysis — Row OR Column ....................................................................................212 Repair Analysis — Row AND Column .................................................................................213 RedundancyAnalysis Wrapper ................................................................................................214 Repair Analysis — Row AND Column ..................................................................................215 Fully Autonomous Self-Repair ...............................................................................................216 Summary: Manufacturing Repair Flow ..................................................................................218 Support for Power Domains ....................................................................................................221 Implementing Repair with Tessent MemoryBIST ..................................................................222 Tessent MBIST Shell

Table of Contents Load Design / Options ............................................................................................................223 DftSpecification: RepairOptions .............................................................................................224 DftSpecification: MemoryBISR..............................................................................................225 Design Rule Checks ................................................................................................................226 Implementing Repair with Tessent MemoryBIST ..................................................................227 DftSpecification ......................................................................................................................228 Implementing Repair with Tessent MemoryBIST ..................................................................229 PatternsSpecification ...............................................................................................................230 Implementing Repair with Tessent MemoryBIST ..................................................................231 Testbench Simulations ............................................................................................................232 FuseBox ..................................................................................................................................233 Fuse Box .tcd_fbox .................................................................................................................234 Additional BISR Options ........................................................................................................235 Lab 6: Repair Flow.................................................................................................................236

Tessent MBIST Shell