test methodologies for very deep sub-micron ... - Semantic Scholar
IDDT Test Methodologies for Very Deep Sub-micron CMOS Circuits Ali Chehab*, Rafic Makki**, Michael Spica*** and David Wu***, * Multilink Technology Corporation **University of North Carolina at Charlotte ***Intel Corp.
Abstract In this paper, we investigate three iDDT-based test methodologies, Double Threshold iDDT, Delta iDDT, and Delayed iDDT, and we compare their effectiveness in the detection of defects in very deep sub-micron random logic circuits. The target defects are resistive opens and resistive bridges. We present preliminary simulation results of 49 defects to study the defect sensitivity of each of the three test methods. This paper reports our preliminary results on these three test methods using a relatively small transistor-level sample circuit, and is not intended to imply any feasibility in a production environment. The test methods presented herein are the subject of a current invention disclosure.
opens- on the performance of such circuits and on the behavior of iDDT. The impact of a resistive defect on the performance of a CMOS circuit depends on the circuit topology, the location of the defect and the resistance value of such a defect. In some cases, the defect may have no impact on the logic value but it can impact the iDDT pulse.
II. Simulation Set-up The initial transistor-level simulations were based on a 0.35-micron process with a power supply voltage of 3.3V. Thirty transitions are induced, and hence, 30 iDDT pulses are produced. Figure 1 shows the initial circuit under study and Figure 2 shows the results of the good circuit simulation.
I. Introduction The International Technology Roadmap for Semiconductors (ITRS), in its 1999 edition, addressed several issues that will challenge chip designers, test engineers and the testing community as a whole. Among these issues are: the tremendous increase in circuit size, the rapid increase in clock frequencies, the dominance of the interconnect delay, the transmissionline behavior of interconnects, the reduced level of the power supply voltage, the increase in leakage currents, the increase in power consumption, and the increased sensitivity of a design to the process defects. These factors give rise to new types of defects that, on one hand, can no longer be represented using the existing fault models, and on the other hand, cannot be easily detected using traditional voltage testing techniques as well as the single threshold IDDQ test. Consequently, more effective techniques are being investigated and proposed by researchers. Among these techniques is Delta-IDDQ testing [1]-[5] and Dynamic Current Testing [6]-[13]. In this paper, we characterize iDDT as related to the switching of CMOS random logic circuits in very deep sub-micron technologies. We analyze the effects of resistive defects -bridges and
II.1 Double Threshold iDDT This method is based on the fact that a good circuit will always have a lower bound and an upper bound of peak iDDT values in response to selected input vector pairs. Figure 2 shows the lower and upper bounds for the circuit under study. If a circuit draws a peak iDDT value that is either lower than the lower bound or higher than the upper bound (within a given tolerance), a defect may be inferred. As an example, we can see that the peak values of the iDDT spikes range from 220 to 350 µA. A resistive open of 100 KΩ at the gate of the PMOS transistor P7 in Figure-2, will produce, in response to vectors “1000” and “0000” two iDDT spikes with values of 327 and 147 µA respectively. The second spike is 33% lower than the lower bound (220) and hence such a defect can be detected using the double threshold iDDT method. The threshold for detection using this method was set to 20% (faulty iDDT is 20% lower/higher than good iDDT). The test vector set is such that no test vector outside the set will produce iDDT outside the minimum and maximum bounds in Figure 2.
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
Figure 1. Transistor-Level Schematic of the Good Circuit
400
350
300
Peak IDDT (mA)
250
200
150
100
50
0 1
2
3
4
5
6
7
8
9
10
11 12 13
14 15 16 17
18 19 20 21
22 23 24 25
26 27 28 29
Vector #
Figure 2. Peak iDDT for All Possible Input Vectors (Transitions)
II.2 Delta iDDT We define two input vectors to be complimentary if they cause opposite transitions of the circuit’s output and along the same path, like the vectors “1000” and “0000”. This method is based on the fact that, in response to 2 complimentary vectors, a good circuit will have a difference in the corresponding iDDT spikes limited between a lower bound and an upper bound. This difference is bound in our example between 0 and 112 µA. The reason for proposing this methodology is that a defective circuit can draw iDDT spikes with peak magnitudes that are within the good circuit limits or slightly outside the limits as defined in the double iDDT threshold method. However, the difference of such peak magnitudes can amplify in some cases the abnormal behavior of iDDT and produce a value outside the good circuit limits as defined in Delta iDDT. Consider the same example used in the double iDDT
30
Figure 3: Logic Extract from an Intel Chip Based on a 0.18-micron Process
threshold method. The difference in the peak magnitudes of iDDT in response to the vectors “1000” and “0000” are 4 µA for the good circuit and 180 µA for the defective one, and hence, such a defect can be detected.
II.3 Delayed iDDT This method is based on the fact that a good circuit is normally expected to switch, and hence to draw an iDDT pulse within a specific time interval. Outside such an interval, no pulse should be observed. This time interval is dictated by the circuit's speed and by the frequency of operation. If a particular defect causes a delay in the circuit's response, this delay will be reflected in a delayed iDDT pulse. If the delay is unacceptable, it can shift the iDDT pulse outside the window of observation. If we shift the window of
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
observation past the time where a good circuit is supposed to switch, then this pulse, if it has an appreciable magnitude, will be detected.
III. Results The correlation between resistive opens/bridges and each of the 3 methodologies were investigated by the manual insertion of resistors in the circuit shown in Figure 1. The resistors were inserted at different locations in the circuit and with different resistor values, simulating the effects of opens and shorts as well as benign faults that do not affect the circuit operation. Table 1 summarizes the results. The simulations were performed at a speed of 166 MHz where each vector takes 1 ns of setup time (fall/rise), and a 5 ns steady value. The results of the simulations show that for the circuit under analysis, the Double
Resistive Opens
Number of defects Considered 40
Resistive Shorts
9
iDDT Threshold method performs very well and is capable of detecting all the defects that were introduced at the transistor terminals and that are causing a delay of 0.5 ns or more. On the other hand, the Delta iDDT method is very sensitive to the location of the defects. It can detect a defect producing a delay as small as 0.1 ns in one location but can only detect a defect causing a logic failure in another location. This method behaves poorly when the defect causes the iDDT spikes, resulting from complimentary vectors, to change in the same direction; i.e. for both of them to increase or both of them to decrease. However, if the two spikes change in opposite directions, the Delta iDDT method performs very well. As for the Delayed iDDT method, it can detect resistive opens that cause a measurable delay value.
Number (Percentage) of defects Detected by: Double Threshold Delta Delayed iDDT iDDT iDDT 38 (95%)
29 (72.5%)
24 (60%)
Number of Defects Not Detected By any Method 1 (2.5%)
8 (89%)
1 (11%)
9 (100%)
0 (0%)
Table 1. Results Summary
IV. Effect of the Process Technology As the process technology scales down, the transistor transconductance k’ increases, while the power supply voltage, and the threshold voltage decrease, and the overall effect is a reduction in the peak magnitude of iDDT per device. This fact has been verified by simulating an inverter with various process technologies and the results are shown in Table-2 below. On the other hand, and within the same process technology, the shape and the peak magnitude of iDDT are also affected by the process variations, and they behave differently at different corners of the process. This was verified by the following experiment based on a 0.18-micron process technology for the circuit of Figure 3. The circuit was simulated over three different process skews, one for a typical skew, another one for the slowest skew, and the last one for the fastest skew. An input vector "00001" was inserted through the scan chain. The first 4 zeros will initialize all 4 inputs as well as the output to zero, and the last shifted “1” will cause a transition on the output from “0” to “1”, at which time the iDDT response is captured. The vector insertion process through the scan chain is done via two non-overlapping scan clocks. The iDDT responses
for the three different skews of the good circuit are shown in Figure 4. These results show a change in the peak magnitude of iDDT and a change in the spread over time of the iDDT response among the different process skews. This change is consistent with the nature of the process where, for instance, the slow skew exhibits a lower iDDT peak value and a longer time to settle when compared with the other skews. This result is interesting for it can be used for speed binning.
V. Scalability Issues We have conducted preliminary experiments to investigate the effects of switching a large number of gates on the sensitivities of the three iDDT test methods. At this stage we can say that the threshold iDDT test method looses ground relatively quickly with the number of simultaneously switching gates (as compared to the other two methods) unless test vectors are selected in a way so as to switch a minimum number of gates simultaneously. The scalability issues are intimately related to two important parameters:
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
1.
2.
Selection of test vectors: Test vectors are selected to switch a minimum number of gates simultaneously. The sensitivity of the sensor which is employed: This has to do with the maximum circuit size that a sensor can support, given the total circuit leakages and switching profile.
sensor. In general, more capable sensors result in less partitions. So the issue is not simply whether the iDDT test method works for a large circuit, but also how many sections would we need to partition the circuit into (for iDDT measurement purposes) and is the overhead acceptable. Last, the iDDT test methods should not be considered a stand-alone test, but rather supporting other methods to increase coverage .
A large circuit would have to be partitioned into sections such that each section can be supported by a
Process (micron) 1.2 0.5 0.35 0.18
First iDDT Peak (µA) 113 81 58 41
Second iDDT Peak (µA) 144 112 86 58
Table-2: Effect of the Process Technology on iDDT
Slow -0.16
Fast -0.45
Typical -0.36 Figure 4. iDDT Response Over 3 Process Skews
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
VI. Conclusions Three iDDT test methods were studied; Double Threshold iDDT, Delta iDDT, and Delayed iDDT. It was shown that the threshold and Delta iDDT are effective in detecting both short and open defects if iDDT pulses are effectively controlled with select input test vectors that switch a minimum amount of gates. It was also shown that the delayed iDDT test is primarily effective in detecting opens. The key issues are the ability to control the iDDT pulse peak values and the effectiveness of the sensor that is deployed.
[11]
[12]
[13]
J. Plusquellic, D. Chiarulli, S. Levitan. “Characterization of CMOS Defects using Transient Signal Analysis,” DFT, pp. 93-101, November 1998. R. Makki, S. Su, T. Nagle, “Transient Power Supply Current Testing of Digital CMOS Circuits,” ITC, 1995, pp. 892–901. S. Su, R. Makki, T. Nagle, “Transient Power Supply Current Monitoring – A New Test Method for CMOS VLSI Circuits,” Journal of Electronic Testing: Theory and Applications, pp. 23-43, February 1995.
Acknowledgements This work was funded by the National Science Foundation under award CCR 9912412 and by a grant from Intel Corporation.
References [1]
[2]
[3] [4] [5]
[6]
[7]
[8]
[9]
[10]
C. Thibeault, “An Histogram Based Procedure for Current Testing of Active Defects,” Int. Test Conf., 1999, pp. 714-723. A. C. Miller, “IDDQ Testing in Deep Submicron Integrated Circuits,” Int. Test Conf., 1999, pp. 724-729. K. Baker, “SIA Roadmaps: Sunset Boulevard for IDDQ”, Int. Test Conf., 1999, p. 1121. D. Bhavsar, “ITC99 Panels,” IEEE Design & Test, vol. 16, no. 4, Oct.-Dec. 1999, pp. 96-99. C. F. Hawkins, J.M. Soden, “Deep Submicron CMOS Current IC Testing: Is There a Future?” IEEE Design & Test, vol. 16, no. 4, Oct.-Dec. 1999, pp. 14-15. B. Kruseman, P. Janssen, V. Zieren, “Transient Current Testing of 0.25 µm CMOS Devices,” Int. Test Conf., 1999, pp. 47-56. M. Sachdev, P. Janssen, V. Zieren, “Defect Detection with Transient Current Testing and its Potential for Deep Sub-micron CMOS ICs,” Int. Test Conf., 1998, pp.204-213. W. Jiang, B. Vinnakota, “Statistical Threshold Formulation For Dynamic Idd Test,” Int. Test Conf., 1999, pp. 57-66. B. Vinnakota, “Monitoring Power Dissipation for Fault Detection,” 14th VTS, pp. 483-488, 1996. A. Germida, Z. Yan, J. Plusquellic, F. Muradali, “Defect Detection using Power Supply Transient Signal Analysis,” Int. Test Conf., 1999, pp. 67-76.
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
Abstract In this paper, we investigate three iDDT-based test methodologies, Double Threshold iDDT, Delta iDDT, and Delayed iDDT, and we compare their effectiveness in the detection of defects in very deep sub-micron random logic circuits. The target defects are resistive opens and resistive bridges. We present preliminary simulation results of 49 defects to study the defect sensitivity of each of the three test methods. This paper reports our preliminary results on these three test methods using a relatively small transistor-level sample circuit, and is not intended to imply any feasibility in a production environment. The test methods presented herein are the subject of a current invention disclosure.
opens- on the performance of such circuits and on the behavior of iDDT. The impact of a resistive defect on the performance of a CMOS circuit depends on the circuit topology, the location of the defect and the resistance value of such a defect. In some cases, the defect may have no impact on the logic value but it can impact the iDDT pulse.
II. Simulation Set-up The initial transistor-level simulations were based on a 0.35-micron process with a power supply voltage of 3.3V. Thirty transitions are induced, and hence, 30 iDDT pulses are produced. Figure 1 shows the initial circuit under study and Figure 2 shows the results of the good circuit simulation.
I. Introduction The International Technology Roadmap for Semiconductors (ITRS), in its 1999 edition, addressed several issues that will challenge chip designers, test engineers and the testing community as a whole. Among these issues are: the tremendous increase in circuit size, the rapid increase in clock frequencies, the dominance of the interconnect delay, the transmissionline behavior of interconnects, the reduced level of the power supply voltage, the increase in leakage currents, the increase in power consumption, and the increased sensitivity of a design to the process defects. These factors give rise to new types of defects that, on one hand, can no longer be represented using the existing fault models, and on the other hand, cannot be easily detected using traditional voltage testing techniques as well as the single threshold IDDQ test. Consequently, more effective techniques are being investigated and proposed by researchers. Among these techniques is Delta-IDDQ testing [1]-[5] and Dynamic Current Testing [6]-[13]. In this paper, we characterize iDDT as related to the switching of CMOS random logic circuits in very deep sub-micron technologies. We analyze the effects of resistive defects -bridges and
II.1 Double Threshold iDDT This method is based on the fact that a good circuit will always have a lower bound and an upper bound of peak iDDT values in response to selected input vector pairs. Figure 2 shows the lower and upper bounds for the circuit under study. If a circuit draws a peak iDDT value that is either lower than the lower bound or higher than the upper bound (within a given tolerance), a defect may be inferred. As an example, we can see that the peak values of the iDDT spikes range from 220 to 350 µA. A resistive open of 100 KΩ at the gate of the PMOS transistor P7 in Figure-2, will produce, in response to vectors “1000” and “0000” two iDDT spikes with values of 327 and 147 µA respectively. The second spike is 33% lower than the lower bound (220) and hence such a defect can be detected using the double threshold iDDT method. The threshold for detection using this method was set to 20% (faulty iDDT is 20% lower/higher than good iDDT). The test vector set is such that no test vector outside the set will produce iDDT outside the minimum and maximum bounds in Figure 2.
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
Figure 1. Transistor-Level Schematic of the Good Circuit
400
350
300
Peak IDDT (mA)
250
200
150
100
50
0 1
2
3
4
5
6
7
8
9
10
11 12 13
14 15 16 17
18 19 20 21
22 23 24 25
26 27 28 29
Vector #
Figure 2. Peak iDDT for All Possible Input Vectors (Transitions)
II.2 Delta iDDT We define two input vectors to be complimentary if they cause opposite transitions of the circuit’s output and along the same path, like the vectors “1000” and “0000”. This method is based on the fact that, in response to 2 complimentary vectors, a good circuit will have a difference in the corresponding iDDT spikes limited between a lower bound and an upper bound. This difference is bound in our example between 0 and 112 µA. The reason for proposing this methodology is that a defective circuit can draw iDDT spikes with peak magnitudes that are within the good circuit limits or slightly outside the limits as defined in the double iDDT threshold method. However, the difference of such peak magnitudes can amplify in some cases the abnormal behavior of iDDT and produce a value outside the good circuit limits as defined in Delta iDDT. Consider the same example used in the double iDDT
30
Figure 3: Logic Extract from an Intel Chip Based on a 0.18-micron Process
threshold method. The difference in the peak magnitudes of iDDT in response to the vectors “1000” and “0000” are 4 µA for the good circuit and 180 µA for the defective one, and hence, such a defect can be detected.
II.3 Delayed iDDT This method is based on the fact that a good circuit is normally expected to switch, and hence to draw an iDDT pulse within a specific time interval. Outside such an interval, no pulse should be observed. This time interval is dictated by the circuit's speed and by the frequency of operation. If a particular defect causes a delay in the circuit's response, this delay will be reflected in a delayed iDDT pulse. If the delay is unacceptable, it can shift the iDDT pulse outside the window of observation. If we shift the window of
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
observation past the time where a good circuit is supposed to switch, then this pulse, if it has an appreciable magnitude, will be detected.
III. Results The correlation between resistive opens/bridges and each of the 3 methodologies were investigated by the manual insertion of resistors in the circuit shown in Figure 1. The resistors were inserted at different locations in the circuit and with different resistor values, simulating the effects of opens and shorts as well as benign faults that do not affect the circuit operation. Table 1 summarizes the results. The simulations were performed at a speed of 166 MHz where each vector takes 1 ns of setup time (fall/rise), and a 5 ns steady value. The results of the simulations show that for the circuit under analysis, the Double
Resistive Opens
Number of defects Considered 40
Resistive Shorts
9
iDDT Threshold method performs very well and is capable of detecting all the defects that were introduced at the transistor terminals and that are causing a delay of 0.5 ns or more. On the other hand, the Delta iDDT method is very sensitive to the location of the defects. It can detect a defect producing a delay as small as 0.1 ns in one location but can only detect a defect causing a logic failure in another location. This method behaves poorly when the defect causes the iDDT spikes, resulting from complimentary vectors, to change in the same direction; i.e. for both of them to increase or both of them to decrease. However, if the two spikes change in opposite directions, the Delta iDDT method performs very well. As for the Delayed iDDT method, it can detect resistive opens that cause a measurable delay value.
Number (Percentage) of defects Detected by: Double Threshold Delta Delayed iDDT iDDT iDDT 38 (95%)
29 (72.5%)
24 (60%)
Number of Defects Not Detected By any Method 1 (2.5%)
8 (89%)
1 (11%)
9 (100%)
0 (0%)
Table 1. Results Summary
IV. Effect of the Process Technology As the process technology scales down, the transistor transconductance k’ increases, while the power supply voltage, and the threshold voltage decrease, and the overall effect is a reduction in the peak magnitude of iDDT per device. This fact has been verified by simulating an inverter with various process technologies and the results are shown in Table-2 below. On the other hand, and within the same process technology, the shape and the peak magnitude of iDDT are also affected by the process variations, and they behave differently at different corners of the process. This was verified by the following experiment based on a 0.18-micron process technology for the circuit of Figure 3. The circuit was simulated over three different process skews, one for a typical skew, another one for the slowest skew, and the last one for the fastest skew. An input vector "00001" was inserted through the scan chain. The first 4 zeros will initialize all 4 inputs as well as the output to zero, and the last shifted “1” will cause a transition on the output from “0” to “1”, at which time the iDDT response is captured. The vector insertion process through the scan chain is done via two non-overlapping scan clocks. The iDDT responses
for the three different skews of the good circuit are shown in Figure 4. These results show a change in the peak magnitude of iDDT and a change in the spread over time of the iDDT response among the different process skews. This change is consistent with the nature of the process where, for instance, the slow skew exhibits a lower iDDT peak value and a longer time to settle when compared with the other skews. This result is interesting for it can be used for speed binning.
V. Scalability Issues We have conducted preliminary experiments to investigate the effects of switching a large number of gates on the sensitivities of the three iDDT test methods. At this stage we can say that the threshold iDDT test method looses ground relatively quickly with the number of simultaneously switching gates (as compared to the other two methods) unless test vectors are selected in a way so as to switch a minimum number of gates simultaneously. The scalability issues are intimately related to two important parameters:
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
1.
2.
Selection of test vectors: Test vectors are selected to switch a minimum number of gates simultaneously. The sensitivity of the sensor which is employed: This has to do with the maximum circuit size that a sensor can support, given the total circuit leakages and switching profile.
sensor. In general, more capable sensors result in less partitions. So the issue is not simply whether the iDDT test method works for a large circuit, but also how many sections would we need to partition the circuit into (for iDDT measurement purposes) and is the overhead acceptable. Last, the iDDT test methods should not be considered a stand-alone test, but rather supporting other methods to increase coverage .
A large circuit would have to be partitioned into sections such that each section can be supported by a
Process (micron) 1.2 0.5 0.35 0.18
First iDDT Peak (µA) 113 81 58 41
Second iDDT Peak (µA) 144 112 86 58
Table-2: Effect of the Process Technology on iDDT
Slow -0.16
Fast -0.45
Typical -0.36 Figure 4. iDDT Response Over 3 Process Skews
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
VI. Conclusions Three iDDT test methods were studied; Double Threshold iDDT, Delta iDDT, and Delayed iDDT. It was shown that the threshold and Delta iDDT are effective in detecting both short and open defects if iDDT pulses are effectively controlled with select input test vectors that switch a minimum amount of gates. It was also shown that the delayed iDDT test is primarily effective in detecting opens. The key issues are the ability to control the iDDT pulse peak values and the effectiveness of the sensor that is deployed.
[11]
[12]
[13]
J. Plusquellic, D. Chiarulli, S. Levitan. “Characterization of CMOS Defects using Transient Signal Analysis,” DFT, pp. 93-101, November 1998. R. Makki, S. Su, T. Nagle, “Transient Power Supply Current Testing of Digital CMOS Circuits,” ITC, 1995, pp. 892–901. S. Su, R. Makki, T. Nagle, “Transient Power Supply Current Monitoring – A New Test Method for CMOS VLSI Circuits,” Journal of Electronic Testing: Theory and Applications, pp. 23-43, February 1995.
Acknowledgements This work was funded by the National Science Foundation under award CCR 9912412 and by a grant from Intel Corporation.
References [1]
[2]
[3] [4] [5]
[6]
[7]
[8]
[9]
[10]
C. Thibeault, “An Histogram Based Procedure for Current Testing of Active Defects,” Int. Test Conf., 1999, pp. 714-723. A. C. Miller, “IDDQ Testing in Deep Submicron Integrated Circuits,” Int. Test Conf., 1999, pp. 724-729. K. Baker, “SIA Roadmaps: Sunset Boulevard for IDDQ”, Int. Test Conf., 1999, p. 1121. D. Bhavsar, “ITC99 Panels,” IEEE Design & Test, vol. 16, no. 4, Oct.-Dec. 1999, pp. 96-99. C. F. Hawkins, J.M. Soden, “Deep Submicron CMOS Current IC Testing: Is There a Future?” IEEE Design & Test, vol. 16, no. 4, Oct.-Dec. 1999, pp. 14-15. B. Kruseman, P. Janssen, V. Zieren, “Transient Current Testing of 0.25 µm CMOS Devices,” Int. Test Conf., 1999, pp. 47-56. M. Sachdev, P. Janssen, V. Zieren, “Defect Detection with Transient Current Testing and its Potential for Deep Sub-micron CMOS ICs,” Int. Test Conf., 1998, pp.204-213. W. Jiang, B. Vinnakota, “Statistical Threshold Formulation For Dynamic Idd Test,” Int. Test Conf., 1999, pp. 57-66. B. Vinnakota, “Monitoring Power Dissipation for Fault Detection,” 14th VTS, pp. 483-488, 1996. A. Germida, Z. Yan, J. Plusquellic, F. Muradali, “Defect Detection using Power Supply Transient Signal Analysis,” Int. Test Conf., 1999, pp. 67-76.
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
