Test pattern generation for analog circuits using neural networks and
TEST PATTERN GENERATION FOR ANALOG CIRCUITS USING NEURAL NETWORKS AND EVOLUTIVE ALGORITHMS
J.L. Bernier, J.J. Merelo, J. Ortega and A. Prieto Dpto. Electrónica y Tecnología de computadores Campus Fuentenueva s/n. Facultad de Ciencias 18071 Granada. Spain
Abstract This paper presents a comparative analysis of neural networks, simulated annealing, and genetic algorithms in the determination of input patterns for testing analog circuits. The problem has been modelled as an optimization problem in which the objective is to determine a test signal that maximizes the quadratic difference between the nominal response and the faulty one due to a defect in the circuit. This approach makes possible the search of the test pattern space by using techniques based on neural and evolutive algorithms.
I. INTRODUCTION. The ever increasing capabilities of VLSI technology have allowed to include complex analog and digital circuits in a single chip. As the size of that circuits grows, the need for tools to automate designing and testing of circuits is higher. One of the most important step in the process of manufacturing a circuit is its test. It allows to assure that the circuit will work according to the specifications. As more and more circuits are included in a single chip, the cost of testing it is increased not only because its size has grown, but also because its controllability and observability have decreased. Moreover, it is difficult to find accurate solutions to some important problems which appear in the test of circuits because they are NPcomplete problems [1]. Focusing on digital circuit testing, there are several efficient procedures to generate test patterns and even some standards [2] about procedures to increase the testability of the circuits. The situation is worst in the analog testing field due mainly to the following two reasons: 1.
The size of the majority of analog circuits was small two decades ago, so it was possible an efficient manual generation of the test patterns.
2.
The specific difficulties of analog testing compared with digital testing. More precisely, the lack of simple and accurate models for the possible defects of the analog circuits, and the tolerance of the analog elements that in some cases allows a circuit to function according to the specifications, even when its parameters have some deviation with respect to its nominal values. A possible procedure to detect faults in an analog circuit can be implemented by using the following steps: Test procedure 1) Generation: 1.1) Define a set of potential faults. 1.2) Obtain a set of test patterns for these faults.
2) Application: 2.1) Apply the test patterns to the circuit under test. 2.2) If the difference in the output is greater than a predetermined threshold the circuit is diagnosed as faulty.
As it is shown from step 1.2) in the previous procedure, one of the problems which appears in the test of analog circuits is the determination of a set of patterns to detect if the circuit is faulty. It belongs to the class of NP-complete problems which means that a high amount of computing time would be required to find patterns for testing analog circuits with high, or even medium size. The problem of automatic test pattern generation for analog circuits has been discussed in some previous papers [3,4]. In [4] the problem is formulated as an optimization problem where the goal is to obtain the set of input patterns which maximize the "difference" of responses from normal and faulty circuit. Thus, for a given fault the input stimulus x(t) selected as test pattern should maximize the difference between the outputs y(t) and y*(t), corresponding to the correct and the faulty circuit, respectively. In what follows, it is provided a function which allows to quantify the difference between responses of circuits with and without faults [4]. It can be obtained by representing the behaviour of the circuits by the discrete version of their impulse response, hn for the correct circuit, and h*n for the faulty one, and using the convolution to describe the outputs in term of the input stimulus, xi: (1)
(2)
and, this way, yn-y*n is (3)
where (4)
As the input xi corresponds to a set of instants, i=0,..,n, it is possible to define a function which represents the overall difference between y and y*: (5)
This way, the pattern generation for testing a fault in an analog circuit is expressed as a search for the values of xi, i=0,..,n that maximize D, given h*n to model the effect of the fault in the circuit represented by hn. It is possible to show [4] that the function, D, to maximize is semipositive quadratic in terms of xi, thus the problem to solve is a quadratic programming problem. This way, the maximum of D must occur for xi=±Vmax, and since Vmax would be a common factor in (5), the problem is to find an optimal assignment of +1 or -1 to each xi. As it has been said, the optimization problem to solve is a quadratic programming problem, which is NP-complete. There are some numerical methods that allow to determine a local maximum in an iterative way [5] or by using a heuristic algorithm [4] but they do not assure to find a global maximum. In this paper, it is studied the use of the Hopfield neural network,
Simulated Annealing, and Genetic Algorithms to maximize (5), thus providing the test pattern for a given analog circuit. These methods, besides introducing new ways to guide the search towards a global maximum in the solution space, provide a methodology that has the potential to exploit fine-grain parallel computing [6]. Thus, they would give way and make easy to use the massively parallel computers in compute-intensive CAD applications. The rest of the paper is structured in six sections as follows. The description of the set of analog circuits used to make the experimental comparison among the different methods is described in Sect. II. Sections III to V deal with the characteristics and performances evaluated for each method used to optimize (5). Finally, the comparative analysis of the different procedures and the conclusions are provided in Sect. VI., while the references are given in Sect. VIII. II. BENCHMARK CIRCUITS. As benchmark circuits we have used a set of lowpass analog Chebyshev filters [7] with order n=1, ...,10, a cutoff frequency at wo=300 and a 0.5db ripple. The transference function for this kind of circuits is (6)
where n is called the order of the filter. Fig. 1 shows the typical gain response for such circuits in the frequency domain. Higher values for the filter order implies a better approximation to an ideal filtering function (step). By using a bilinear transform the frequency response (Fig. 1) can be mapped into the digital plane in order to obtain the discrete impulse response h (Fig. 2). The set of defects that can modify the right behaviour of the filter has been modelled as a +50% deviation in the value of each ai, with i=1...n+1. Different patterns have been generated for different circuits with order n=1,2,..,10 using the MATLAB package [7] to calculate the coefficients ai for each filter and the matrix ∆h defined in (4).
Figure 1. Gain response of a fourth-order filter.
Figure 2. Discrete impulse response of the filter.
III. TEST GENERATION WITH THE HOPFIELD NETWORK. The Tsai’s algorithm [4] is quite similar to a Hopfield network. In this algorithm, for convenience, (5) is expressed as: (7)
This way, the algorithm in [4] works according to the following steps: 1) 2) 3) 4)
Do xi=1 for i=0,...,n Calculate the minimum Pi = Pmin. If Pmin
J.L. Bernier, J.J. Merelo, J. Ortega and A. Prieto Dpto. Electrónica y Tecnología de computadores Campus Fuentenueva s/n. Facultad de Ciencias 18071 Granada. Spain
Abstract This paper presents a comparative analysis of neural networks, simulated annealing, and genetic algorithms in the determination of input patterns for testing analog circuits. The problem has been modelled as an optimization problem in which the objective is to determine a test signal that maximizes the quadratic difference between the nominal response and the faulty one due to a defect in the circuit. This approach makes possible the search of the test pattern space by using techniques based on neural and evolutive algorithms.
I. INTRODUCTION. The ever increasing capabilities of VLSI technology have allowed to include complex analog and digital circuits in a single chip. As the size of that circuits grows, the need for tools to automate designing and testing of circuits is higher. One of the most important step in the process of manufacturing a circuit is its test. It allows to assure that the circuit will work according to the specifications. As more and more circuits are included in a single chip, the cost of testing it is increased not only because its size has grown, but also because its controllability and observability have decreased. Moreover, it is difficult to find accurate solutions to some important problems which appear in the test of circuits because they are NPcomplete problems [1]. Focusing on digital circuit testing, there are several efficient procedures to generate test patterns and even some standards [2] about procedures to increase the testability of the circuits. The situation is worst in the analog testing field due mainly to the following two reasons: 1.
The size of the majority of analog circuits was small two decades ago, so it was possible an efficient manual generation of the test patterns.
2.
The specific difficulties of analog testing compared with digital testing. More precisely, the lack of simple and accurate models for the possible defects of the analog circuits, and the tolerance of the analog elements that in some cases allows a circuit to function according to the specifications, even when its parameters have some deviation with respect to its nominal values. A possible procedure to detect faults in an analog circuit can be implemented by using the following steps: Test procedure 1) Generation: 1.1) Define a set of potential faults. 1.2) Obtain a set of test patterns for these faults.
2) Application: 2.1) Apply the test patterns to the circuit under test. 2.2) If the difference in the output is greater than a predetermined threshold the circuit is diagnosed as faulty.
As it is shown from step 1.2) in the previous procedure, one of the problems which appears in the test of analog circuits is the determination of a set of patterns to detect if the circuit is faulty. It belongs to the class of NP-complete problems which means that a high amount of computing time would be required to find patterns for testing analog circuits with high, or even medium size. The problem of automatic test pattern generation for analog circuits has been discussed in some previous papers [3,4]. In [4] the problem is formulated as an optimization problem where the goal is to obtain the set of input patterns which maximize the "difference" of responses from normal and faulty circuit. Thus, for a given fault the input stimulus x(t) selected as test pattern should maximize the difference between the outputs y(t) and y*(t), corresponding to the correct and the faulty circuit, respectively. In what follows, it is provided a function which allows to quantify the difference between responses of circuits with and without faults [4]. It can be obtained by representing the behaviour of the circuits by the discrete version of their impulse response, hn for the correct circuit, and h*n for the faulty one, and using the convolution to describe the outputs in term of the input stimulus, xi: (1)
(2)
and, this way, yn-y*n is (3)
where (4)
As the input xi corresponds to a set of instants, i=0,..,n, it is possible to define a function which represents the overall difference between y and y*: (5)
This way, the pattern generation for testing a fault in an analog circuit is expressed as a search for the values of xi, i=0,..,n that maximize D, given h*n to model the effect of the fault in the circuit represented by hn. It is possible to show [4] that the function, D, to maximize is semipositive quadratic in terms of xi, thus the problem to solve is a quadratic programming problem. This way, the maximum of D must occur for xi=±Vmax, and since Vmax would be a common factor in (5), the problem is to find an optimal assignment of +1 or -1 to each xi. As it has been said, the optimization problem to solve is a quadratic programming problem, which is NP-complete. There are some numerical methods that allow to determine a local maximum in an iterative way [5] or by using a heuristic algorithm [4] but they do not assure to find a global maximum. In this paper, it is studied the use of the Hopfield neural network,
Simulated Annealing, and Genetic Algorithms to maximize (5), thus providing the test pattern for a given analog circuit. These methods, besides introducing new ways to guide the search towards a global maximum in the solution space, provide a methodology that has the potential to exploit fine-grain parallel computing [6]. Thus, they would give way and make easy to use the massively parallel computers in compute-intensive CAD applications. The rest of the paper is structured in six sections as follows. The description of the set of analog circuits used to make the experimental comparison among the different methods is described in Sect. II. Sections III to V deal with the characteristics and performances evaluated for each method used to optimize (5). Finally, the comparative analysis of the different procedures and the conclusions are provided in Sect. VI., while the references are given in Sect. VIII. II. BENCHMARK CIRCUITS. As benchmark circuits we have used a set of lowpass analog Chebyshev filters [7] with order n=1, ...,10, a cutoff frequency at wo=300 and a 0.5db ripple. The transference function for this kind of circuits is (6)
where n is called the order of the filter. Fig. 1 shows the typical gain response for such circuits in the frequency domain. Higher values for the filter order implies a better approximation to an ideal filtering function (step). By using a bilinear transform the frequency response (Fig. 1) can be mapped into the digital plane in order to obtain the discrete impulse response h (Fig. 2). The set of defects that can modify the right behaviour of the filter has been modelled as a +50% deviation in the value of each ai, with i=1...n+1. Different patterns have been generated for different circuits with order n=1,2,..,10 using the MATLAB package [7] to calculate the coefficients ai for each filter and the matrix ∆h defined in (4).
Figure 1. Gain response of a fourth-order filter.
Figure 2. Discrete impulse response of the filter.
III. TEST GENERATION WITH THE HOPFIELD NETWORK. The Tsai’s algorithm [4] is quite similar to a Hopfield network. In this algorithm, for convenience, (5) is expressed as: (7)
This way, the algorithm in [4] works according to the following steps: 1) 2) 3) 4)
Do xi=1 for i=0,...,n Calculate the minimum Pi = Pmin. If Pmin
