Thermal characterization and modeling of power ... - Semantic Scholar
Thermal characterization and modeling of power hybrid converters for distributed power systems P. Cova* , N. Delmonte, R. Menozzi University of Parma, Dipartimento di Ingegneria dell’Informazione Viale G.P. Usberti, 181/A - Parma, Italy Abstract We have developed and experimentally validated a 3D model for thermal analysis and reliability-conscious design of hybrid power converters, using the commercial finite-elementsolver COMSOLTM. The model was tuned using an accurate packaged MOSFET model and a specially-designed test board for multi-point temperature measurements. Measured and modeled temperatures showed good agreement for various dissipated power levels. A simplified version of the packaged MOSFET was then used in a bridge configuration to build a thermal model of the converter. After thermal studies, we performed preliminary finite-element analysis of the thermally-induced stress distributions.
1. Introduction The use of distributed power systems (DPS) is strongly growing in computing (e.g. servers) and telecom (e.g. routers) applications [1]. In a DPS a main power supply feeds different local power supplies (called “Point of Load” - POL), each dedicated to a single board or a board cluster. Every point of load is designed to supply a specific voltage required to bias particular circuits (analog, digital, I/O, etc.). Fig. 1 shows an example of DPS structure. Due to the increasing conversion frequencies and power requirements, together with the need of compactness, the EMC and thermal problems are becoming the bottleneck in designing each power supply level.
* Corresponding author. [email protected] Tel: +39 0521 905818; Fax: +39 0521 905822
On-board converter Power Factor Correction
DC/DC Bus converter
400 V 12 V 500 W 500 kHz
High-Volt VRM On-board converter Low-Volt VRM
POL
Fig. 1. Basic configuration of a DPS [2].
In particular, when hybrid solutions are considered, the thermal design has important reliability implications, due to the presence of different materials in intimate contact, which can give thermo-mechanical problems, such as delamination, solder creep, ceramic crack, and so on
[3]. For these reasons, power supply design needs accurate coupled thermo-mechanical simulation of the whole system. D2PAK
Si die Fig. 2. External view an internal layout of D2PAK package for power MOSFETs.
Drain Al flange Gate Gate Sourc e
In this work we show a case study of thermal characterization and modeling of a 500W-12V DC/DC bus converter for communication systems. In order to show the usefulness of the design procedure, we simulated a simple full-bridge DC/DC converter fabricated with hybrid SMD technology, both on a standard FR4 PCB and on a multilayer board on metal substrate (e.g., Bergquist Thermal Clad). The model can be easily modified for different converter solutions, such as low-voltage POL converters, by simply changing device specifications and current levels. The thermal and thermo-mechanical models were built using a Finite Element Model (FEM) software (COMSOL MultiphysicsTM) able to carry out multiphysics 3D simulations. The heat transfer module includes Fourier conduction and convection equations [4], while the mechanical model applies the principle of virtual work [5]. 2. Single-MOSFET thermal model experimental validation
and
2.1. Packaged device and its FEM model The active device chosen for the bus converter was a STP20NM50 500V-20A power MOSFET mounted on a D2PAK package. In Fig. 2 we show the external view of the device, together with a schematics of the internal layout, taken from the data sheet. The drain contact is connected through a solder layer with the aluminum flange of the package, which acts as mechanical support, as well as electrical contact and heat sink.
Source
Drain Al flange
Fig. 3. 3D model of the D2PAK packaged MOSFET used in the simulations.
The first step in the modeling procedure was building a 3D model for the single packaged MOSFET. The model is shown in Fig. 3. The silicon die is treated as a uniform heat source, since our focus was on package materials, interfaces and solder layers, which are the main cause of thermomechanical failures. Geometrical dimensions and thermal parameters were obtained whenever possible from data sheets and communications from the package manufacturer. 2.2. The thermal test board The test board for model tuning was made using standard FR4 PBC technology. The layout is very simple, and it allows to DC-bias the device under test (D.U.T.) and to measure temperatures by means of thermocouples placed at different locations. Fig. 4 shows the test PCB and the test points. 2.2.1. Silicon temperature measurement We measured the silicon die temperature by an indirect method, using the drain to source voltage at a fixed drain current (ID = 250 µ A), as the temperature-sensitiveparameter (TSP), because it has a large dependence on the channel temperature [6]. The measurements were done with VGS = VDS. The calibration curve VDS(T), measured in a climatic chamber, shows an almost linear behavior, with a sensitivity of about -5.5 mV/°C. In order to measure the silicon temperature during the device on-state, we used the set-up illustrated by the block scheme of Fig. 5: the MOSFET is current biased (e.g. ID = 1 A) and, after reaching the thermal regime, the main power supply is switched off and only the 250 µA
measuring current is left on the device. VDS is then sampled (see. Fig. 6) after a time much shorter than the thermal time constant of the silicon die (which is of the order of hundred of ms [7]); from the sampled VDS and the calibration curve, we extract the device channel temperature.
V DS Trigg.
5 µs 200 mV
Cu, close to the D.U.T. Backside FR4 surface
V DS(T) @ ID=250 µA
Al drain flange (through hole)
Top of the package
0 Fig. 6. Indirect measurement of the die temperature: VDS was acquired just after the end of the electrical transient following the switchoff of the main supply.
Fig. 4. FR4 thermal test board: the test points indicated by the arrows.
1A CURRENT SUPPLY
RELAY
D.U.T.
SCOPE DRIVER
Temperature increase [ °C ]
250 µA CURRENT SUPPLY
140
Plastic lid upper surface Silicon die Al drain flange Cu close to the drain FR4 rear surface
120 100 80 60 40 20 0 0
Fig. 5. Experimental set-up for die temperature indirect measurement.
We performed temperature measurement for dissipated power ranging from 1.16 to 4.4 W. The ambient temperature was always monitored and ranged between 20 and 24°C. The measurements were repeated several times, in order to reduce random experimental errors, and for a few nominally identical devices. Fig. 7 shows the results of the measurements, in terms of temperature increase with respect to the ambient.
t
1 2 3 4 D.U.T. power dissipation [ W ]
5
Fig. 7. Results of the thermal measurements.
2.3 The FEM model of the test board In order to make a comparison between measurements and simulations, we created a 3D FE model of the test board. The model of the single device was included and different meshing techniques were adopted for proper FEM treatment of layers with different thickness. Fig. 8 shows the model of the complete PCB. We added an interface solder layer between the Al flange and the Cu footprint.
for the silicon die. Table 2 Measured (simulated) temperature increases in Celsius at the test points.
D.U.T. power
Fig. 8. 3D Model of the test PCB. The colored areas indicate the Cu footprints.
2.3.1. Tuning the model Table 1 shows the parameter values used in the simulations. Whenever possible we calculated the parameters from analytical formulas (as in the case of the top convection coefficient, hup [8]), or used the default values of the simulator (as for parameters kSiA l and kAl-Cu in Table 1); in this way, we limited the number of fitting parameters to three: the thermal conductance of the FR4 board, that of the package plastic lid, and the backside convection coefficient. Table 1 Heat transfer parameters used for the finite element analysis. Parameter Symbol Value Unit Top convection coefficient Backside convection coefficient (fitting parameter) Thermal conductance Si-Al bonding layer
h up
11 1 5
W°C-1m-2
h FR4
25
W°C-1m-2
kSi-Al
50
W°C-1m-1
Temperature increase [°C]
Position 1.19 W Packag 26 e top (26) 39 Si die (36) Al 33 flange (35) Cu close 32 to D.U.T. (33) FR4 21 back (22) 140
2.29 W
3.36 W
4.4 W
48 (49) 75 (69) 66 (67) 61 (63) 42 (41)
71 (69) 104 (98) 94 (96) 89 (91) 58 (59)
92 (88) 131 (126) 122 (123) 112 (117) 74 (76)
Fig. 9. Measured and the silicon die ver
Measurements Simulations
120 100 80 60 40 20 0
2
4
6
D.U.T. power [ W ]
3. Thermal model of the whole converter
Thermal conductance kAl-Cu Al-Cu bonding layer Thermal conductance kFR4 FR4 (fitting parameter) Thermal conductance plastic lid (fitting klid parameter)
-1
-1
50
W°C m
0.1
W°C-1m-1
0.1
W°C-1m-1
After tuning the model we obtained a good agreement between measured and simulated temperatures, for the whole power range and all the test points, as shown in Table 2. Fig.9 shows the comparison between measurements and simulations
As a test vehicle for our case study, we choose a hybrid bridge converter in SMD technology. We simulated two versions of the converter, using two different technologies: A) standard technology, with a 1.5-mm FR4 PCB and 35-mm Cu layer; B) multilayer board featuring a 75-µm thermally conductive dielectric layer on top of a 0.5-mm bottom copper baseplate, with 35-µm thick top copper metal lines. The active components are four power MOSFETs; the power dissipation per MOSFET is 3.5 W in case A, 17 W in case B. In order to limit the computational overhead for these full converter simulations, we developed a simplified model of the packaged MOSFET and
validated it by means of a comparison with the full model described above. In the simplified model we neglected the heat exchange through the leads (after verification that the error introduced on the extracted temperatures was negligible), while the thermal conductivity of Al was adjusted to include the thermal resistance of the two bonding layers.
thermal map of the two versions of the bridge converter: it can be noticed that, due to the presence of the copper baseplate, the multilayer version can manage about five times as much power as the FR4 version, with lower temperatures. Fig. 11 compares the temperature distributions along a vertical axis in the two technologies, with a dissipated power of 3.4 W: we found peak temperatures of about 120°C in the case of FR4 and 75°C in the multilayer board. 4. Thermo-mechanical simulations
Fig. 10. Thermal map of the surface of a hybrid converter simulated with simplified D2PAK model in the case of standard FR4 technology (a) and thermal multilayer (b). The power dissipated by each MOSFET is 3.5 W (a) and 17 W (b). T max = 120 °C
130 FR4
Temperature [°C]
120 110 flange
100
lid
90
die solder
80
multilayer
70 60 0
2
4
6
Vertical position [mm]
Fig. 11. Temperature along a vertical axis in the case of FR4 PCB and multilayer boards. The dissipated power is 3.4 W.
Other heating blocks are added to account for power dissipated by magnetic components. As an example, Fig. 10 shows the surface
One of the main reasons for developing an accurate thermal model is the investigation of the critical points from the reliability perspective. In hybrid power circuits the most important degradation mechanisms are related with thermo-mechanical stress due to thermal cycling at interfaces between materials with different coefficients of thermal expansion (CTE). The thermal model alone can give important indications about the presence of critical conditions at the interfaces, but a deeper insight can be obtained with a thermo-mechanical model of the structure. In the case of the multi-physics simulator we used, the thermo-mechanical model couples the thermal module with a mechanical module solving the stress-strain equations for systems in the elastoplastic regime [5]. In particular, we applied the principle of virtual work, where the load is due to thermal expansion, assuming that the structure is in the stress-free state at room temperature. The thermomechanical problem was solved for the case of a single MOSFET mounted on standard FR4 PCB, with a dissipated power of 3.4 W. The solutions yield many quantities interesting for reliability studies: normal stress, shear stress, von Mises stress, strains, and so on. For example, it is speculated that “peel stress”, the direction of which is orthogonal to the board plane, plays a significant role in delamination [9]. Another important factor for solder joint reliability is the von Mises stress, useful for calculating the fatigue strength or estimating yield criteria [10]. Unlike the thermal model, out thermomechanical model is at an early stage of development: suitable test structures and experiments will have to be devised in order to tune and validate the model. As an example, Fig. 12 shows the preliminary results for peel stress evaluated along a diagonal line in the square occupied by solder (60Sn-40Pb) between the drain aluminum flange and the PCB copper layer.
thermo-mechanical model.
50 Peel stress [MPa]
0
References
-50 -100 -150 -200 -250 0
5
10
15
Position [mm]
Fig. 12. Simulated peel stress in the solder layer between the Al flange and the PCB copper layer.
Near the edges the stress is compressive, with maxima around 200 MPa at the edges in agreement with recently published results [9] (analytical models show that the peel stress should be close to zero in the middle). As expected, other stress components also show rapid increase toward the edges. However, the simulated stress profiles are noisy, probably due to non-optimal meshing of the simulated structure. 5. Conclusions Accurate and detailed thermal and thermomechanical modeling is a fundamental tool for the design of reliable power converters. We developed and experimentally validated a 3D model for the thermal analysis of hybrid power converters, using the commercial finite-element solver COMSOLTM. The model was tuned using an accurate packaged MOSFET model and a specially-designed test board for multi-point temperature measurement. Measured and modeled temperatures showed excellent agreement for various dissipated power levels. A simplified version of the packaged MOSFET was then used in a bridge configuration to build a thermal model of the whole converter. We then compared, temperature-wise, two PCB technologies, namely, standard FR4 versus multilayer board on metal substrate. Finally, we showed preliminary results of thermo-mechanical simulations aimed at evaluating interface stress/strain distributions. Further work is needed to tune and experimentally validate the
[1] Luo S. A review of distributed power systems part I: DC distributed power system. IEEE Aerospace and Electronic Systems Magazine. 20 Part 2 (2005) 5-16 [2] Lee FC, Barbosa P, Xu P,Zhang J, Yang B, Canales F. Topologies and Design Considerations for Distributed Power System Applications. Proc. IEEE. 89 (2001) 939-950. [3] Azzopardi S, Thébaud J-M, Woirgard E, Zardini C, Sablé P. Al/SiC baseplate hybrid power modules: evaluation of the thermome-chanical performances. Proc. IEEE Internat. Workshop on Integrated Power Packaging, IWIPP, (1998) 74-78. [4] Heat Transfer Module User’s Guide - COMSOL version 3.2., 2005. [5] Structural Mechanics Module User’s Guide COMSOL version 3.2., 2005. [6] Baliga BJ. Modern Power Devices. John Wiley & Sons, New York, 1987, pp. 327-329. [7] Hopkins T, Cognetti C, Tiziani R. Designing with Thermal Impedance. Proc. IV Semiconductor Thermal and Temperature Measurement Symp., SEMITHERM, 1988, pp. 55-61. [8] Mohan N, Undeland TM, Robbins WP. Power Electronics: Converters, Applications, and Design; 3rd Ed.. John Wiley & Sons, New York, 2003, pp. 739-741. [9] Zhu N, van Wyk JD, Liang ZX. Thermo-mechanical Stress Analysis for Planar Metallization i n Integrated Power Electronics Modules. Proc. IV Internat. Conference on Integrated Power Systems, CIPS, (2006) 111-116. [10] Sylvester MF, Banks DR, Le-Huu D, Kern RW. Thermal Cycling Effects on Eutectic Flip-Chip Die on Organic Packages. Proc. Internat. Conference on High-Density Interconnect and Systems Packaging, (2000) 438-443.
1. Introduction The use of distributed power systems (DPS) is strongly growing in computing (e.g. servers) and telecom (e.g. routers) applications [1]. In a DPS a main power supply feeds different local power supplies (called “Point of Load” - POL), each dedicated to a single board or a board cluster. Every point of load is designed to supply a specific voltage required to bias particular circuits (analog, digital, I/O, etc.). Fig. 1 shows an example of DPS structure. Due to the increasing conversion frequencies and power requirements, together with the need of compactness, the EMC and thermal problems are becoming the bottleneck in designing each power supply level.
* Corresponding author. [email protected] Tel: +39 0521 905818; Fax: +39 0521 905822
On-board converter Power Factor Correction
DC/DC Bus converter
400 V 12 V 500 W 500 kHz
High-Volt VRM On-board converter Low-Volt VRM
POL
Fig. 1. Basic configuration of a DPS [2].
In particular, when hybrid solutions are considered, the thermal design has important reliability implications, due to the presence of different materials in intimate contact, which can give thermo-mechanical problems, such as delamination, solder creep, ceramic crack, and so on
[3]. For these reasons, power supply design needs accurate coupled thermo-mechanical simulation of the whole system. D2PAK
Si die Fig. 2. External view an internal layout of D2PAK package for power MOSFETs.
Drain Al flange Gate Gate Sourc e
In this work we show a case study of thermal characterization and modeling of a 500W-12V DC/DC bus converter for communication systems. In order to show the usefulness of the design procedure, we simulated a simple full-bridge DC/DC converter fabricated with hybrid SMD technology, both on a standard FR4 PCB and on a multilayer board on metal substrate (e.g., Bergquist Thermal Clad). The model can be easily modified for different converter solutions, such as low-voltage POL converters, by simply changing device specifications and current levels. The thermal and thermo-mechanical models were built using a Finite Element Model (FEM) software (COMSOL MultiphysicsTM) able to carry out multiphysics 3D simulations. The heat transfer module includes Fourier conduction and convection equations [4], while the mechanical model applies the principle of virtual work [5]. 2. Single-MOSFET thermal model experimental validation
and
2.1. Packaged device and its FEM model The active device chosen for the bus converter was a STP20NM50 500V-20A power MOSFET mounted on a D2PAK package. In Fig. 2 we show the external view of the device, together with a schematics of the internal layout, taken from the data sheet. The drain contact is connected through a solder layer with the aluminum flange of the package, which acts as mechanical support, as well as electrical contact and heat sink.
Source
Drain Al flange
Fig. 3. 3D model of the D2PAK packaged MOSFET used in the simulations.
The first step in the modeling procedure was building a 3D model for the single packaged MOSFET. The model is shown in Fig. 3. The silicon die is treated as a uniform heat source, since our focus was on package materials, interfaces and solder layers, which are the main cause of thermomechanical failures. Geometrical dimensions and thermal parameters were obtained whenever possible from data sheets and communications from the package manufacturer. 2.2. The thermal test board The test board for model tuning was made using standard FR4 PBC technology. The layout is very simple, and it allows to DC-bias the device under test (D.U.T.) and to measure temperatures by means of thermocouples placed at different locations. Fig. 4 shows the test PCB and the test points. 2.2.1. Silicon temperature measurement We measured the silicon die temperature by an indirect method, using the drain to source voltage at a fixed drain current (ID = 250 µ A), as the temperature-sensitiveparameter (TSP), because it has a large dependence on the channel temperature [6]. The measurements were done with VGS = VDS. The calibration curve VDS(T), measured in a climatic chamber, shows an almost linear behavior, with a sensitivity of about -5.5 mV/°C. In order to measure the silicon temperature during the device on-state, we used the set-up illustrated by the block scheme of Fig. 5: the MOSFET is current biased (e.g. ID = 1 A) and, after reaching the thermal regime, the main power supply is switched off and only the 250 µA
measuring current is left on the device. VDS is then sampled (see. Fig. 6) after a time much shorter than the thermal time constant of the silicon die (which is of the order of hundred of ms [7]); from the sampled VDS and the calibration curve, we extract the device channel temperature.
V DS Trigg.
5 µs 200 mV
Cu, close to the D.U.T. Backside FR4 surface
V DS(T) @ ID=250 µA
Al drain flange (through hole)
Top of the package
0 Fig. 6. Indirect measurement of the die temperature: VDS was acquired just after the end of the electrical transient following the switchoff of the main supply.
Fig. 4. FR4 thermal test board: the test points indicated by the arrows.
1A CURRENT SUPPLY
RELAY
D.U.T.
SCOPE DRIVER
Temperature increase [ °C ]
250 µA CURRENT SUPPLY
140
Plastic lid upper surface Silicon die Al drain flange Cu close to the drain FR4 rear surface
120 100 80 60 40 20 0 0
Fig. 5. Experimental set-up for die temperature indirect measurement.
We performed temperature measurement for dissipated power ranging from 1.16 to 4.4 W. The ambient temperature was always monitored and ranged between 20 and 24°C. The measurements were repeated several times, in order to reduce random experimental errors, and for a few nominally identical devices. Fig. 7 shows the results of the measurements, in terms of temperature increase with respect to the ambient.
t
1 2 3 4 D.U.T. power dissipation [ W ]
5
Fig. 7. Results of the thermal measurements.
2.3 The FEM model of the test board In order to make a comparison between measurements and simulations, we created a 3D FE model of the test board. The model of the single device was included and different meshing techniques were adopted for proper FEM treatment of layers with different thickness. Fig. 8 shows the model of the complete PCB. We added an interface solder layer between the Al flange and the Cu footprint.
for the silicon die. Table 2 Measured (simulated) temperature increases in Celsius at the test points.
D.U.T. power
Fig. 8. 3D Model of the test PCB. The colored areas indicate the Cu footprints.
2.3.1. Tuning the model Table 1 shows the parameter values used in the simulations. Whenever possible we calculated the parameters from analytical formulas (as in the case of the top convection coefficient, hup [8]), or used the default values of the simulator (as for parameters kSiA l and kAl-Cu in Table 1); in this way, we limited the number of fitting parameters to three: the thermal conductance of the FR4 board, that of the package plastic lid, and the backside convection coefficient. Table 1 Heat transfer parameters used for the finite element analysis. Parameter Symbol Value Unit Top convection coefficient Backside convection coefficient (fitting parameter) Thermal conductance Si-Al bonding layer
h up
11 1 5
W°C-1m-2
h FR4
25
W°C-1m-2
kSi-Al
50
W°C-1m-1
Temperature increase [°C]
Position 1.19 W Packag 26 e top (26) 39 Si die (36) Al 33 flange (35) Cu close 32 to D.U.T. (33) FR4 21 back (22) 140
2.29 W
3.36 W
4.4 W
48 (49) 75 (69) 66 (67) 61 (63) 42 (41)
71 (69) 104 (98) 94 (96) 89 (91) 58 (59)
92 (88) 131 (126) 122 (123) 112 (117) 74 (76)
Fig. 9. Measured and the silicon die ver
Measurements Simulations
120 100 80 60 40 20 0
2
4
6
D.U.T. power [ W ]
3. Thermal model of the whole converter
Thermal conductance kAl-Cu Al-Cu bonding layer Thermal conductance kFR4 FR4 (fitting parameter) Thermal conductance plastic lid (fitting klid parameter)
-1
-1
50
W°C m
0.1
W°C-1m-1
0.1
W°C-1m-1
After tuning the model we obtained a good agreement between measured and simulated temperatures, for the whole power range and all the test points, as shown in Table 2. Fig.9 shows the comparison between measurements and simulations
As a test vehicle for our case study, we choose a hybrid bridge converter in SMD technology. We simulated two versions of the converter, using two different technologies: A) standard technology, with a 1.5-mm FR4 PCB and 35-mm Cu layer; B) multilayer board featuring a 75-µm thermally conductive dielectric layer on top of a 0.5-mm bottom copper baseplate, with 35-µm thick top copper metal lines. The active components are four power MOSFETs; the power dissipation per MOSFET is 3.5 W in case A, 17 W in case B. In order to limit the computational overhead for these full converter simulations, we developed a simplified model of the packaged MOSFET and
validated it by means of a comparison with the full model described above. In the simplified model we neglected the heat exchange through the leads (after verification that the error introduced on the extracted temperatures was negligible), while the thermal conductivity of Al was adjusted to include the thermal resistance of the two bonding layers.
thermal map of the two versions of the bridge converter: it can be noticed that, due to the presence of the copper baseplate, the multilayer version can manage about five times as much power as the FR4 version, with lower temperatures. Fig. 11 compares the temperature distributions along a vertical axis in the two technologies, with a dissipated power of 3.4 W: we found peak temperatures of about 120°C in the case of FR4 and 75°C in the multilayer board. 4. Thermo-mechanical simulations
Fig. 10. Thermal map of the surface of a hybrid converter simulated with simplified D2PAK model in the case of standard FR4 technology (a) and thermal multilayer (b). The power dissipated by each MOSFET is 3.5 W (a) and 17 W (b). T max = 120 °C
130 FR4
Temperature [°C]
120 110 flange
100
lid
90
die solder
80
multilayer
70 60 0
2
4
6
Vertical position [mm]
Fig. 11. Temperature along a vertical axis in the case of FR4 PCB and multilayer boards. The dissipated power is 3.4 W.
Other heating blocks are added to account for power dissipated by magnetic components. As an example, Fig. 10 shows the surface
One of the main reasons for developing an accurate thermal model is the investigation of the critical points from the reliability perspective. In hybrid power circuits the most important degradation mechanisms are related with thermo-mechanical stress due to thermal cycling at interfaces between materials with different coefficients of thermal expansion (CTE). The thermal model alone can give important indications about the presence of critical conditions at the interfaces, but a deeper insight can be obtained with a thermo-mechanical model of the structure. In the case of the multi-physics simulator we used, the thermo-mechanical model couples the thermal module with a mechanical module solving the stress-strain equations for systems in the elastoplastic regime [5]. In particular, we applied the principle of virtual work, where the load is due to thermal expansion, assuming that the structure is in the stress-free state at room temperature. The thermomechanical problem was solved for the case of a single MOSFET mounted on standard FR4 PCB, with a dissipated power of 3.4 W. The solutions yield many quantities interesting for reliability studies: normal stress, shear stress, von Mises stress, strains, and so on. For example, it is speculated that “peel stress”, the direction of which is orthogonal to the board plane, plays a significant role in delamination [9]. Another important factor for solder joint reliability is the von Mises stress, useful for calculating the fatigue strength or estimating yield criteria [10]. Unlike the thermal model, out thermomechanical model is at an early stage of development: suitable test structures and experiments will have to be devised in order to tune and validate the model. As an example, Fig. 12 shows the preliminary results for peel stress evaluated along a diagonal line in the square occupied by solder (60Sn-40Pb) between the drain aluminum flange and the PCB copper layer.
thermo-mechanical model.
50 Peel stress [MPa]
0
References
-50 -100 -150 -200 -250 0
5
10
15
Position [mm]
Fig. 12. Simulated peel stress in the solder layer between the Al flange and the PCB copper layer.
Near the edges the stress is compressive, with maxima around 200 MPa at the edges in agreement with recently published results [9] (analytical models show that the peel stress should be close to zero in the middle). As expected, other stress components also show rapid increase toward the edges. However, the simulated stress profiles are noisy, probably due to non-optimal meshing of the simulated structure. 5. Conclusions Accurate and detailed thermal and thermomechanical modeling is a fundamental tool for the design of reliable power converters. We developed and experimentally validated a 3D model for the thermal analysis of hybrid power converters, using the commercial finite-element solver COMSOLTM. The model was tuned using an accurate packaged MOSFET model and a specially-designed test board for multi-point temperature measurement. Measured and modeled temperatures showed excellent agreement for various dissipated power levels. A simplified version of the packaged MOSFET was then used in a bridge configuration to build a thermal model of the whole converter. We then compared, temperature-wise, two PCB technologies, namely, standard FR4 versus multilayer board on metal substrate. Finally, we showed preliminary results of thermo-mechanical simulations aimed at evaluating interface stress/strain distributions. Further work is needed to tune and experimentally validate the
[1] Luo S. A review of distributed power systems part I: DC distributed power system. IEEE Aerospace and Electronic Systems Magazine. 20 Part 2 (2005) 5-16 [2] Lee FC, Barbosa P, Xu P,Zhang J, Yang B, Canales F. Topologies and Design Considerations for Distributed Power System Applications. Proc. IEEE. 89 (2001) 939-950. [3] Azzopardi S, Thébaud J-M, Woirgard E, Zardini C, Sablé P. Al/SiC baseplate hybrid power modules: evaluation of the thermome-chanical performances. Proc. IEEE Internat. Workshop on Integrated Power Packaging, IWIPP, (1998) 74-78. [4] Heat Transfer Module User’s Guide - COMSOL version 3.2., 2005. [5] Structural Mechanics Module User’s Guide COMSOL version 3.2., 2005. [6] Baliga BJ. Modern Power Devices. John Wiley & Sons, New York, 1987, pp. 327-329. [7] Hopkins T, Cognetti C, Tiziani R. Designing with Thermal Impedance. Proc. IV Semiconductor Thermal and Temperature Measurement Symp., SEMITHERM, 1988, pp. 55-61. [8] Mohan N, Undeland TM, Robbins WP. Power Electronics: Converters, Applications, and Design; 3rd Ed.. John Wiley & Sons, New York, 2003, pp. 739-741. [9] Zhu N, van Wyk JD, Liang ZX. Thermo-mechanical Stress Analysis for Planar Metallization i n Integrated Power Electronics Modules. Proc. IV Internat. Conference on Integrated Power Systems, CIPS, (2006) 111-116. [10] Sylvester MF, Banks DR, Le-Huu D, Kern RW. Thermal Cycling Effects on Eutectic Flip-Chip Die on Organic Packages. Proc. Internat. Conference on High-Density Interconnect and Systems Packaging, (2000) 438-443.
