Thermal instability effects in SiC Power MOSFETs - Semantic Scholar
Microelectronics Reliability 52 (2012) 2414–2419
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Thermal instability effects in SiC Power MOSFETs Alberto Castellazzi a,⇑, Tsuyoshi Funaki b, Tsunenobu Kimoto c, Takashi Hikihara d a
Power Electronics, Machines and Control Group, University of Nottingham, NG7 2RD Nottingham, UK Power Systems Laboratory, Osaka University, Suita, 565-0871 Osaka, Japan c Semiconductor Science & Engineering Laboratory, Kyoto University, Katsura, 615-8510 Kyoto, Japan d Power Conversion and System Control Laboratory, Kyoto University, Katsura, 615-8510 Kyoto, Japan b
a r t i c l e
i n f o
Article history: Received 3 June 2012 Accepted 22 June 2012 Available online 28 August 2012
a b s t r a c t Silicon carbide (SiC) power MOSFETs are characterised by potentially thermally unstable behaviour over a broad range of bias conditions. In the past, such behaviour has been shown for silicon (Si) MOSFETs to be related to a reduction of Safe Operating Area at higher drain–source bias voltages. For SiC MOSFETs no characterisation exists yet. This paper presents a thorough experimental investigation for devices of different voltage classes (600 and 1200 V) and different manufacturers, highlighting important differences in electro-thermal performance and failure mode as compared to Si devices. The goal is to derive information for design optimisation and reliable device development for a diverse range of target applications. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction SiC is expected to replace Si as the basis material for the production of electronic components, due to a number of superior electrothermal properties, which make it very attractive, particularly in electrical energy conversion applications. After many years of research on device physics and manufacturing, SiC power components are starting to be available as engineering samples or even commercial products. Following the development of JFETs and BJTs, more recently SiC power MOSFETs have been introduced and are rapidly advancing in technological maturity. Before SiC can be used extensively in application, robustness and reliability investigations are mandatory, with the aim of highlighting similarities and differences with well established Si technology and assess, both at device and system level, up to which point SiC devices can be viewed as a drop-in replacement of Si ones and where, conversely, the definition of bespoke solutions is required. This paper focuses specifically on the issues of electro-thermal instability, a well known and well investigated aspect of latest technology Si power MOSFETs and one which is known to significantly affect their robustness and reliability, particularly in low voltage applications; for SiC power MOSFETs no characterisation exists yet. Focussing on typical bias and operational conditions of linear switches or current limiters, the investigation is particularly relevant to the development of integrated switches (e.g. Smart Power) and to the understanding of device robustness under stressful abnormal events (e.g. short-circuit).
⇑ Corresponding author. E-mail address: [email protected] (A. Castellazzi). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.06.096
The paper will present first the steady-state characterisation of the devices, followed by a discussion of the known facts about electro-thermal instability in Si power MOSFETs. Subsequently, an extensive characterisation of different SiC device types in the transient domain is proposed, concluding with a discussion on the experimental findings. 2. SiC MOSFET steady-state characterisation Fig. 1a and b shows, respectively, the output and the transfer characteristics of a 600 V–10 A SiC power MOSFET, measured at three different temperature values; the transfer characteristics refers to a drain–source bias voltage VDS = 5 V. As is evident, the device exhibits positive drain current temperature coefficient, aT ¼ @l@TT , for a broad range of values of the gate–source voltage, VGS, and temperature, T: a positive aT is associated with thermally unstable behaviour, with the device drawing more and more current as its temperature increases for a fixed VGS. In the case of Si power MOSFETs, operation under thermally unstable bias conditions has been shown to be associated with a reduction of the Safe Operating Area (SOA) at higher drain–source voltage values, VDS, due to on-chip current crowding phenomena and hot-spot formation during pulsed operation [1,2]. Eventual device failure was attributed in other studies to the activation and subsequent thermal runaway of the parasitic BJT structure [2,3] or to the device becoming intrinsic [4]. Thermally stable or unstable behaviour is traditionally interpreted on the basis of two concurrent effects: the increase with temperature of the on-state resistance, RDS,ON, on the one hand, and the decrease with temperature of the threshold-voltage, Vth, on the other. Due to material physics (e.g. charge carriers mobility),
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Fig. 2. Illustration of Power MOSFET thermally stable and unstable operation depending on bias and load conditions [2].
Fig. 1. Measured output (a), and transfer characteristics (b), of new generation 600 V SiC Power MOSFETs. In these measurements, VDS = 5 V.
technological and manufacturing issues, the decrease of Vth is presently the dominating effect in SiC and a transfer characteristics with a broad range of positive aT is a common feature of all SiC power MOSFETs, independent of voltage class and manufacturer (see [5], for instance, for an example of a different voltage class and manufacturer). However, important differences exist in the physical electro-thermal parameters of Si and SiC, such as intrinsic carrier density, on-state base-emitter voltage and open-base gain of the intrinsic BJT, which motivates a bespoke investigation. In an attempt to deliver a representative and comprehensive analysis, devices with different voltage and current ratings, as well as of different manufacturers are taken into consideration: a 600 V–10 A and two 1200 V power MOSFETs, rated, respectively at 24 and 35 A, of different manufacturers. 3. Si power MOSFETs thermal instability Investigations of thermally unstable behaviour in Si power MOSFETs have pointed out that aT > 0 is only a necessary condition for instability [6]. If the parameter S ¼ V DS aT ðID Þ Z Th;JA ðtÞ is defined, where ZTh,JA(t) is the transistor chip thermal impedance, then the actual criticality is represented by S P 1, that is:
aT
1 V DS Z Th;JA ðtÞ
ð1Þ
For the sake of illustration Fig. 2, shows a plot of aT as a function of ID, for a given temperature value. For a given transistor chip (identified by a given value of thermal impedance ZTh,JA(t)), the condition in (1) identifies two regions of operation, which vary with the value of VDS: indeed, when the condition in (1) is satisfied, the device does exhibit thermally unstable behaviour within a range of values of ID (I1–I2), which becomes larger as VDS is increased; however, as ID increases beyond a given value (I2 in
Fig. 3. Current temperature coefficient for different temperature values (here, VDS = 5 V).
Fig. 2), the condition for thermal instability is removed and thermal stability can be re-gained. For even higher values of ID, aT becomes negative, removing the necessary condition for thermal instability. However, during pulsed operation, for a given VDS value, the device temperature changes with the current and if the temperature at some location within the device exceeds the technologically allowed maximum before ID = I2 the device fails: this was the crucial issue in low-voltage Si Power MOSFETs, where, to the authors’ knowledge, no recovery from thermally unstable transient operation has ever been documented. Fig. 3 shows the experimentally derived aT for the 600 V device type, still for VDS = 5 V. In this case, the ID range of positive aT is noticed to reduce considerably with increasing temperature and, still at a value as low as 400 K, aT becomes negative already when ID = 7.5 A. That suggests that, as opposed to Si MOSFETs, these devices may be capable, during pulsed operation, of entering a stable operational mode before approaching a thermally critical working condition. However, measuring aT at higher VDS values is impractical. Thus, to further investigate the issue, single-pulse tests were carried out, presented and discussed in the next section.
4. SiC MSOFET transient characterisation The test circuit schematic is shown in Fig. 4; the experimental test setup is a custom developed comprehensive solution enabling for the easy testing of a number of performance and robustness related issues in novel SiC power devices, ranging from thermal instabilities and short-circuit, to double-pulse testing and over-current
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Fig. 4. Schematic of the single-pulse test circuit used for device characterisation in the transient domain.
turn-off, and also enabling for unclamped inductive switching and avalanche ruggedness tests [8]. Here, the test parameters were the device case temperature, T, the value of VDS and the amplitude and pulse-width of VGS.
4.1. 600 V devices First, VGS = 19 V was applied: this corresponds to a bias condition on the transfer characteristics (Fig. 1b), where starting at ambient temperature, the device is expected to initially feature thermally unstable behaviour and then transition into a thermally stable one as the transient temperature increases. Fig. 5 shows the resulting current waveforms for a pulse width of 10 ls for three different values of VDS: 50, 150 and 270 V. Indeed, the results confirm that, just as in the case of Si devices, increasing VDS does result in the device entering a thermally unstable operational mode over a larger range of ID values; however, the ensuing transient temperature increase rapidly brings the device back into a thermally stable operational mode (i.e. negative temperature coefficient of the drain-current). It is worth noting that the VDS driven transition from thermally unstable to thermally stable regime of operation takes place already at very low values of VDS (here, around 60 V) in relation to the device rating and so, the device is exposed to thermally unstable bias conditions virtually all over its valid range of VDS bias. In a second test, VGS was lowered to 15 V, which is a bias point where still starting from an unstable operational condition, a higher current value must be reached before recovering thermal stability (Fig. 1b). So, the maximum applied VDS was 150 V in this case to avoid unnecessary device failures at this stage due to excessive power dissipation and overheating. The pulse-width was however varied up to much longer durations. Fig. 6 shows the resulting current waveform for this case: here, too, the device recovers ther-
Fig. 5. Experimental results for the short-circuit current when applying a fixed VGS = 19 V, for different values of Vin. The pulse-width in this case is 10 ls.
Fig. 6. Experimental results of the short-circuit current waveform when applying a fixed VGS = 15 V, for different values of Vin and pulse-widths.
mally stable operation for all tested values of VDS and is able to safely withstand longer pulses without damage. As is clear by comparing the relative current waveforms at VDS = 150 V, when VGS is lower, although the initial current level at turn-on is lower than in the case where VGS = 19 V (ca. 16 A as opposed to 20 A), it can be clearly seen that the device current needs to become significantly higher before a thermally stable behaviour can be reached, with higher stress and risk of localised high temperature increase and failure. In the results of both Figs. 5 and 6, the device case temperature is 300 K.
4.2. 1200 V devices The first set of tests was conducted on a 160 mX device, specified for 24 A current rating. The device was packaged in TO247 case. Here, in comparison to the tests above, the case temperature was also varied. Fig. 7 shows the measured current waveforms for different values of VDS at a fixed temperature T = 20 °C and fixed VGS = 16 V. The device exhibits a very similar behaviour as for the lower voltage class device and indeed, the time in thermal instability reduces to only a few ms and becomes negligible as the voltage increases. Moreover, here, the additional observation is made, that, starting from a given value of VDS (here 400 V), the peak current value at which inversion from thermally unstable to stable behaviour takes place decreases, in line with the expectations from Fig. 3, when it is considered that the increasing VDS corresponds to higher power dissipation within the chip and thus more pronounced temperature increase.
Fig. 7. Experimental results of the pulsed current waveform when applying a fixed VGS = 16 V, at a constant case temperature of 20 °C, for different values of VDS.
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Fig. 8. Experimental results of the single-pulse current waveform when applying a fixed VGS = 16 V, for different values of case-temperature T, for two different VDS values: VDS = 200 V (a) and VDS = 300 V (b).
Fig. 8 shows a second set of measurements where VDS and VGS are kept constant and the device case temperature, T, is varied between 20 and 90 °C: in Fig. 8a, VDS = 200 V; in Fig. 8b, it is 300 V. Here, the somewhat surprising observation is made, that increasing the case temperature from 20 to 90 °C has the effect of reducing the current levels at the beginning of the pulse; and that although the device is manifestly in a situation of positive aT, as evidenced by the subsequent current increase over time. Measurements were repeated at different VGS values and confirmed the same qualitative evolution: for illustration, Fig. 9 shows the results in the case of VGS = 18 V and VDS swept from 100 to 400 V. This seemingly contradictory behaviour is interpreted as a result of the fact that the total device on-state resistance is made up of two components: the channel resistance, RCH, and the drift region resistance, RDRIFT. The only component which contributes to thermally unstable behaviour is the channel resistance, which is affected by both the carriers’ mobility and the threshold voltage. On the other hand, RDRIFT is expected to increase both with applied VDS, due to a greater extension of the depletion layer, and with temperature. So, increasing the case temperature increases the total resistance value; however, during, the pulse, the decrease of RCH in the region of instability still causes the current to increase during the initial portion of the pulse. The hypothesis is made that this behaviour is not manifest in the output and transfer characteristics (see Fig. 1), due to the very low VDS value applied in those measurements, which probably makes RDRIFT negligible over the total resistance value. The increase of RDRIFT , and RCH with VDS also contribute to the behaviour observed in the results of Fig. 7, where the current levels decrease increasing VDS beyond a given value (e.g. from 300 to 400 V). To the authors’ knowledge, such behaviour is a connotative feature of SiC MOSFETs and has never been observed in Si MOSFETs: this is compatible with the fact that thermal instability
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Fig. 9. Experimental results of the single-pulse current waveform when applying a fixed VGS = 18 V, for different values of VDS, at two different case-temperatures: 20 °C (a), and 90 °C (b).
Fig. 10. Summary of the current overshoot and time to inversion for a given VGS value, as a function of VDS and for two different case temperature values: (a) T = 20 °C; (b) T = 90 °C.
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Fig. 11. Short-circuit current waveform of a 1200 V-rated SiC Power MOSFET when applying a VGS = 13.5 V at VDS = 150 V and T = 400 K.
Fig. 12. Short-circuit current waveform of a 1200 V-rated SiC 90 m SiC Power MOSFET for a case-temperature T = 60 °C, VDS = 200 V and different values of VGS.
Fig. 13. Short-circuit current waveform of the 1200 V-rated SiC 90 m SiC Power MOSFET biased at VDS = 150 V and VGS = 13.5 V for an initial base-plate temperature of 130 °C.
Finally Fig. 11, shows the evolution of the pulse current waveform for various VGS values at a fix VDS = 400 V: these results point out a clear reduction of tINV as higher VGS values are applied, so that the most critical condition for the formation of potentially destructive hot-spots is in the lower range of VGS values. Finally, tests were conducted on a 90 mX device, of a different manufacturer, still in TO247 package. Fig. 12 summarises the results for an average cse-temperature test value T = 60 °C, for VDS = 200 V and different values of VGS. Qualitatively, a very similar performance to the other device type is found; so, based on the observations above, a reliability critical bias condition was searched for and an example of failure under conditions of thermal instability was produced. Fig. 13 shows the measured short circuit current for the device biased at VDS = 150 V and VGS = 13.5 V for an initial base-plate temperature of 130 °C, which evidences a clear thermally unstable behaviour. Failure is detected upon attempted turn-off after only10 ls. 5. Discussion and conclusion
primarily affects low-voltage Si devices, where RDRIFT is a negligible portion of the total transistor on-state resistance value. A more precise understanding of these observations and validation of the advanced hypothesis would require more detailed knowledge of the device characteristics and is beyond the scope of this paper. Based on the above results, in an attempt to provide a meaningful characterisation of the transistor performance during pulsed transient operation, regarding in particular the inversion from thermally unstable to thermally stable behaviour, two parameters are introduced: – DIINV, which is the difference between the peak current value and that immediately after turn-on; – tINV, which is the time interval from turn-onto inversion from unstable to stable behaviour. Fig. 10a and b shows a plot of their values as a function of VDS, for VGS = 18 V and for two different temperature values, respectively. As can be seen, for a given value of VGS and T, increasing VDS rapidly reduces tINV; however, as T is increased, tINV for a given VDS value is higher and the DIINV value, which is lower at higher temperatures for relatively low VDS values, becomes higher as VDS is increased. This increases the risk that the device is affected by hot-spot formation and localised overheating. More test points are needed to extract an indicative relation of tINV as a function of temperature at a given set of VDS and VGS bias conditions and try to identify a worst-case condition in relation to the additional self-heating caused by DIINV; however, a clear trend can be already recognised in the results of Fig. 10.
In a first approximation, the thermal time constant of a semiconductor die can be described by:
s¼
q cs kTh
2
2
d ¼cd
ð2Þ
where q is the material density, cs is the specific heat, kTh is the thermal conductivity and d is the die thickness. In SiC, c is approximately a factor three smaller than in Si; so, for a given thickness and power dissipation the temperature will increase three times faster. The critical maximum temperature in SiC devices can also realistically be expected to be much higher than in Si devices of similar voltage ratings (latest generation low-voltage Si MOSFETs have such high doping levels that transient temperature values in excess of 700 K inside the crystal are possible). A rapidly increasing temperature has the positive effect of pushing the device back into thermally stable behaviour (the current range of positive aT decreases with temperature for a given set of bias conditions), but, on the other hand, it shortens the time before the onset of thermal instability during current regulation [6]. The key aspect to be investigated is the variation with temperature and bias conditions of aT against the device thermal impedance. The investigations of [6] further predicted the required time for the onset of thermally unstable behaviour when the device is operated with a constant current pulse under constant VDS bias conditions (i.e. VGS is not constant, but changed to give constant current) on the basis of its thermal impedance. Moreover, they incorporated very important considerations of device design aspects (e.g. channel length, chip aspect ratio) in the treatment of
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the phenomenon of thermal instability induced SOA reduction. Such considerations are further elaborated on in [7], which also includes considerations of chip geometry and its influence on thermal properties [7]. Further experiments are planned extending the range of study for VDS and VGS values and also including the study of constant power pulses applied (i.e. the MOSFET is inserted within a current regulation circuit which varies VGS to keep a constant ID for a given VDS value over a given length of time). The analysis of [6,7] will be used to inform and as a reference for subsequent investigations, to the aim of producing guideline for the production of robust and reliable SiC power MOSFETs that can be successfully used in the production of protective and regulation functionalities at key system locations (e.g. high-temperature Smart Power). References [1] Breglio G, Frisina F, Magri A, Spirito P. Electro-thermal instability in low voltage power MOS: experimental characterization. In: Proc ISPSD ’99, Toronto, Canada; 1999.
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[2] Castellazzi A, Kartal V, Kraus R, Seliger N, Honsberg-Riedl M, Schmitt-Landsiedel D. Hot-spot measurements and analysis of electro-thermal effects in lowvoltage Power MOSFETs. Microelectron Reliab 2003;43:1877–82. [3] Castellazzi A, Wachutka G. Low-voltage Power MOSFETs used as dissipative elements: electrothermal analysis and characterization. In: Proc PESC2006, Jeju, South Korea; 2006. [4] Denison M, Pfost M, Pieper K, Mtirkl S, Metzner D, Stecher M. lInfluence of inhomogeneous current distribution on the thermal SOA of integrated DMOS transistors. In: Proc ISPSD2004, Kitakyushu, Japan; June 2004. [5] http://www.cree.com/products/pdf/CPMF-1200S080B.pdf. [6] Spirito P, Breglio G, d’Alessandro V, Rinaldi N. Analytical model for the thermal instability of low-voltage PowerMOS and SOA in pulse operation. In: Proc ISPSD ’02, Santa Fe, Mexico; 2002. [7] Spirito P, Breglio G, d’Alessandro V, Rinaldi N. Thermal instabilities in high current power MOS devices: experimental evidence, electro-thermal simulations and analytical modelling. In: Proc MIEL 2002, Nis, Serbia; May 2002. [8] Fayyaz A, Castellazzi A. Performance and robustness testing of SiC power devices. In: Proc PEMD2012, Bristol, UK; March 2012.
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Thermal instability effects in SiC Power MOSFETs Alberto Castellazzi a,⇑, Tsuyoshi Funaki b, Tsunenobu Kimoto c, Takashi Hikihara d a
Power Electronics, Machines and Control Group, University of Nottingham, NG7 2RD Nottingham, UK Power Systems Laboratory, Osaka University, Suita, 565-0871 Osaka, Japan c Semiconductor Science & Engineering Laboratory, Kyoto University, Katsura, 615-8510 Kyoto, Japan d Power Conversion and System Control Laboratory, Kyoto University, Katsura, 615-8510 Kyoto, Japan b
a r t i c l e
i n f o
Article history: Received 3 June 2012 Accepted 22 June 2012 Available online 28 August 2012
a b s t r a c t Silicon carbide (SiC) power MOSFETs are characterised by potentially thermally unstable behaviour over a broad range of bias conditions. In the past, such behaviour has been shown for silicon (Si) MOSFETs to be related to a reduction of Safe Operating Area at higher drain–source bias voltages. For SiC MOSFETs no characterisation exists yet. This paper presents a thorough experimental investigation for devices of different voltage classes (600 and 1200 V) and different manufacturers, highlighting important differences in electro-thermal performance and failure mode as compared to Si devices. The goal is to derive information for design optimisation and reliable device development for a diverse range of target applications. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction SiC is expected to replace Si as the basis material for the production of electronic components, due to a number of superior electrothermal properties, which make it very attractive, particularly in electrical energy conversion applications. After many years of research on device physics and manufacturing, SiC power components are starting to be available as engineering samples or even commercial products. Following the development of JFETs and BJTs, more recently SiC power MOSFETs have been introduced and are rapidly advancing in technological maturity. Before SiC can be used extensively in application, robustness and reliability investigations are mandatory, with the aim of highlighting similarities and differences with well established Si technology and assess, both at device and system level, up to which point SiC devices can be viewed as a drop-in replacement of Si ones and where, conversely, the definition of bespoke solutions is required. This paper focuses specifically on the issues of electro-thermal instability, a well known and well investigated aspect of latest technology Si power MOSFETs and one which is known to significantly affect their robustness and reliability, particularly in low voltage applications; for SiC power MOSFETs no characterisation exists yet. Focussing on typical bias and operational conditions of linear switches or current limiters, the investigation is particularly relevant to the development of integrated switches (e.g. Smart Power) and to the understanding of device robustness under stressful abnormal events (e.g. short-circuit).
⇑ Corresponding author. E-mail address: [email protected] (A. Castellazzi). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.06.096
The paper will present first the steady-state characterisation of the devices, followed by a discussion of the known facts about electro-thermal instability in Si power MOSFETs. Subsequently, an extensive characterisation of different SiC device types in the transient domain is proposed, concluding with a discussion on the experimental findings. 2. SiC MOSFET steady-state characterisation Fig. 1a and b shows, respectively, the output and the transfer characteristics of a 600 V–10 A SiC power MOSFET, measured at three different temperature values; the transfer characteristics refers to a drain–source bias voltage VDS = 5 V. As is evident, the device exhibits positive drain current temperature coefficient, aT ¼ @l@TT , for a broad range of values of the gate–source voltage, VGS, and temperature, T: a positive aT is associated with thermally unstable behaviour, with the device drawing more and more current as its temperature increases for a fixed VGS. In the case of Si power MOSFETs, operation under thermally unstable bias conditions has been shown to be associated with a reduction of the Safe Operating Area (SOA) at higher drain–source voltage values, VDS, due to on-chip current crowding phenomena and hot-spot formation during pulsed operation [1,2]. Eventual device failure was attributed in other studies to the activation and subsequent thermal runaway of the parasitic BJT structure [2,3] or to the device becoming intrinsic [4]. Thermally stable or unstable behaviour is traditionally interpreted on the basis of two concurrent effects: the increase with temperature of the on-state resistance, RDS,ON, on the one hand, and the decrease with temperature of the threshold-voltage, Vth, on the other. Due to material physics (e.g. charge carriers mobility),
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Fig. 2. Illustration of Power MOSFET thermally stable and unstable operation depending on bias and load conditions [2].
Fig. 1. Measured output (a), and transfer characteristics (b), of new generation 600 V SiC Power MOSFETs. In these measurements, VDS = 5 V.
technological and manufacturing issues, the decrease of Vth is presently the dominating effect in SiC and a transfer characteristics with a broad range of positive aT is a common feature of all SiC power MOSFETs, independent of voltage class and manufacturer (see [5], for instance, for an example of a different voltage class and manufacturer). However, important differences exist in the physical electro-thermal parameters of Si and SiC, such as intrinsic carrier density, on-state base-emitter voltage and open-base gain of the intrinsic BJT, which motivates a bespoke investigation. In an attempt to deliver a representative and comprehensive analysis, devices with different voltage and current ratings, as well as of different manufacturers are taken into consideration: a 600 V–10 A and two 1200 V power MOSFETs, rated, respectively at 24 and 35 A, of different manufacturers. 3. Si power MOSFETs thermal instability Investigations of thermally unstable behaviour in Si power MOSFETs have pointed out that aT > 0 is only a necessary condition for instability [6]. If the parameter S ¼ V DS aT ðID Þ Z Th;JA ðtÞ is defined, where ZTh,JA(t) is the transistor chip thermal impedance, then the actual criticality is represented by S P 1, that is:
aT
1 V DS Z Th;JA ðtÞ
ð1Þ
For the sake of illustration Fig. 2, shows a plot of aT as a function of ID, for a given temperature value. For a given transistor chip (identified by a given value of thermal impedance ZTh,JA(t)), the condition in (1) identifies two regions of operation, which vary with the value of VDS: indeed, when the condition in (1) is satisfied, the device does exhibit thermally unstable behaviour within a range of values of ID (I1–I2), which becomes larger as VDS is increased; however, as ID increases beyond a given value (I2 in
Fig. 3. Current temperature coefficient for different temperature values (here, VDS = 5 V).
Fig. 2), the condition for thermal instability is removed and thermal stability can be re-gained. For even higher values of ID, aT becomes negative, removing the necessary condition for thermal instability. However, during pulsed operation, for a given VDS value, the device temperature changes with the current and if the temperature at some location within the device exceeds the technologically allowed maximum before ID = I2 the device fails: this was the crucial issue in low-voltage Si Power MOSFETs, where, to the authors’ knowledge, no recovery from thermally unstable transient operation has ever been documented. Fig. 3 shows the experimentally derived aT for the 600 V device type, still for VDS = 5 V. In this case, the ID range of positive aT is noticed to reduce considerably with increasing temperature and, still at a value as low as 400 K, aT becomes negative already when ID = 7.5 A. That suggests that, as opposed to Si MOSFETs, these devices may be capable, during pulsed operation, of entering a stable operational mode before approaching a thermally critical working condition. However, measuring aT at higher VDS values is impractical. Thus, to further investigate the issue, single-pulse tests were carried out, presented and discussed in the next section.
4. SiC MSOFET transient characterisation The test circuit schematic is shown in Fig. 4; the experimental test setup is a custom developed comprehensive solution enabling for the easy testing of a number of performance and robustness related issues in novel SiC power devices, ranging from thermal instabilities and short-circuit, to double-pulse testing and over-current
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Fig. 4. Schematic of the single-pulse test circuit used for device characterisation in the transient domain.
turn-off, and also enabling for unclamped inductive switching and avalanche ruggedness tests [8]. Here, the test parameters were the device case temperature, T, the value of VDS and the amplitude and pulse-width of VGS.
4.1. 600 V devices First, VGS = 19 V was applied: this corresponds to a bias condition on the transfer characteristics (Fig. 1b), where starting at ambient temperature, the device is expected to initially feature thermally unstable behaviour and then transition into a thermally stable one as the transient temperature increases. Fig. 5 shows the resulting current waveforms for a pulse width of 10 ls for three different values of VDS: 50, 150 and 270 V. Indeed, the results confirm that, just as in the case of Si devices, increasing VDS does result in the device entering a thermally unstable operational mode over a larger range of ID values; however, the ensuing transient temperature increase rapidly brings the device back into a thermally stable operational mode (i.e. negative temperature coefficient of the drain-current). It is worth noting that the VDS driven transition from thermally unstable to thermally stable regime of operation takes place already at very low values of VDS (here, around 60 V) in relation to the device rating and so, the device is exposed to thermally unstable bias conditions virtually all over its valid range of VDS bias. In a second test, VGS was lowered to 15 V, which is a bias point where still starting from an unstable operational condition, a higher current value must be reached before recovering thermal stability (Fig. 1b). So, the maximum applied VDS was 150 V in this case to avoid unnecessary device failures at this stage due to excessive power dissipation and overheating. The pulse-width was however varied up to much longer durations. Fig. 6 shows the resulting current waveform for this case: here, too, the device recovers ther-
Fig. 5. Experimental results for the short-circuit current when applying a fixed VGS = 19 V, for different values of Vin. The pulse-width in this case is 10 ls.
Fig. 6. Experimental results of the short-circuit current waveform when applying a fixed VGS = 15 V, for different values of Vin and pulse-widths.
mally stable operation for all tested values of VDS and is able to safely withstand longer pulses without damage. As is clear by comparing the relative current waveforms at VDS = 150 V, when VGS is lower, although the initial current level at turn-on is lower than in the case where VGS = 19 V (ca. 16 A as opposed to 20 A), it can be clearly seen that the device current needs to become significantly higher before a thermally stable behaviour can be reached, with higher stress and risk of localised high temperature increase and failure. In the results of both Figs. 5 and 6, the device case temperature is 300 K.
4.2. 1200 V devices The first set of tests was conducted on a 160 mX device, specified for 24 A current rating. The device was packaged in TO247 case. Here, in comparison to the tests above, the case temperature was also varied. Fig. 7 shows the measured current waveforms for different values of VDS at a fixed temperature T = 20 °C and fixed VGS = 16 V. The device exhibits a very similar behaviour as for the lower voltage class device and indeed, the time in thermal instability reduces to only a few ms and becomes negligible as the voltage increases. Moreover, here, the additional observation is made, that, starting from a given value of VDS (here 400 V), the peak current value at which inversion from thermally unstable to stable behaviour takes place decreases, in line with the expectations from Fig. 3, when it is considered that the increasing VDS corresponds to higher power dissipation within the chip and thus more pronounced temperature increase.
Fig. 7. Experimental results of the pulsed current waveform when applying a fixed VGS = 16 V, at a constant case temperature of 20 °C, for different values of VDS.
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Fig. 8. Experimental results of the single-pulse current waveform when applying a fixed VGS = 16 V, for different values of case-temperature T, for two different VDS values: VDS = 200 V (a) and VDS = 300 V (b).
Fig. 8 shows a second set of measurements where VDS and VGS are kept constant and the device case temperature, T, is varied between 20 and 90 °C: in Fig. 8a, VDS = 200 V; in Fig. 8b, it is 300 V. Here, the somewhat surprising observation is made, that increasing the case temperature from 20 to 90 °C has the effect of reducing the current levels at the beginning of the pulse; and that although the device is manifestly in a situation of positive aT, as evidenced by the subsequent current increase over time. Measurements were repeated at different VGS values and confirmed the same qualitative evolution: for illustration, Fig. 9 shows the results in the case of VGS = 18 V and VDS swept from 100 to 400 V. This seemingly contradictory behaviour is interpreted as a result of the fact that the total device on-state resistance is made up of two components: the channel resistance, RCH, and the drift region resistance, RDRIFT. The only component which contributes to thermally unstable behaviour is the channel resistance, which is affected by both the carriers’ mobility and the threshold voltage. On the other hand, RDRIFT is expected to increase both with applied VDS, due to a greater extension of the depletion layer, and with temperature. So, increasing the case temperature increases the total resistance value; however, during, the pulse, the decrease of RCH in the region of instability still causes the current to increase during the initial portion of the pulse. The hypothesis is made that this behaviour is not manifest in the output and transfer characteristics (see Fig. 1), due to the very low VDS value applied in those measurements, which probably makes RDRIFT negligible over the total resistance value. The increase of RDRIFT , and RCH with VDS also contribute to the behaviour observed in the results of Fig. 7, where the current levels decrease increasing VDS beyond a given value (e.g. from 300 to 400 V). To the authors’ knowledge, such behaviour is a connotative feature of SiC MOSFETs and has never been observed in Si MOSFETs: this is compatible with the fact that thermal instability
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Fig. 9. Experimental results of the single-pulse current waveform when applying a fixed VGS = 18 V, for different values of VDS, at two different case-temperatures: 20 °C (a), and 90 °C (b).
Fig. 10. Summary of the current overshoot and time to inversion for a given VGS value, as a function of VDS and for two different case temperature values: (a) T = 20 °C; (b) T = 90 °C.
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Fig. 11. Short-circuit current waveform of a 1200 V-rated SiC Power MOSFET when applying a VGS = 13.5 V at VDS = 150 V and T = 400 K.
Fig. 12. Short-circuit current waveform of a 1200 V-rated SiC 90 m SiC Power MOSFET for a case-temperature T = 60 °C, VDS = 200 V and different values of VGS.
Fig. 13. Short-circuit current waveform of the 1200 V-rated SiC 90 m SiC Power MOSFET biased at VDS = 150 V and VGS = 13.5 V for an initial base-plate temperature of 130 °C.
Finally Fig. 11, shows the evolution of the pulse current waveform for various VGS values at a fix VDS = 400 V: these results point out a clear reduction of tINV as higher VGS values are applied, so that the most critical condition for the formation of potentially destructive hot-spots is in the lower range of VGS values. Finally, tests were conducted on a 90 mX device, of a different manufacturer, still in TO247 package. Fig. 12 summarises the results for an average cse-temperature test value T = 60 °C, for VDS = 200 V and different values of VGS. Qualitatively, a very similar performance to the other device type is found; so, based on the observations above, a reliability critical bias condition was searched for and an example of failure under conditions of thermal instability was produced. Fig. 13 shows the measured short circuit current for the device biased at VDS = 150 V and VGS = 13.5 V for an initial base-plate temperature of 130 °C, which evidences a clear thermally unstable behaviour. Failure is detected upon attempted turn-off after only10 ls. 5. Discussion and conclusion
primarily affects low-voltage Si devices, where RDRIFT is a negligible portion of the total transistor on-state resistance value. A more precise understanding of these observations and validation of the advanced hypothesis would require more detailed knowledge of the device characteristics and is beyond the scope of this paper. Based on the above results, in an attempt to provide a meaningful characterisation of the transistor performance during pulsed transient operation, regarding in particular the inversion from thermally unstable to thermally stable behaviour, two parameters are introduced: – DIINV, which is the difference between the peak current value and that immediately after turn-on; – tINV, which is the time interval from turn-onto inversion from unstable to stable behaviour. Fig. 10a and b shows a plot of their values as a function of VDS, for VGS = 18 V and for two different temperature values, respectively. As can be seen, for a given value of VGS and T, increasing VDS rapidly reduces tINV; however, as T is increased, tINV for a given VDS value is higher and the DIINV value, which is lower at higher temperatures for relatively low VDS values, becomes higher as VDS is increased. This increases the risk that the device is affected by hot-spot formation and localised overheating. More test points are needed to extract an indicative relation of tINV as a function of temperature at a given set of VDS and VGS bias conditions and try to identify a worst-case condition in relation to the additional self-heating caused by DIINV; however, a clear trend can be already recognised in the results of Fig. 10.
In a first approximation, the thermal time constant of a semiconductor die can be described by:
s¼
q cs kTh
2
2
d ¼cd
ð2Þ
where q is the material density, cs is the specific heat, kTh is the thermal conductivity and d is the die thickness. In SiC, c is approximately a factor three smaller than in Si; so, for a given thickness and power dissipation the temperature will increase three times faster. The critical maximum temperature in SiC devices can also realistically be expected to be much higher than in Si devices of similar voltage ratings (latest generation low-voltage Si MOSFETs have such high doping levels that transient temperature values in excess of 700 K inside the crystal are possible). A rapidly increasing temperature has the positive effect of pushing the device back into thermally stable behaviour (the current range of positive aT decreases with temperature for a given set of bias conditions), but, on the other hand, it shortens the time before the onset of thermal instability during current regulation [6]. The key aspect to be investigated is the variation with temperature and bias conditions of aT against the device thermal impedance. The investigations of [6] further predicted the required time for the onset of thermally unstable behaviour when the device is operated with a constant current pulse under constant VDS bias conditions (i.e. VGS is not constant, but changed to give constant current) on the basis of its thermal impedance. Moreover, they incorporated very important considerations of device design aspects (e.g. channel length, chip aspect ratio) in the treatment of
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the phenomenon of thermal instability induced SOA reduction. Such considerations are further elaborated on in [7], which also includes considerations of chip geometry and its influence on thermal properties [7]. Further experiments are planned extending the range of study for VDS and VGS values and also including the study of constant power pulses applied (i.e. the MOSFET is inserted within a current regulation circuit which varies VGS to keep a constant ID for a given VDS value over a given length of time). The analysis of [6,7] will be used to inform and as a reference for subsequent investigations, to the aim of producing guideline for the production of robust and reliable SiC power MOSFETs that can be successfully used in the production of protective and regulation functionalities at key system locations (e.g. high-temperature Smart Power). References [1] Breglio G, Frisina F, Magri A, Spirito P. Electro-thermal instability in low voltage power MOS: experimental characterization. In: Proc ISPSD ’99, Toronto, Canada; 1999.
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[2] Castellazzi A, Kartal V, Kraus R, Seliger N, Honsberg-Riedl M, Schmitt-Landsiedel D. Hot-spot measurements and analysis of electro-thermal effects in lowvoltage Power MOSFETs. Microelectron Reliab 2003;43:1877–82. [3] Castellazzi A, Wachutka G. Low-voltage Power MOSFETs used as dissipative elements: electrothermal analysis and characterization. In: Proc PESC2006, Jeju, South Korea; 2006. [4] Denison M, Pfost M, Pieper K, Mtirkl S, Metzner D, Stecher M. lInfluence of inhomogeneous current distribution on the thermal SOA of integrated DMOS transistors. In: Proc ISPSD2004, Kitakyushu, Japan; June 2004. [5] http://www.cree.com/products/pdf/CPMF-1200S080B.pdf. [6] Spirito P, Breglio G, d’Alessandro V, Rinaldi N. Analytical model for the thermal instability of low-voltage PowerMOS and SOA in pulse operation. In: Proc ISPSD ’02, Santa Fe, Mexico; 2002. [7] Spirito P, Breglio G, d’Alessandro V, Rinaldi N. Thermal instabilities in high current power MOS devices: experimental evidence, electro-thermal simulations and analytical modelling. In: Proc MIEL 2002, Nis, Serbia; May 2002. [8] Fayyaz A, Castellazzi A. Performance and robustness testing of SiC power devices. In: Proc PEMD2012, Bristol, UK; March 2012.
