Three-Dimensional Flexible Complementary Metal- Oxide ...
SUPPORTING INFORMATION
Three-Dimensional Flexible Complementary MetalOxide-Semiconductor Logic Circuits Based on TwoLayer Stacks of Single-Walled Carbon Nanotube Networks Yudan Zhao1,2, Qunqing Li1,2*, Xiaoyang Xiao1,2, Guanhong Li1,2, Yuanhao Jin1,2, Kaili Jiang1,2, Jiaping Wang1,2, Shoushan Fan1,2 1
State Key Laboratory of Low-Dimensional Quantum Physics, Department of Physics and
Tsinghua-Foxconn Nanotechnology Research Center, Tsinghua University, Beijing 100084, China 2
Collaborative Innovation Center of Quantum Matter, Beijing 100084, China
*Corresponding author. E-mail address: [email protected];
Supporting information available: S1. The influence of silicon nitride deposition conditions on the properties of n-type CNTTFTs.
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S2. Pull-up network (PUN) and pull-down network (PDN) units in a CMOS circuit fabricated on upper and lower layers, separately. S3. Working principle of the 3D flexible CMOS inverter. S4. Hysteresis of p-type and n-type SWCNT TFTs. S5. Fatigue test of the n-type SWCNT TFT and the 3D CMOS inverter. S6. 7-stage oscillator’s output voltage oscillograms and 15-stage oscillator’s oscillogram under Vdd=15V. S7. Electrical performance of the n-type CNT-TFT during manufacturing processes.
1. The influence of silicon nitride deposition conditions on the properties of n-type CNTTFTs. Figure S1a shows that nitrogen gas and high temperature are the key factors for obtaining high-performance n-type devices. First, the role of nitrogen gas purging before the fabrication of the silicon nitride thin film was verified. We found that the as-grown p-type TFT device could only transfer to an ambipolar transistor if silicon nitride was directly deposited on the SWCNT thin films at a growth temperature of 300 °C without the purging of nitrogen gas in advance. Then, we found that we could only obtain an ambipolar transistor if the silicon nitride deposition temperature was set as low as 150 °C, even with nitrogen gas purging in advance. This indicates that both antecedent gas flow and high temperature are needed to remove oxygen and water vapor adsorbed on the surface of carbon nanotubes. If the channel was protected with photoresist when the silicon nitride thin film was deposited, we could also get an ambipolar transistor even under the conditions as that of Figure 2a. This proves that the photoresist can partly prevent the
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nitrogen flow from removing oxygen and water vapor, as well as hinder the field-effect doping induced by the positive fixed charges within silicon nitride.
Figure S1. (a) Transfer curves of n-type TFTs with various silicon nitride growth conditions. Red: silicon nitride grown at 300 °C with nitrogen flow, blue: 150 °C with nitrogen flow, green: 300 °C without nitrogen flow, yellow: 300 °C with nitrogen flow and photoresist protection, with TFT dimension of L=20 µm, W=100 µm. (b) Influence of the thickness of silicon nitride. The thickness of the silicon nitride thin film could also affect the properties of the n-type devices. Although devices covered with 20-nm silicon nitride fabricated at 300 °C and with antecedent nitrogen purging performed as n-type TFTs, we found that the on current is smaller and the off current is higher than that of devices covered with 50-nm silicon nitride, as shown in Figure S1b. This suggests that the positive fixed charge near the interface of silicon nitride and SWCNTs leads to the bending of the energy band, so it is understandable that the growth time of silicon nitride directly influences the amount of positive fixed charge near the interface. Thus, as the thickness of silicon nitride decreases, the on current decreases and the off current increases.
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2. Pull-up network (PUN) and pull-down network (PDN) units in a CMOS circuit fabricated on upper and lower layers, separately.
Figure S2. (a) CMOS logic circuit constituted by PUN and PDN. (b) PUN and PDN designed and manufactured respectively on the upper (p-type) and lower (n-type) layers and connected by one or several through-holes.
3. Working principle of 3D flexible CMOS inverters. There are two classical model to describe drain voltage versus current for field-effect transistors: one is the constant-mobility model, and the other is the velocity-saturation model.1
(1) (2)
Formulas (1) and (2) describe the TFT drain current (ID) in linear regions and saturation regions, respectively, using the constant-mobility model. Here, is a function of doping concentration and oxide thickness and is approximately equal to 1 with low doping concentration
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and thin oxide layer, while is the mobility under a low electric field (n=1 or 2 represents mobility under different conditions). From formula (2), we know that ID in the saturation region increases quadratically with gate voltage (VG). In this model, because the carrier velocity is independent of electric field intensity, the mobility is constant.
(3) (4)
However, when a horizontal electric field is high enough, mobility is no longer constant because of the scattering effect of carriers. Thus, the ID of TFTs should be described by the velocity-saturation model, which is defined by formula (3) for linear regions and formula (4) for saturation regions, where and are correction factors considering the velocity saturation level. We find that ID in the saturation region increases linearly with VG. From these two classical models, we can understand the working principle of 3D CMOS inverters using the output characteristic curves of n-type and p-type TFT devices. The typical output curves of p-type and n-type TFTs are plotted in Figure S3a. It is clear that p-type TFTs follow the constant-mobility model, while n-type TFTs follow the velocity-saturation model. In other words, when a horizontal electric field increases to a certain extent, n-type TFT carriers scatter more intensely and meet the requirements of the velocity-saturation model at first, while the p-type TFT still maintains its initial state. It should be emphasized that the critical horizontal electric field for velocity saturation depends on doping concentration and the vertical electric field, while for the inverter, the vertical electric field of the n-type TFT is even smaller because of its thicker dielectric layer. Therefore, the silicon nitride dielectric layer of the n-type TFT and the aluminum oxide above introduces a huge amount of positive fixed charges and results in heavy field-effect doping to its conductive channel, as well as inducing a small built-in vertical
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field. As a result, a relatively small electric field can lead to carrier scattering effects, which means a relative low drain voltage for an n-type TFTs may follow the velocity-saturation model, different from the ambient p-type TFTs.
Figure S3. Working principle of 3D flexible CMOS inverters. (a) Output curve shows ID and VG are a quadratic relationship for p-type TFTs (constant-mobility model), and linear relationship for n-type TFTs (velocity-saturation model). (b) Transform of the transfer curve of p-type TFT to a common coordinate system with n-type TFT. (c) Static work points extracted from output curves and (d) corresponding input-output and power curves, using same color dots. From the output characteristics of both n-type and p-type TFTs, we can analyze the static operating characteristics of the 3D CMOS inverter in detail. Considering a traditional CMOS
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inverter, including a couple of n-type and p-type TFTs, the intrinsic electrical parameters can be determined by the inverter’s parameters (for p-type TFTs, Vgs=Vin-Vdd, Vds=Vout-Vdd; for n-type TFTs, Vgs=Vin, Vds=Vout, and Idsn=-Idsp). Then, we draw the output curves in the same Vout-Idn graph, as Figure S3b illustrates.2 Curves with the same color represent the I-V characteristics of p-type and n-type TFTs under the same input voltage, and the abscissa of the intersection point is the output voltage under this input. Thus, we can obtain the direct current operating points of the inverter from this graph directly and easily. When the input voltage increases from zero to the switching threshold voltage (I-V curves change from red to green), the intersection points concentrate at “high” voltages with increasing current. Then, as the input voltage increases further (I-V curves change from blue to black), intersection points turn to “low” voltage rapidly with decreasing current, as shown in Figure S3c and S3d. This is because of the quadratic relationship output curves of the p-type TFTs; when the input changes from 0 to the switching threshold (“low” voltage), it still operates in the linear region. Meanwhile, the n-type TFTs saturation current is still very low at the same time because of the ID-VG linear relationship resulting from the velocity saturation effect. As a result, the intersection points of the two output curves are located near the supply voltage, with a very small static current. If the two output curves are totally symmetric like the p-type one, the ordinate of intersection points must be increased and lead to larger static current. Similarly, when the input voltage changes from the switching threshold to Vdd continuously (“high” voltage), the n-type TFT begins to work in its linear regions and the p-type TFT works in its saturation regions. Furthermore, because of the ptype TFT output curves’ quadratic relationship, the drain current in the saturation region decreases rapidly as the gate voltage increases. It can thus intersect with the n-type output curves at its linear region with “low” voltage as well as low static current. Therefore, the 3D flexible
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CMOS inverter possesses advantages including high gain, large noise margin, and low static power consumption because of the asymmetric quadratic and linear relationships of the output curves. Similar results for CMOS inverters with SWCNTs integrated with other semiconducting materials also showed high performance with such asymmetric quadratic and linear output relationships.3-5
4. Hysteresis of p-type and n-type SWCNT TFTs. Figure S4 shows the typical transfer characteristics curves of the n-type and p-type CNT-TFT measured at VD=1V where the magnitude of the hysteresis (evaluated at half of Ion) is measured to be 1.6V for n-type CNT-TFT and 5.3V for p-type CNT-TFT, when VG is swept from -5 V to 5V. It is obvious that hysteresis decreases after Si3N4 passivation layer deposition because of its high dielectric constants.6
Figure S4. Hysteresis of p-type and n-type SWCNT TFT. Typical transfer characteristic curve of (a) n-type CNT-TFT with hysteresis of 1.6V and (b) p-type CNT-TFT with hysteresis of 5.3V.
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5. Fatigue test of the n-type SWCNT TFT and the 3D CMOS inverter. To verify the 3D flexible CMOS circuits’ resistance to bending fatigue, we test the electrical performance of the n-type CNT-TFTs and inverters after various bending cycles as figure S5 shows. From which we can see the on and off current of n-type CNT-TFT had almost no change after over 1000 times bending cycles with bending radius less than 4mm. The only tiny change is threshold voltage moving towards positive voltage slightly. As a result, the switching threshold and gain of CMOS inverter change a little after bending but can hardly influence its performance, which still keeps in a high level. Thus the 3D CMOS circuits are proved to be suitable for flexible application further more.
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Figure S5. Fatigue test of the n-type SWCNT TFT and the 3D CMOS inverter. The change of the electrical performance after various bending cycles of (a) a typical n-type CNT-TFT and (b) a typical CMOS inverter. (c) Bending radius controlled by the automatic machine to as small as 4mm. (d) Inverter gain shows the device still works with high performance presenting high gain, accurate switching threshold located at the half of Vdd and large noise margin.
6. 7-stage oscillator’s output voltage oscillograms and 15-stage oscillator’s oscillogram under Vdd=15V. For supplementary of whole data points in figure 7e and 7f, we demonstrate 7-stage oscillator’s oscillograms and 15-stage oscillator’s oscillogram under Vdd=15V as figure S6 shows. The 7-stage oscillator has similar structure as 15-stage one and can also work in a wide supply voltage range.
Figure S6. (a) Optical microscope photo of the two nested 3D CMOS 7-stage ring oscillators. (b) Typical output voltage oscillograms of the 7-stage oscillator with various supply voltages. (c) Output voltage oscillogram of the 15-stage oscillator under Vdd=15V.
7. Electrical performance of the n-type CNT-TFT during manufacturing processes.
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We found that there has almost no change of the electrical performance for the n-type TFT after the fabrication of the upper CNT channel and S/D electrodes compared with its performance just after the deposition of 30-nm alumina using ALD, as shown in Figure S7. Thus we can conclude that the improvement of the n-type TFT is mainly because of the Al2O3 grown by ALD.
Figure S7. Transfer characteristic of typical n-type CNT-TFT before deposition of Al2O3 (hollow dots), after deposition of Al2O3 (filled dots) and after fabrication of upper p-type TFT (hollow diamonds) with channel length of 40µm (red) and 80µm (blue) respectively (width=100µm).
REFERENCES 1. Sze, S. M.; Kwok, K. N. Physics of Semiconductor Devices/Third Edition; John Wiley and Sons: New Jersey, 2006.
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2. Rabaey, J. M.; Chandrakasan, A.; Nikolic, B. Digital Integrated Circuits A Design Perspective/Second Edition; Prentice Hall: New Jersey, 2002. 3. Geier, M. L.; Prabhumirashi, P. L.; McMorrow, J. J.; Xu, W.; Seo, J. W.; Everaerts, K.; Kim, C. H.; Marks, T. J.; Hersam, M. C. Subnanowatt Carbon Nanotube Complementary Logic Enabled by Threshold Voltage Control. Nano Lett 2013, 13, 4810–4814. 4. Chen, H.; Cao, Y.; Zhang, J.; Zhou, C. Large-Scale Complementary Macroelectronics Using Hybrid Integration of Carbon Nanotubes and IGZO Thin-Film Transistors. Nat Commun 2014, 5, 4097–4108. 5. Kim, B.; Jang, S.; Geier, M. L.; Prabhumirashi, P. L.; Hersam, M. C.; Dodabalapur, A. HighSpeed, Inkjet-Printed Carbon Nanotube/Zinc Tin Oxide Hybrid Complementary Ring Oscillators. Nano Lett 2014, 14, 3683–3687. 6. Wang, C.; Zhang, J.; Ryu, K.; Badmaev, A.; De Arco, L. G.; Zhou, C. Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications. Nano Lett 2009, 9, 4285–4291.
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Three-Dimensional Flexible Complementary MetalOxide-Semiconductor Logic Circuits Based on TwoLayer Stacks of Single-Walled Carbon Nanotube Networks Yudan Zhao1,2, Qunqing Li1,2*, Xiaoyang Xiao1,2, Guanhong Li1,2, Yuanhao Jin1,2, Kaili Jiang1,2, Jiaping Wang1,2, Shoushan Fan1,2 1
State Key Laboratory of Low-Dimensional Quantum Physics, Department of Physics and
Tsinghua-Foxconn Nanotechnology Research Center, Tsinghua University, Beijing 100084, China 2
Collaborative Innovation Center of Quantum Matter, Beijing 100084, China
*Corresponding author. E-mail address: [email protected];
Supporting information available: S1. The influence of silicon nitride deposition conditions on the properties of n-type CNTTFTs.
1
S2. Pull-up network (PUN) and pull-down network (PDN) units in a CMOS circuit fabricated on upper and lower layers, separately. S3. Working principle of the 3D flexible CMOS inverter. S4. Hysteresis of p-type and n-type SWCNT TFTs. S5. Fatigue test of the n-type SWCNT TFT and the 3D CMOS inverter. S6. 7-stage oscillator’s output voltage oscillograms and 15-stage oscillator’s oscillogram under Vdd=15V. S7. Electrical performance of the n-type CNT-TFT during manufacturing processes.
1. The influence of silicon nitride deposition conditions on the properties of n-type CNTTFTs. Figure S1a shows that nitrogen gas and high temperature are the key factors for obtaining high-performance n-type devices. First, the role of nitrogen gas purging before the fabrication of the silicon nitride thin film was verified. We found that the as-grown p-type TFT device could only transfer to an ambipolar transistor if silicon nitride was directly deposited on the SWCNT thin films at a growth temperature of 300 °C without the purging of nitrogen gas in advance. Then, we found that we could only obtain an ambipolar transistor if the silicon nitride deposition temperature was set as low as 150 °C, even with nitrogen gas purging in advance. This indicates that both antecedent gas flow and high temperature are needed to remove oxygen and water vapor adsorbed on the surface of carbon nanotubes. If the channel was protected with photoresist when the silicon nitride thin film was deposited, we could also get an ambipolar transistor even under the conditions as that of Figure 2a. This proves that the photoresist can partly prevent the
2
nitrogen flow from removing oxygen and water vapor, as well as hinder the field-effect doping induced by the positive fixed charges within silicon nitride.
Figure S1. (a) Transfer curves of n-type TFTs with various silicon nitride growth conditions. Red: silicon nitride grown at 300 °C with nitrogen flow, blue: 150 °C with nitrogen flow, green: 300 °C without nitrogen flow, yellow: 300 °C with nitrogen flow and photoresist protection, with TFT dimension of L=20 µm, W=100 µm. (b) Influence of the thickness of silicon nitride. The thickness of the silicon nitride thin film could also affect the properties of the n-type devices. Although devices covered with 20-nm silicon nitride fabricated at 300 °C and with antecedent nitrogen purging performed as n-type TFTs, we found that the on current is smaller and the off current is higher than that of devices covered with 50-nm silicon nitride, as shown in Figure S1b. This suggests that the positive fixed charge near the interface of silicon nitride and SWCNTs leads to the bending of the energy band, so it is understandable that the growth time of silicon nitride directly influences the amount of positive fixed charge near the interface. Thus, as the thickness of silicon nitride decreases, the on current decreases and the off current increases.
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2. Pull-up network (PUN) and pull-down network (PDN) units in a CMOS circuit fabricated on upper and lower layers, separately.
Figure S2. (a) CMOS logic circuit constituted by PUN and PDN. (b) PUN and PDN designed and manufactured respectively on the upper (p-type) and lower (n-type) layers and connected by one or several through-holes.
3. Working principle of 3D flexible CMOS inverters. There are two classical model to describe drain voltage versus current for field-effect transistors: one is the constant-mobility model, and the other is the velocity-saturation model.1
(1) (2)
Formulas (1) and (2) describe the TFT drain current (ID) in linear regions and saturation regions, respectively, using the constant-mobility model. Here, is a function of doping concentration and oxide thickness and is approximately equal to 1 with low doping concentration
4
and thin oxide layer, while is the mobility under a low electric field (n=1 or 2 represents mobility under different conditions). From formula (2), we know that ID in the saturation region increases quadratically with gate voltage (VG). In this model, because the carrier velocity is independent of electric field intensity, the mobility is constant.
(3) (4)
However, when a horizontal electric field is high enough, mobility is no longer constant because of the scattering effect of carriers. Thus, the ID of TFTs should be described by the velocity-saturation model, which is defined by formula (3) for linear regions and formula (4) for saturation regions, where and are correction factors considering the velocity saturation level. We find that ID in the saturation region increases linearly with VG. From these two classical models, we can understand the working principle of 3D CMOS inverters using the output characteristic curves of n-type and p-type TFT devices. The typical output curves of p-type and n-type TFTs are plotted in Figure S3a. It is clear that p-type TFTs follow the constant-mobility model, while n-type TFTs follow the velocity-saturation model. In other words, when a horizontal electric field increases to a certain extent, n-type TFT carriers scatter more intensely and meet the requirements of the velocity-saturation model at first, while the p-type TFT still maintains its initial state. It should be emphasized that the critical horizontal electric field for velocity saturation depends on doping concentration and the vertical electric field, while for the inverter, the vertical electric field of the n-type TFT is even smaller because of its thicker dielectric layer. Therefore, the silicon nitride dielectric layer of the n-type TFT and the aluminum oxide above introduces a huge amount of positive fixed charges and results in heavy field-effect doping to its conductive channel, as well as inducing a small built-in vertical
5
field. As a result, a relatively small electric field can lead to carrier scattering effects, which means a relative low drain voltage for an n-type TFTs may follow the velocity-saturation model, different from the ambient p-type TFTs.
Figure S3. Working principle of 3D flexible CMOS inverters. (a) Output curve shows ID and VG are a quadratic relationship for p-type TFTs (constant-mobility model), and linear relationship for n-type TFTs (velocity-saturation model). (b) Transform of the transfer curve of p-type TFT to a common coordinate system with n-type TFT. (c) Static work points extracted from output curves and (d) corresponding input-output and power curves, using same color dots. From the output characteristics of both n-type and p-type TFTs, we can analyze the static operating characteristics of the 3D CMOS inverter in detail. Considering a traditional CMOS
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inverter, including a couple of n-type and p-type TFTs, the intrinsic electrical parameters can be determined by the inverter’s parameters (for p-type TFTs, Vgs=Vin-Vdd, Vds=Vout-Vdd; for n-type TFTs, Vgs=Vin, Vds=Vout, and Idsn=-Idsp). Then, we draw the output curves in the same Vout-Idn graph, as Figure S3b illustrates.2 Curves with the same color represent the I-V characteristics of p-type and n-type TFTs under the same input voltage, and the abscissa of the intersection point is the output voltage under this input. Thus, we can obtain the direct current operating points of the inverter from this graph directly and easily. When the input voltage increases from zero to the switching threshold voltage (I-V curves change from red to green), the intersection points concentrate at “high” voltages with increasing current. Then, as the input voltage increases further (I-V curves change from blue to black), intersection points turn to “low” voltage rapidly with decreasing current, as shown in Figure S3c and S3d. This is because of the quadratic relationship output curves of the p-type TFTs; when the input changes from 0 to the switching threshold (“low” voltage), it still operates in the linear region. Meanwhile, the n-type TFTs saturation current is still very low at the same time because of the ID-VG linear relationship resulting from the velocity saturation effect. As a result, the intersection points of the two output curves are located near the supply voltage, with a very small static current. If the two output curves are totally symmetric like the p-type one, the ordinate of intersection points must be increased and lead to larger static current. Similarly, when the input voltage changes from the switching threshold to Vdd continuously (“high” voltage), the n-type TFT begins to work in its linear regions and the p-type TFT works in its saturation regions. Furthermore, because of the ptype TFT output curves’ quadratic relationship, the drain current in the saturation region decreases rapidly as the gate voltage increases. It can thus intersect with the n-type output curves at its linear region with “low” voltage as well as low static current. Therefore, the 3D flexible
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CMOS inverter possesses advantages including high gain, large noise margin, and low static power consumption because of the asymmetric quadratic and linear relationships of the output curves. Similar results for CMOS inverters with SWCNTs integrated with other semiconducting materials also showed high performance with such asymmetric quadratic and linear output relationships.3-5
4. Hysteresis of p-type and n-type SWCNT TFTs. Figure S4 shows the typical transfer characteristics curves of the n-type and p-type CNT-TFT measured at VD=1V where the magnitude of the hysteresis (evaluated at half of Ion) is measured to be 1.6V for n-type CNT-TFT and 5.3V for p-type CNT-TFT, when VG is swept from -5 V to 5V. It is obvious that hysteresis decreases after Si3N4 passivation layer deposition because of its high dielectric constants.6
Figure S4. Hysteresis of p-type and n-type SWCNT TFT. Typical transfer characteristic curve of (a) n-type CNT-TFT with hysteresis of 1.6V and (b) p-type CNT-TFT with hysteresis of 5.3V.
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5. Fatigue test of the n-type SWCNT TFT and the 3D CMOS inverter. To verify the 3D flexible CMOS circuits’ resistance to bending fatigue, we test the electrical performance of the n-type CNT-TFTs and inverters after various bending cycles as figure S5 shows. From which we can see the on and off current of n-type CNT-TFT had almost no change after over 1000 times bending cycles with bending radius less than 4mm. The only tiny change is threshold voltage moving towards positive voltage slightly. As a result, the switching threshold and gain of CMOS inverter change a little after bending but can hardly influence its performance, which still keeps in a high level. Thus the 3D CMOS circuits are proved to be suitable for flexible application further more.
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Figure S5. Fatigue test of the n-type SWCNT TFT and the 3D CMOS inverter. The change of the electrical performance after various bending cycles of (a) a typical n-type CNT-TFT and (b) a typical CMOS inverter. (c) Bending radius controlled by the automatic machine to as small as 4mm. (d) Inverter gain shows the device still works with high performance presenting high gain, accurate switching threshold located at the half of Vdd and large noise margin.
6. 7-stage oscillator’s output voltage oscillograms and 15-stage oscillator’s oscillogram under Vdd=15V. For supplementary of whole data points in figure 7e and 7f, we demonstrate 7-stage oscillator’s oscillograms and 15-stage oscillator’s oscillogram under Vdd=15V as figure S6 shows. The 7-stage oscillator has similar structure as 15-stage one and can also work in a wide supply voltage range.
Figure S6. (a) Optical microscope photo of the two nested 3D CMOS 7-stage ring oscillators. (b) Typical output voltage oscillograms of the 7-stage oscillator with various supply voltages. (c) Output voltage oscillogram of the 15-stage oscillator under Vdd=15V.
7. Electrical performance of the n-type CNT-TFT during manufacturing processes.
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We found that there has almost no change of the electrical performance for the n-type TFT after the fabrication of the upper CNT channel and S/D electrodes compared with its performance just after the deposition of 30-nm alumina using ALD, as shown in Figure S7. Thus we can conclude that the improvement of the n-type TFT is mainly because of the Al2O3 grown by ALD.
Figure S7. Transfer characteristic of typical n-type CNT-TFT before deposition of Al2O3 (hollow dots), after deposition of Al2O3 (filled dots) and after fabrication of upper p-type TFT (hollow diamonds) with channel length of 40µm (red) and 80µm (blue) respectively (width=100µm).
REFERENCES 1. Sze, S. M.; Kwok, K. N. Physics of Semiconductor Devices/Third Edition; John Wiley and Sons: New Jersey, 2006.
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2. Rabaey, J. M.; Chandrakasan, A.; Nikolic, B. Digital Integrated Circuits A Design Perspective/Second Edition; Prentice Hall: New Jersey, 2002. 3. Geier, M. L.; Prabhumirashi, P. L.; McMorrow, J. J.; Xu, W.; Seo, J. W.; Everaerts, K.; Kim, C. H.; Marks, T. J.; Hersam, M. C. Subnanowatt Carbon Nanotube Complementary Logic Enabled by Threshold Voltage Control. Nano Lett 2013, 13, 4810–4814. 4. Chen, H.; Cao, Y.; Zhang, J.; Zhou, C. Large-Scale Complementary Macroelectronics Using Hybrid Integration of Carbon Nanotubes and IGZO Thin-Film Transistors. Nat Commun 2014, 5, 4097–4108. 5. Kim, B.; Jang, S.; Geier, M. L.; Prabhumirashi, P. L.; Hersam, M. C.; Dodabalapur, A. HighSpeed, Inkjet-Printed Carbon Nanotube/Zinc Tin Oxide Hybrid Complementary Ring Oscillators. Nano Lett 2014, 14, 3683–3687. 6. Wang, C.; Zhang, J.; Ryu, K.; Badmaev, A.; De Arco, L. G.; Zhou, C. Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications. Nano Lett 2009, 9, 4285–4291.
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