Transparent DFT: A Design for Testability and Test ... - IEEE Xplore
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TABLE I TRANSPARENT-SCAN MODES
Transparent DFT: A Design for Testability and Test Generation Approach for Synchronous Sequential Circuits Irith Pomeranz and Sudhakar M. Reddy Abstract—This paper describes a design for testability (DFT) approach for synchronous sequential circuits that combines scan with nonscan DFT in a transparent way. DFT control inputs and scan chain inputs are used as primary inputs of the circuit, and scan chain outputs are used as primary outputs of the circuit during test generation to eliminate the distinction between functional clock cycles and the various types of nonfunctional clock cycles. The result is 1) short test application times due to the nonscan DFT modes and the ability to use limited scan operations and 2) the ability to detect all the combinationally irredundant faults due to the scan mode. Index Terms—Design for testability (DFT), scan circuits, synchronous sequential circuits, test compaction, test generation.
I. I NTRODUCTION
Fig. 1.
Transparent-scan was proposed in [1] as an approach to test generation and test compaction for scan circuits. Under the transparent-scan approach, the distinction between scan clock cycles and clock cycles where the circuit operates in functional mode is eliminated. Test generation and test compaction procedures under this approach consider the scan chain input(s) and the scan select input as primary inputs of the circuit, and the scan chain output(s) as primary output(s) of the circuit. This provides complete flexibility in interleaving scan clock cycles and functional clock cycles during test generation. It results naturally in limited scan operations, where a scan chain is shifted a number of times smaller than its length [2]–[5]. Experimental results presented in [1] show that transparent scan reduces the test application time for benchmark circuits compared to the best known earlier scanbased procedures. The transparent-scan approach was found to be necessary in [6] in order to test critical paths in a microprocessor with partial scan. Although transparent scan reduces the test application time relative to other scan-based approaches, it still relies on scan operations for controlling and observing the circuit state. Scan operations, even limited ones, take several clock cycles. Design for testability (DFT) approaches for synchronous sequential circuits that do not use scan [7]–[11] have the potential of reducing the test application time to a larger extent than scan-based approaches. The goal of the DFT approach proposed in this work is to combine the advantages of transparent scan with those of nonscan DFT approaches under an approach we refer to as transparent DFT. To introduce the transparent-DFT approach, we first show in Table I the modes of operation of a standard scan flip-flop, and in Fig. 1 a conceptual description of such a flip-flop. We denote by yi the output (the present-state variable) of flip-flop i, and by Yi the input (the next state variable) of flip-flop i in the original circuit. We assume that the circuit has n flip-flops, numbered 1, 2, . . . , n. For simplicity we assume that all the flip-flops are included in a single scan chain. In the Manuscript received June 30, 2004; revised January 7, 2005 and March 27, 2005. The work of I. Pomeranz was supported in part by National Science Foundation (NSF) Grant CCR-0098091 and in part by Semiconductor Research Corporation (SRC) Grant 2001-TJ-950. The work of S. M. Reddy was supported in part by NSF Grant CCR-0097905 and in part by SRC Grant 2001-TJ-949. This paper was recommended by Associate Editor S. Hellebrand. I. Pomeranz is with the School of Electrical and Computer Engineering (ECE), Purdue University, West Lafayette, IN 47907 USA. S. M. Reddy is with the Electrical and Computer Engineering (ECE) Department, University of Iowa, Iowa City, IA 52242 USA. Digital Object Identifier 10.1109/TCAD.2005.855947
Transparent-scan flip-flop.
circuit with scan, the input of flip-flop i (1 ≤ i ≤ n) is denoted by Yˆi . For 1 < i ≤ n, Yˆi is a function of Yi , the scan select input s_sel, and yi−1 . For i = 1, yi−1 is replaced by the scan input s_inp. We also have a scan output s_out, which is connected to yn . For the transparent-DFT approach we introduce the following changes relative to scan. Instead of the scan select input s_sel, we have DFT select inputs denoted by d_sel1, d_sel2, . . . , d_selM . Each combination of values on d_sel1, d_sel2, . . . , d_selM corresponds to a different mode of operation. Possible modes of operation are as follows. The normal or functional mode of operation must always be possible, and we implement it corresponding to d_sel1 = d_sel2 = . . . = d_selM = 0. In this case, Yˆi = Yi for 1 ≤ i ≤ n. Scan should be included as a possible mode of operation since it guarantees the detection of every combinationally irredundant stuckat fault when full scan is used. We implement scan for d_sel1 = d_sel2 = . . . = d_selM − 1 = 0 and d_selM = 1. In this case, Yˆi = yi−1 for 1 < i ≤ n and Yˆ1 = s_inp, where s_inp is the scan input. We also have a scan output s_out connected to yn . Other combinations of d_sel1, d_sel2, . . . , d_selM can be used to set Yˆi = Yj , Yˆi = Y j , Yˆi = yj or Yˆi = y j , where 1 ≤ j ≤ n. For example, with Yˆi = yi for 1 ≤ i ≤ n we obtain the implementation of the DFT approach called Freeze [7], where the circuit is allowed to stay in the same state while primary input vectors are applied. With Yˆi = yi+1 for every 1 ≤ i < n and Yˆn = s_inp, we obtain a scan operation in the opposite direction to the one obtained when Yˆi = yi−1 for 1 < i ≤ n and Yˆ1 = s_inp. More complex functions of Yj and yj can also be used for Yˆi , 1 ≤ i ≤ n. This includes the option of using a different function for every flip-flop. It is also possible to incorporate scan chain modification techniques such as the one presented in [12] and [13]. Under this technique, XOR gates are included between scan flip-flops in order to achieve power reductions. In the context of transparent DFT, this technique can be used for reducing the test application time. We describe a particular transparent-DFT implementation with two control inputs d_sel1 and d_sel2 in Section II. We give an example of a test sequence under the transparent-DFT approach in Section III. We demonstrate the effectiveness of the transparent-DFT approach relative to the transparent-scan approach by performing two experiments outlined next. In both experiments, we assume the equivalent of full scan circuits, i.e., we assume that all the flip-flops are modified to incorporate DFT modes of operation.
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TABLE II TRANSPARENT-DFT MODES
For the first experiment, described in Section IV, we note that test generation under the transparent-DFT approach can be performed similar to the transparent-scan approach, by using a sequential test generation procedure [14] and [15] for the circuit with transparentDFT logic embedded in it. The sequential test generation procedure is allowed to use d_sel1, d_sel2, . . . , d_selM , and s_inp as primary inputs of the circuit. In addition, s_out is used as a primary output of the circuit. We apply the same sequential test generation procedure to two versions of a circuit, one for the transparent-scan approach, and one for the transparent-DFT approach. We compare the lengths of the test sequences generated, and the test generation times. The following points are important with respect to the use of a sequential test generation procedure. 1) The complexity of sequential test generation is reduced by the insertion of DFT logic under transparent scan as well as under transparent DFT. Specifically, the sequential test generation procedure can use the DFT modes of operation to justify states and propagate fault effects. 2) Sequential test generation is important for partial scan circuits, where combinational test generation is not an option. In the second experiment, described in Section V, we avoid sequential test generation altogether. We obtain a test sequence under the transparent-DFT approach by starting from a scan-based sequence (that can be computed by combinational test generation when the equivalent of full scan is used) and inserting the modes of operation allowed by the transparent-DFT approach into the sequence. We demonstrate that the modified sequence can be compacted beyond the compaction possible under transparent scan. In the comparison of test lengths, it is important to note that the length of a test sequence under the transparent scan or under the transparent-DFT approach is equal to the number of clock cycles required for applying the test sequence. In both cases, scan clock cycles can be longer than functional clock cycles, or they can be equal in length to allow at-speed test application. Our results indicate that test sequences under transparent DFT can be significantly shorter than test sequences under transparent scan. The transparent-DFT approach is also expected to facilitate diagnosis. For example, accurate diagnosis of defects in scan chains was found to be difficult with standard scan designs when multiple defects are present [16] and [17]. Incorporating a transparent-DFT mode to shift the scan chains in two directions is expected to aid accurate diagnosis of defects in scan chains.
II. T RANSPARENT -DFT C ONFIGURATION In this section, we describe a specific transparent-DFT configuration with two DFT select inputs, d_sel1 and d_sel2. In Table II, we show the modes supported by the proposed configuration. The first two modes follow the convention stated in Section I. When d_sel1 = d_sel2 = 0, we obtain the normal mode of operation where Yˆi = Yi for 1 ≤ i ≤ n. When d_sel1 = 0 and d_sel2 = 1, we obtain the scan mode of operation, where Yˆi = yi−1 for 1 < i ≤ n and Yˆ1 = s_inp.
Fig. 2. Transparent-DFT flip-flop.
For the next two modes we have a number of options as stated in Section I. We avoid the options where Yˆi is a function of Yj or yj for an arbitrary j in order to avoid the routing overhead from flip-flop j to flip-flop i. Instead, we use the following two options. When d_sel1 = 1 and d_sel2 = 0, we implement a mode similar to the normal mode except that the state is inverted before it is latched in the flip-flops. This is implemented by setting Yˆi = Y i for 1 ≤ i ≤ n. This mode allows us to obtain the most dramatic change possible in the circuit state (the state is inverted relative to the state that would have been obtained in normal mode). It is likely to allow us to reach a state that is different from the present-state, using a shorter sequence than would have been required if this mode had not been available. We refer to this mode as invert-normal mode. When d_sel1 = 1 and d_sel2 = 1, we implement a scan mode where the state is inverted while it is being shifted. This is implemented by setting Yˆi = y i−1 for 1 < i ≤ n and Yˆ1 = s_inp. Similar to the invert-normal mode, this mode also allows us to obtain large changes in the circuit state, especially during a limited scan operation. We refer to it as invert-scan mode. In Fig. 2, we show a conceptual implementation of a flip-flop for the transparent-DFT approach with the modes of Table II. The increase in flip-flop size and the additional control input compared to the transparent-scan flip-flop of Fig. 1 are overheads incurred by the transparent-DFT approach. In addition, there may be a delay overhead associated with the increase in the numbers of gate inputs compared to the transparent-scan approach. Specifically, the number of gate inputs per flip-flop increases from six under transparent scan to 16 under transparent DFT, indicating the increase in area per flip-flop. The number of gate inputs on a path from Yi to Yˆi increases from four under transparent scan to seven under transparent DFT, indicating the increase in delay per flip-flop.
III. T EST S EQUENCE U NDER T RANSPARENT -DFT In this section, we demonstrate the structure of a test sequence for a transparent-DFT circuit. We consider International Symposium on
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Fig. 3. ISCAS-89 benchmark circuit s27. TABLE III TEST SEQUENCE FOR s27
TABLE IV COMBINATIONAL TEST SET FOR s27
it, we obtain the next state 011. This becomes the present-state at time unit u = 3. At time unit u = 3 we have d_sel1d_sel2 = 01, corresponding to a scan operation. The present-state is 011 and the scan input is s_inp = 1. The next state is obtained by shifting 011 to the right, and placing s_inp = 1 in the leftmost position. The resulting next state is 101. This becomes the present-state at time unit u = 4. Note that the transparent-DFT sequence interleaves the various modes arbitrarily. This will allow us to obtain test sequences with reduced lengths. Circuits and Systems (ISCAS)-89 benchmark circuit s27 shown in Fig. 3. In the circuit with DFT, the flip-flops are replaced by flip-flops with the modes shown in Table II. The order of the flip-flops in the scan chain is 1, 2, 3 using the flip-flop numbers shown in Fig. 3. A test sequence for s27 with transparent DFT is shown in Table III. Under column u we show the time unit. Under column 1234 we show the values of the original primary inputs of the circuit, lines 1, 2, 3, and 4. Under column d_sel1, d_sel2 and s_inp, we show the values of the corresponding DFT inputs. Under column 567, we show the present-state of the circuit (5, 6, and 7 are the line numbers for the flip-flop outputs). Under column 26, we show the value of the primary output of the original circuit, line 26. Under column s_out, we show the value of the scan output. We consider the first four time units of the test sequence next. At time unit u = 0 we have d_sel1d_sel2 = 00, corresponding to normal operation. The present-state is xxx and the primary input vector is 0010. The resulting next state is 0x0. This becomes the present-state at time unit u = 1. At time unit u = 1 we have d_sel1d_sel2 = 11, corresponding to an invert-scan operation. The present-state is 0x0 and the scan input is s_inp = 0. The next state is obtained by shifting 0x0 to the right, placing s_inp = 0 in the leftmost position, and inverting every bit. The resulting next state is 11x. This becomes the present-state at time unit u = 2. At time unit u = 2 we have d_sel1d_sel2 = 10, corresponding to an invert-normal operation. The present-state is 11x and the primary input vector is 1111. This results in the next state 100. After inverting
IV. U SING S EQUENTIAL T EST G ENERATION In this section, we describe the use of sequential test generation for transparent-DFT circuits and present results for ISCAS-89 and International Test Conference (ITC)-99 benchmark circuits. We use two versions of every circuit, one for transparent scan where the flip-flops are modified as shown in Fig. 1, and one for transparent DFT where the flip-flops are modified as shown in Fig. 2. The list of target faults includes the combinationally detectable collapsed single stuck-at faults in the combinational logic of the original circuit. In both cases, the complexity of sequential test generation is reduced due to the extra inputs and outputs that provide extra controllability and observability relative to the non-DFT circuit. The test generation procedure we use is designed for synchronous sequential circuits without DFT, and it does not use any knowledge of the functions of s_sel (or d_sel1 and d_sel2), s_inp and s_out. As a result, it may not always be able to detect all the detectable faults. When this happens, we complete the test sequence by adding scanbased tests for the faults that remain undetected. The scan-based tests are computed by a combinational test generation procedure. The use of combinational tests to obtain transparent-scan and transparent-DFT sequences, introduced in [1] for transparent scan, is demonstrated next. A combinational test set for ISCAS-89 benchmark circuit s27 is shown in Table IV using the line numbers of Fig. 3. The combinational test set of Table IV can be translated into the transparent-scan sequence shown in Table V(a). Each combinational test requires three scan clock cycles for scanning in the state, one functional clock cycle for applying
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TABLE V SEQUENCES FOR s27 BASED ON A COMBINATIONAL TEST SET. (a) TRANSPARENT SCAN. (b) TRANSPARENT DFT
TABLE VI CIRCUIT PARAMETERS
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detectable faults. The fault efficiency after adding combinational tests is always 100%, and it is not reported in Table VII. The length of the test sequence generated is shown under subcolumn len. This includes the test length due to combinational tests added to achieve 100% fault efficiency. The test length after static test compaction using the procedures from [18] and [19], which are static test compaction procedures for synchronous sequential circuits, is shown under subcolumn comp. The normalized run time of test generation is shown under subcolumn n.time. The run time is normalized to the time it takes to fault simulate a combinational test set. Under column improv of Table VII, we show the percentage improvement in test length of transparent DFT relative to transparent-scan after static test compaction. From Table VII, it can be seen that the test sequence length is typically shorter under the transparent-DFT approach than under the transparent-scan approach. In many cases it is significantly shorter. In the few cases where the transparent-scan approach gives a more compact test sequence, this sequence can be used instead of the transparent-DFT sequence. Static test compaction reduces the test sequence lengths for both types of circuits. Overall, the compacted sequences under the transparent-DFT approach are significantly shorter than the transparent-scan sequences. V. U SING C OMBINATIONAL T EST G ENERATION
the primary input vector, and three scan out clock cycles (which can be overlapped with the scan in cycles of the next test). The x values are don’t-cares that can be specified arbitrarily. The transparent-scan sequence of Table V(a) can be translated into the transparent-DFT sequence of Table V(b). To perform the translation, we replace s_sel = 0 with d_sel1 = d_sel2 = 0 to implement the functional clock cycles, and we replace s_sel = 1 with d_sel1 = 0, d_sel2 = 1 to implement the scan clock cycles. The results of sequential test generation followed by static test compaction are shown in Tables VI and VII as follows. In Table VI, under column FF, we show the number of flip-flops, and under column flts, we show the number of collapsed single stuck-at faults in the circuits considered. Under column comb, we show the test length obtained if a compact combinational test set is translated into a transparent-scan sequence as demonstrated by Tables IV and V. This length is equal to the number of clock cycles required for applying the combinational test set. It is important in demonstrating the test length reductions possible with transparent scan and transparent DFT relative to combinational test generation with dynamic test compaction. In Table VII, under column transparent scan, we show the results of test generation and static test compaction for the transparent-scan circuit, and under column transparent DFT, we show the results for the transparent-DFT circuit. For every type of circuit we show the following information. The fault efficiency achieved before adding any combinational tests is shown under subcolumn f.e. The fault efficiency is the percentage of detected faults out of the combinationally
In this section, we describe an approach to test generation for transparent-DFT circuits that requires only combinational test generation for circuits where all the flip-flops have DFT modes. The proposed procedure starts from a combinational test set. This test set is translated into a test sequence under the transparent-DFT approach as demonstrated by Tables IV and V. The intermediate transparent-scan sequence obtained in this process can be compacted if desired before the transparent-DFT sequence is obtained. The translated test sequence T does not have any time units where d_sel1 = 1 since these modes of operation do not exist under the transparent-scan sequence from which T is obtained. Our goal is to introduce such clock cycles into the sequence. It will then be possible to further compact the sequence by applying static test compaction. We achieve the goal of introducing the unique transparent-DFT modes by modifying the values of d_sel1 and d_sel2 in clock cycles where d_sel1 = 0 using a procedure referred to as Procedure 1. Procedure 1 goes over the test sequence T one time unit at a time in a random order. For every time unit u where d_sel1 = 0 it attempts to set d_sel1 = 1 and d_sel2 = 0. The change is accepted if all the faults originally detected by T continue to be detected. Otherwise, Procedure 1 tries to set d_sel1 = 1 and d_sel2 = 1 at time unit u. If none of the pairs of values is accepted, the procedure restores the original values of d_sel1 and d_sel2 at time unit u. To check whether all the faults continue to be detected after changing the values of d_sel1 and d_sel2 at time unit u, only faults that were detected by T at time unit u or later need to be simulated. For every fault f , we denote by u_ det(f ) the first time unit where f is detected by T. After changing d_sel1 and d_sel2 at time unit u, we only simulate a fault f if u_ det(f ) ≥ u. Fault simulation can stop as soon as a fault is identified, which is not detected by the modified test sequence. To further speed up this process, we use the following techniques. We partition the faults in F with u_ det(f ) ≥ u into two subsets. The subset F1 includes the faults with detection time units that are close to u. The subset F2 includes the faults with detection time units that are further from u. We simulate the faults in F1 first, since they are more likely to be left undetected after d_sel1 and d_sel2 at time unit u are modified. Only if all the faults in F1 are detected, we also simulate the faults in F2 .
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TABLE VII RESULTS USING SEQUENTIAL TEST GENERATION
We associate with every fault f ∈ F1 (or F2 ) a variable fail(f ) that indicates whether or not the modification of T has failed (at any time unit) because f remained undetected. We first simulate the faults in Fi (i = 1, 2) with fail(f ) = 1, and then the faults with fail(f ) = 0. The assumption behind this order is that faults that have caused the modification of T to fail earlier are more likely to cause it to fail again. Within each group, we simulate the faults by order of increasing detection time unit u_ det(f ). This is based on the assumption that faults detected sooner after the modified time unit are more likely to remain undetected after the modification. Procedure 1 performs several iterations over the test sequence T until one of the following conditions are satisfied. 1) No modifications are possible in a complete pass over all the time units of T for which d_sel1 = 0. 2) The number of time units in which d_sel1 was changed to one reaches a preselected percentage P of the length of T. In our experiments we use P = 10% to limit the run time of Procedure 1. The result of Procedure 1 is a test sequence of the same length as T, containing the modes of operation unique to the transparentDFT approach in addition to functional and scan clock cycles. The resulting test sequence can be compacted using static test compaction procedures for synchronous sequential circuits. Our expectation is that static test compaction will be able to reduce the length of T after modification by Procedure 1 more than before the modification due to the use of the transparent-DFT modes of operation. We apply Procedure 1 to ISCAS-89 and ITC-99 benchmark circuits followed by static test compaction using the procedures from [18] and [19]. To demonstrate that this process results in highly compacted test sequences, we use for the initial transparent-scan sequences test sequences that have already been compacted in [1] under the transparentscan approach. The results are shown in Table VIII. After the circuit name we show the length of the initial test sequence T (before Procedure 1 is applied), the number of time units where d_sel1d_sel2 = 00 under T, and the number of time units where d_sel1d_sel2 = 01 under T. Under column modified we show the following information for the test sequence obtained after T is modified by Procedure 1. We show the number of time units where d_sel1d_sel2 = 00, 01, 10 and 11. Next, we show the run time of Procedure 1, normalized to the time it takes to fault simulate the initial test sequence T. We then show the test length after applying the static test compaction procedures from [18] and [19]. In the last column of Table VIII we show the percentage reduction in test length due to Procedure 1 and static test compaction.
TABLE VIII RESULTS OF TRANSPARENT-DFT MODE INSERTION
From Table VIII it can be seen that Procedure 1 is able to insert time units where the unique transparent-DFT modes are used. The target of 10% time units where d_sel1 = 1 is reached in all the cases. This results in test compaction beyond that achieved with transparent scan. Procedure 1, followed by static test compaction, can be applied iteratively to further compact the test sequence under the transparentDFT approach. We show the results of a second iteration in Table IX. Table IX is arranged similar to Table VIII, except that now, the initial test sequence T provided to Procedure 1 includes unique transparentDFT modes that were inserted by the first application of Procedure 1, and left after the first pass of static test compaction. Under column init len, we repeat the test length of the initial test sequence, before the first application of Procedure 1. Under column iteration1, we show the results obtained after applying Procedure 1 followed by static compaction for the first time. Under column iteration2, we show the results of the second iteration. The percentage improvement is given with respect to the initial test sequence, before the first iteration. VI. C ONCLUSION We described a DFT approach for synchronous sequential circuits referred to as transparent DFT. Under this approach, DFT control inputs and scan chain inputs are used as primary inputs of the circuit, and scan chain outputs are used as primary outputs of the circuit to eliminate the distinction between functional clock cycles and the various types of nonfunctional clock cycles during test. The specific transparent-DFT implementation we considered had three nonfunctional modes of operation: scan, invert-normal where the next state is complemented before it is latched, and invert-scan, where flip-flop
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TABLE IX RESULTS OF A SECOND ITERATION OF TRANSPARENT-DFT MODE INSERTION
states are inverted during scan shift. If only the scan mode is available, the approach is referred to as transparent scan. We applied a sequential test generation procedure to transparent-DFT and transparent-scan circuits. We also introduced a procedure that requires only combinational test generation. The results indicated the following advantages of the transparent-DFT approach. 1) It results in short test application times due to the nonscan DFT modes and the ability to use limited scan operations. 2) It is able to detect all the combinationally irredundant faults due to the scan mode. We only considered stuck-at faults in this work. To consider delay faults under transparent scan or transparent DFT, it is possible to use one of several approaches. 1) Methods developed for sequential circuits can be applied to a transparent-scan or transparent-DFT circuit. The sequential test generation procedure will be able to use the DFT modes of operation to facilitate test generation similar to stuck-at faults. 2) Transparent-scan and transparent DFT allow us to scan in the first pattern of a two-pattern test for delay faults similar to conventional scan. The second pattern can then be applied using any of the DFT modes available, or under the functional mode of operation. The final values latched in the flip-flops can then be scanned out. A combination of these approaches can be used as well. Both transparent scan and transparent DFT can be used in conjunction with test data compression methods. For example, it is possible to drive several scan chains from the same external scan input in order to support a large number of internal scan chains, or use a decompression circuit to drive the scan chains from a small number of external inputs.
R EFERENCES [1] I. Pomeranz and S. M. Reddy, “A new approach to test generation and test compaction for scan circuits,” in Proc. Design Automation and Test Europe, Munich, Germany, Mar. 2003, pp. 1000–1005. [2] S. P. Morley and R. A. Marlett, “Selected length partial scan: A method to reduce vector length,” in Proc. Int. Test Conf., Nashville, TN, 1991, pp. 385–392. [3] P.-C. Chen, B.-D. Liu, and J.-F. Wang, “Overall consideration of scan design and test generation,” in Proc. Int. Conf. Computer-Aided Design, Santa Clara, CA, 1992, pp. 9–12. [4] W.-J. Lai, C.-P. Kung, and C.-S. Lin, “Test time reduction in scan designed circuits,” in Proc. Eur. Design Automation Conf., Paris, France, 1993, pp. 489–493. [5] I. Pomeranz and S. M. Reddy, “On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations,” in Proc. Int. Test Conf., Baltimore, MD, 2001, pp. 211–220. [6] J. Grodstein, D. Bhavsar, V. Bettada, and R. Davies, “Automatic generation of critical-path tests for a partial-scan microprocessor,” in Proc. Int. Conf. Computer Design, San Jose, CA, Oct. 2003, pp. 180–186. [7] M. Abramovici, K. B. Rajan, and D. T. Miller, “FREEZE: A new approach for testing sequential circuits,” in Proc. Design Automation Conf., Anaheim, CA, Jun. 1992, pp. 22–25.
[8] D. K. Das and B. B. Bhattacharya, “Testable design of non-scan sequential circuits using extra logic,” in Proc. Asian Test Symp., Bangalore, India, Nov. 1995, pp. 176–182. [9] I. Pomeranz and S. M. Reddy, “On the use of fully specified initial states for testing of synchronous sequential circuits,” IEEE Trans. Comput., vol. 49, no. 2, pp. 175–182, Feb. 2000. [10] H. Fujiwara, “A new class of sequential circuits with combinational test generation complexity,” IEEE Trans. Comput., vol. 49, no. 9, pp. 895– 905, Sep. 2000. [11] M. Abramovici, X. Yu, and E. M. Rudnick, “Low-cost sequential ATPG with clock-control DFT,” in Proc. 39th Design Automation Conf., New Orleans, LA, Jun. 2002, pp. 243–248. [12] O. Sinanoglu and A. Orailoglu, “Aggressive test power reduction through test stimuli transformation,” in Proc. Int. Conf. Computer Design, San Jose, CA, Oct. 2003, pp. 542–547. [13] ——, “Modeling scan chain modifications for scan-in test power minimization,” in Proc. Int. Test Conf., Charlotte, NC, Sep. 2003, pp. 602–611. [14] T. Niermann and J. H. Patel, “HITEC: A test generation package for sequential circuits,” in Proc. Eur. Design Automation Conf., Amsterdam, The Netherlands, 1991, pp. 214–218. [15] X. Lin, I. Pomeranz, and S. M. Reddy, “Techniques for improving the efficiency of sequential circuit test generation,” in Proc. Int. Conf. ComputerAided Design, San Jose, CA, 1999, pp. 147–151. [16] R. Guo and S. Venkataraman, “A technique for fault diagnosis of defects in scan chains,” in Proc. Int. Test Conf., Baltimore, MD, Oct. 2002, pp. 268–277. [17] Y. Huang, W. T. Cheng, C. J. Hsieh, H. Y. Tseng, A. Huang, and Y. T. Hung, “Intermittent scan chain fault diagnosis based on signal probability analysis,” in Proc. Design Automation and Test Europe Conf., Paris, France, Feb. 2004, pp. 1072–1077. [18] I. Pomeranz and S. M. Reddy, “Vector restoration based static compaction of test sequences for synchronous sequential circuits,” in Proc. Int. Conf. Computer Design, Austin, TX, Oct. 1997, pp. 360–365. [19] ——, “On static compaction of test sequences for synchronous sequential circuits,” in Proc. 33rd Design Automation Conf., Las Vegas, NV, Jun. 1996, pp. 215–220.
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TABLE I TRANSPARENT-SCAN MODES
Transparent DFT: A Design for Testability and Test Generation Approach for Synchronous Sequential Circuits Irith Pomeranz and Sudhakar M. Reddy Abstract—This paper describes a design for testability (DFT) approach for synchronous sequential circuits that combines scan with nonscan DFT in a transparent way. DFT control inputs and scan chain inputs are used as primary inputs of the circuit, and scan chain outputs are used as primary outputs of the circuit during test generation to eliminate the distinction between functional clock cycles and the various types of nonfunctional clock cycles. The result is 1) short test application times due to the nonscan DFT modes and the ability to use limited scan operations and 2) the ability to detect all the combinationally irredundant faults due to the scan mode. Index Terms—Design for testability (DFT), scan circuits, synchronous sequential circuits, test compaction, test generation.
I. I NTRODUCTION
Fig. 1.
Transparent-scan was proposed in [1] as an approach to test generation and test compaction for scan circuits. Under the transparent-scan approach, the distinction between scan clock cycles and clock cycles where the circuit operates in functional mode is eliminated. Test generation and test compaction procedures under this approach consider the scan chain input(s) and the scan select input as primary inputs of the circuit, and the scan chain output(s) as primary output(s) of the circuit. This provides complete flexibility in interleaving scan clock cycles and functional clock cycles during test generation. It results naturally in limited scan operations, where a scan chain is shifted a number of times smaller than its length [2]–[5]. Experimental results presented in [1] show that transparent scan reduces the test application time for benchmark circuits compared to the best known earlier scanbased procedures. The transparent-scan approach was found to be necessary in [6] in order to test critical paths in a microprocessor with partial scan. Although transparent scan reduces the test application time relative to other scan-based approaches, it still relies on scan operations for controlling and observing the circuit state. Scan operations, even limited ones, take several clock cycles. Design for testability (DFT) approaches for synchronous sequential circuits that do not use scan [7]–[11] have the potential of reducing the test application time to a larger extent than scan-based approaches. The goal of the DFT approach proposed in this work is to combine the advantages of transparent scan with those of nonscan DFT approaches under an approach we refer to as transparent DFT. To introduce the transparent-DFT approach, we first show in Table I the modes of operation of a standard scan flip-flop, and in Fig. 1 a conceptual description of such a flip-flop. We denote by yi the output (the present-state variable) of flip-flop i, and by Yi the input (the next state variable) of flip-flop i in the original circuit. We assume that the circuit has n flip-flops, numbered 1, 2, . . . , n. For simplicity we assume that all the flip-flops are included in a single scan chain. In the Manuscript received June 30, 2004; revised January 7, 2005 and March 27, 2005. The work of I. Pomeranz was supported in part by National Science Foundation (NSF) Grant CCR-0098091 and in part by Semiconductor Research Corporation (SRC) Grant 2001-TJ-950. The work of S. M. Reddy was supported in part by NSF Grant CCR-0097905 and in part by SRC Grant 2001-TJ-949. This paper was recommended by Associate Editor S. Hellebrand. I. Pomeranz is with the School of Electrical and Computer Engineering (ECE), Purdue University, West Lafayette, IN 47907 USA. S. M. Reddy is with the Electrical and Computer Engineering (ECE) Department, University of Iowa, Iowa City, IA 52242 USA. Digital Object Identifier 10.1109/TCAD.2005.855947
Transparent-scan flip-flop.
circuit with scan, the input of flip-flop i (1 ≤ i ≤ n) is denoted by Yˆi . For 1 < i ≤ n, Yˆi is a function of Yi , the scan select input s_sel, and yi−1 . For i = 1, yi−1 is replaced by the scan input s_inp. We also have a scan output s_out, which is connected to yn . For the transparent-DFT approach we introduce the following changes relative to scan. Instead of the scan select input s_sel, we have DFT select inputs denoted by d_sel1, d_sel2, . . . , d_selM . Each combination of values on d_sel1, d_sel2, . . . , d_selM corresponds to a different mode of operation. Possible modes of operation are as follows. The normal or functional mode of operation must always be possible, and we implement it corresponding to d_sel1 = d_sel2 = . . . = d_selM = 0. In this case, Yˆi = Yi for 1 ≤ i ≤ n. Scan should be included as a possible mode of operation since it guarantees the detection of every combinationally irredundant stuckat fault when full scan is used. We implement scan for d_sel1 = d_sel2 = . . . = d_selM − 1 = 0 and d_selM = 1. In this case, Yˆi = yi−1 for 1 < i ≤ n and Yˆ1 = s_inp, where s_inp is the scan input. We also have a scan output s_out connected to yn . Other combinations of d_sel1, d_sel2, . . . , d_selM can be used to set Yˆi = Yj , Yˆi = Y j , Yˆi = yj or Yˆi = y j , where 1 ≤ j ≤ n. For example, with Yˆi = yi for 1 ≤ i ≤ n we obtain the implementation of the DFT approach called Freeze [7], where the circuit is allowed to stay in the same state while primary input vectors are applied. With Yˆi = yi+1 for every 1 ≤ i < n and Yˆn = s_inp, we obtain a scan operation in the opposite direction to the one obtained when Yˆi = yi−1 for 1 < i ≤ n and Yˆ1 = s_inp. More complex functions of Yj and yj can also be used for Yˆi , 1 ≤ i ≤ n. This includes the option of using a different function for every flip-flop. It is also possible to incorporate scan chain modification techniques such as the one presented in [12] and [13]. Under this technique, XOR gates are included between scan flip-flops in order to achieve power reductions. In the context of transparent DFT, this technique can be used for reducing the test application time. We describe a particular transparent-DFT implementation with two control inputs d_sel1 and d_sel2 in Section II. We give an example of a test sequence under the transparent-DFT approach in Section III. We demonstrate the effectiveness of the transparent-DFT approach relative to the transparent-scan approach by performing two experiments outlined next. In both experiments, we assume the equivalent of full scan circuits, i.e., we assume that all the flip-flops are modified to incorporate DFT modes of operation.
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TABLE II TRANSPARENT-DFT MODES
For the first experiment, described in Section IV, we note that test generation under the transparent-DFT approach can be performed similar to the transparent-scan approach, by using a sequential test generation procedure [14] and [15] for the circuit with transparentDFT logic embedded in it. The sequential test generation procedure is allowed to use d_sel1, d_sel2, . . . , d_selM , and s_inp as primary inputs of the circuit. In addition, s_out is used as a primary output of the circuit. We apply the same sequential test generation procedure to two versions of a circuit, one for the transparent-scan approach, and one for the transparent-DFT approach. We compare the lengths of the test sequences generated, and the test generation times. The following points are important with respect to the use of a sequential test generation procedure. 1) The complexity of sequential test generation is reduced by the insertion of DFT logic under transparent scan as well as under transparent DFT. Specifically, the sequential test generation procedure can use the DFT modes of operation to justify states and propagate fault effects. 2) Sequential test generation is important for partial scan circuits, where combinational test generation is not an option. In the second experiment, described in Section V, we avoid sequential test generation altogether. We obtain a test sequence under the transparent-DFT approach by starting from a scan-based sequence (that can be computed by combinational test generation when the equivalent of full scan is used) and inserting the modes of operation allowed by the transparent-DFT approach into the sequence. We demonstrate that the modified sequence can be compacted beyond the compaction possible under transparent scan. In the comparison of test lengths, it is important to note that the length of a test sequence under the transparent scan or under the transparent-DFT approach is equal to the number of clock cycles required for applying the test sequence. In both cases, scan clock cycles can be longer than functional clock cycles, or they can be equal in length to allow at-speed test application. Our results indicate that test sequences under transparent DFT can be significantly shorter than test sequences under transparent scan. The transparent-DFT approach is also expected to facilitate diagnosis. For example, accurate diagnosis of defects in scan chains was found to be difficult with standard scan designs when multiple defects are present [16] and [17]. Incorporating a transparent-DFT mode to shift the scan chains in two directions is expected to aid accurate diagnosis of defects in scan chains.
II. T RANSPARENT -DFT C ONFIGURATION In this section, we describe a specific transparent-DFT configuration with two DFT select inputs, d_sel1 and d_sel2. In Table II, we show the modes supported by the proposed configuration. The first two modes follow the convention stated in Section I. When d_sel1 = d_sel2 = 0, we obtain the normal mode of operation where Yˆi = Yi for 1 ≤ i ≤ n. When d_sel1 = 0 and d_sel2 = 1, we obtain the scan mode of operation, where Yˆi = yi−1 for 1 < i ≤ n and Yˆ1 = s_inp.
Fig. 2. Transparent-DFT flip-flop.
For the next two modes we have a number of options as stated in Section I. We avoid the options where Yˆi is a function of Yj or yj for an arbitrary j in order to avoid the routing overhead from flip-flop j to flip-flop i. Instead, we use the following two options. When d_sel1 = 1 and d_sel2 = 0, we implement a mode similar to the normal mode except that the state is inverted before it is latched in the flip-flops. This is implemented by setting Yˆi = Y i for 1 ≤ i ≤ n. This mode allows us to obtain the most dramatic change possible in the circuit state (the state is inverted relative to the state that would have been obtained in normal mode). It is likely to allow us to reach a state that is different from the present-state, using a shorter sequence than would have been required if this mode had not been available. We refer to this mode as invert-normal mode. When d_sel1 = 1 and d_sel2 = 1, we implement a scan mode where the state is inverted while it is being shifted. This is implemented by setting Yˆi = y i−1 for 1 < i ≤ n and Yˆ1 = s_inp. Similar to the invert-normal mode, this mode also allows us to obtain large changes in the circuit state, especially during a limited scan operation. We refer to it as invert-scan mode. In Fig. 2, we show a conceptual implementation of a flip-flop for the transparent-DFT approach with the modes of Table II. The increase in flip-flop size and the additional control input compared to the transparent-scan flip-flop of Fig. 1 are overheads incurred by the transparent-DFT approach. In addition, there may be a delay overhead associated with the increase in the numbers of gate inputs compared to the transparent-scan approach. Specifically, the number of gate inputs per flip-flop increases from six under transparent scan to 16 under transparent DFT, indicating the increase in area per flip-flop. The number of gate inputs on a path from Yi to Yˆi increases from four under transparent scan to seven under transparent DFT, indicating the increase in delay per flip-flop.
III. T EST S EQUENCE U NDER T RANSPARENT -DFT In this section, we demonstrate the structure of a test sequence for a transparent-DFT circuit. We consider International Symposium on
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Fig. 3. ISCAS-89 benchmark circuit s27. TABLE III TEST SEQUENCE FOR s27
TABLE IV COMBINATIONAL TEST SET FOR s27
it, we obtain the next state 011. This becomes the present-state at time unit u = 3. At time unit u = 3 we have d_sel1d_sel2 = 01, corresponding to a scan operation. The present-state is 011 and the scan input is s_inp = 1. The next state is obtained by shifting 011 to the right, and placing s_inp = 1 in the leftmost position. The resulting next state is 101. This becomes the present-state at time unit u = 4. Note that the transparent-DFT sequence interleaves the various modes arbitrarily. This will allow us to obtain test sequences with reduced lengths. Circuits and Systems (ISCAS)-89 benchmark circuit s27 shown in Fig. 3. In the circuit with DFT, the flip-flops are replaced by flip-flops with the modes shown in Table II. The order of the flip-flops in the scan chain is 1, 2, 3 using the flip-flop numbers shown in Fig. 3. A test sequence for s27 with transparent DFT is shown in Table III. Under column u we show the time unit. Under column 1234 we show the values of the original primary inputs of the circuit, lines 1, 2, 3, and 4. Under column d_sel1, d_sel2 and s_inp, we show the values of the corresponding DFT inputs. Under column 567, we show the present-state of the circuit (5, 6, and 7 are the line numbers for the flip-flop outputs). Under column 26, we show the value of the primary output of the original circuit, line 26. Under column s_out, we show the value of the scan output. We consider the first four time units of the test sequence next. At time unit u = 0 we have d_sel1d_sel2 = 00, corresponding to normal operation. The present-state is xxx and the primary input vector is 0010. The resulting next state is 0x0. This becomes the present-state at time unit u = 1. At time unit u = 1 we have d_sel1d_sel2 = 11, corresponding to an invert-scan operation. The present-state is 0x0 and the scan input is s_inp = 0. The next state is obtained by shifting 0x0 to the right, placing s_inp = 0 in the leftmost position, and inverting every bit. The resulting next state is 11x. This becomes the present-state at time unit u = 2. At time unit u = 2 we have d_sel1d_sel2 = 10, corresponding to an invert-normal operation. The present-state is 11x and the primary input vector is 1111. This results in the next state 100. After inverting
IV. U SING S EQUENTIAL T EST G ENERATION In this section, we describe the use of sequential test generation for transparent-DFT circuits and present results for ISCAS-89 and International Test Conference (ITC)-99 benchmark circuits. We use two versions of every circuit, one for transparent scan where the flip-flops are modified as shown in Fig. 1, and one for transparent DFT where the flip-flops are modified as shown in Fig. 2. The list of target faults includes the combinationally detectable collapsed single stuck-at faults in the combinational logic of the original circuit. In both cases, the complexity of sequential test generation is reduced due to the extra inputs and outputs that provide extra controllability and observability relative to the non-DFT circuit. The test generation procedure we use is designed for synchronous sequential circuits without DFT, and it does not use any knowledge of the functions of s_sel (or d_sel1 and d_sel2), s_inp and s_out. As a result, it may not always be able to detect all the detectable faults. When this happens, we complete the test sequence by adding scanbased tests for the faults that remain undetected. The scan-based tests are computed by a combinational test generation procedure. The use of combinational tests to obtain transparent-scan and transparent-DFT sequences, introduced in [1] for transparent scan, is demonstrated next. A combinational test set for ISCAS-89 benchmark circuit s27 is shown in Table IV using the line numbers of Fig. 3. The combinational test set of Table IV can be translated into the transparent-scan sequence shown in Table V(a). Each combinational test requires three scan clock cycles for scanning in the state, one functional clock cycle for applying
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TABLE V SEQUENCES FOR s27 BASED ON A COMBINATIONAL TEST SET. (a) TRANSPARENT SCAN. (b) TRANSPARENT DFT
TABLE VI CIRCUIT PARAMETERS
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detectable faults. The fault efficiency after adding combinational tests is always 100%, and it is not reported in Table VII. The length of the test sequence generated is shown under subcolumn len. This includes the test length due to combinational tests added to achieve 100% fault efficiency. The test length after static test compaction using the procedures from [18] and [19], which are static test compaction procedures for synchronous sequential circuits, is shown under subcolumn comp. The normalized run time of test generation is shown under subcolumn n.time. The run time is normalized to the time it takes to fault simulate a combinational test set. Under column improv of Table VII, we show the percentage improvement in test length of transparent DFT relative to transparent-scan after static test compaction. From Table VII, it can be seen that the test sequence length is typically shorter under the transparent-DFT approach than under the transparent-scan approach. In many cases it is significantly shorter. In the few cases where the transparent-scan approach gives a more compact test sequence, this sequence can be used instead of the transparent-DFT sequence. Static test compaction reduces the test sequence lengths for both types of circuits. Overall, the compacted sequences under the transparent-DFT approach are significantly shorter than the transparent-scan sequences. V. U SING C OMBINATIONAL T EST G ENERATION
the primary input vector, and three scan out clock cycles (which can be overlapped with the scan in cycles of the next test). The x values are don’t-cares that can be specified arbitrarily. The transparent-scan sequence of Table V(a) can be translated into the transparent-DFT sequence of Table V(b). To perform the translation, we replace s_sel = 0 with d_sel1 = d_sel2 = 0 to implement the functional clock cycles, and we replace s_sel = 1 with d_sel1 = 0, d_sel2 = 1 to implement the scan clock cycles. The results of sequential test generation followed by static test compaction are shown in Tables VI and VII as follows. In Table VI, under column FF, we show the number of flip-flops, and under column flts, we show the number of collapsed single stuck-at faults in the circuits considered. Under column comb, we show the test length obtained if a compact combinational test set is translated into a transparent-scan sequence as demonstrated by Tables IV and V. This length is equal to the number of clock cycles required for applying the combinational test set. It is important in demonstrating the test length reductions possible with transparent scan and transparent DFT relative to combinational test generation with dynamic test compaction. In Table VII, under column transparent scan, we show the results of test generation and static test compaction for the transparent-scan circuit, and under column transparent DFT, we show the results for the transparent-DFT circuit. For every type of circuit we show the following information. The fault efficiency achieved before adding any combinational tests is shown under subcolumn f.e. The fault efficiency is the percentage of detected faults out of the combinationally
In this section, we describe an approach to test generation for transparent-DFT circuits that requires only combinational test generation for circuits where all the flip-flops have DFT modes. The proposed procedure starts from a combinational test set. This test set is translated into a test sequence under the transparent-DFT approach as demonstrated by Tables IV and V. The intermediate transparent-scan sequence obtained in this process can be compacted if desired before the transparent-DFT sequence is obtained. The translated test sequence T does not have any time units where d_sel1 = 1 since these modes of operation do not exist under the transparent-scan sequence from which T is obtained. Our goal is to introduce such clock cycles into the sequence. It will then be possible to further compact the sequence by applying static test compaction. We achieve the goal of introducing the unique transparent-DFT modes by modifying the values of d_sel1 and d_sel2 in clock cycles where d_sel1 = 0 using a procedure referred to as Procedure 1. Procedure 1 goes over the test sequence T one time unit at a time in a random order. For every time unit u where d_sel1 = 0 it attempts to set d_sel1 = 1 and d_sel2 = 0. The change is accepted if all the faults originally detected by T continue to be detected. Otherwise, Procedure 1 tries to set d_sel1 = 1 and d_sel2 = 1 at time unit u. If none of the pairs of values is accepted, the procedure restores the original values of d_sel1 and d_sel2 at time unit u. To check whether all the faults continue to be detected after changing the values of d_sel1 and d_sel2 at time unit u, only faults that were detected by T at time unit u or later need to be simulated. For every fault f , we denote by u_ det(f ) the first time unit where f is detected by T. After changing d_sel1 and d_sel2 at time unit u, we only simulate a fault f if u_ det(f ) ≥ u. Fault simulation can stop as soon as a fault is identified, which is not detected by the modified test sequence. To further speed up this process, we use the following techniques. We partition the faults in F with u_ det(f ) ≥ u into two subsets. The subset F1 includes the faults with detection time units that are close to u. The subset F2 includes the faults with detection time units that are further from u. We simulate the faults in F1 first, since they are more likely to be left undetected after d_sel1 and d_sel2 at time unit u are modified. Only if all the faults in F1 are detected, we also simulate the faults in F2 .
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TABLE VII RESULTS USING SEQUENTIAL TEST GENERATION
We associate with every fault f ∈ F1 (or F2 ) a variable fail(f ) that indicates whether or not the modification of T has failed (at any time unit) because f remained undetected. We first simulate the faults in Fi (i = 1, 2) with fail(f ) = 1, and then the faults with fail(f ) = 0. The assumption behind this order is that faults that have caused the modification of T to fail earlier are more likely to cause it to fail again. Within each group, we simulate the faults by order of increasing detection time unit u_ det(f ). This is based on the assumption that faults detected sooner after the modified time unit are more likely to remain undetected after the modification. Procedure 1 performs several iterations over the test sequence T until one of the following conditions are satisfied. 1) No modifications are possible in a complete pass over all the time units of T for which d_sel1 = 0. 2) The number of time units in which d_sel1 was changed to one reaches a preselected percentage P of the length of T. In our experiments we use P = 10% to limit the run time of Procedure 1. The result of Procedure 1 is a test sequence of the same length as T, containing the modes of operation unique to the transparentDFT approach in addition to functional and scan clock cycles. The resulting test sequence can be compacted using static test compaction procedures for synchronous sequential circuits. Our expectation is that static test compaction will be able to reduce the length of T after modification by Procedure 1 more than before the modification due to the use of the transparent-DFT modes of operation. We apply Procedure 1 to ISCAS-89 and ITC-99 benchmark circuits followed by static test compaction using the procedures from [18] and [19]. To demonstrate that this process results in highly compacted test sequences, we use for the initial transparent-scan sequences test sequences that have already been compacted in [1] under the transparentscan approach. The results are shown in Table VIII. After the circuit name we show the length of the initial test sequence T (before Procedure 1 is applied), the number of time units where d_sel1d_sel2 = 00 under T, and the number of time units where d_sel1d_sel2 = 01 under T. Under column modified we show the following information for the test sequence obtained after T is modified by Procedure 1. We show the number of time units where d_sel1d_sel2 = 00, 01, 10 and 11. Next, we show the run time of Procedure 1, normalized to the time it takes to fault simulate the initial test sequence T. We then show the test length after applying the static test compaction procedures from [18] and [19]. In the last column of Table VIII we show the percentage reduction in test length due to Procedure 1 and static test compaction.
TABLE VIII RESULTS OF TRANSPARENT-DFT MODE INSERTION
From Table VIII it can be seen that Procedure 1 is able to insert time units where the unique transparent-DFT modes are used. The target of 10% time units where d_sel1 = 1 is reached in all the cases. This results in test compaction beyond that achieved with transparent scan. Procedure 1, followed by static test compaction, can be applied iteratively to further compact the test sequence under the transparentDFT approach. We show the results of a second iteration in Table IX. Table IX is arranged similar to Table VIII, except that now, the initial test sequence T provided to Procedure 1 includes unique transparentDFT modes that were inserted by the first application of Procedure 1, and left after the first pass of static test compaction. Under column init len, we repeat the test length of the initial test sequence, before the first application of Procedure 1. Under column iteration1, we show the results obtained after applying Procedure 1 followed by static compaction for the first time. Under column iteration2, we show the results of the second iteration. The percentage improvement is given with respect to the initial test sequence, before the first iteration. VI. C ONCLUSION We described a DFT approach for synchronous sequential circuits referred to as transparent DFT. Under this approach, DFT control inputs and scan chain inputs are used as primary inputs of the circuit, and scan chain outputs are used as primary outputs of the circuit to eliminate the distinction between functional clock cycles and the various types of nonfunctional clock cycles during test. The specific transparent-DFT implementation we considered had three nonfunctional modes of operation: scan, invert-normal where the next state is complemented before it is latched, and invert-scan, where flip-flop
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TABLE IX RESULTS OF A SECOND ITERATION OF TRANSPARENT-DFT MODE INSERTION
states are inverted during scan shift. If only the scan mode is available, the approach is referred to as transparent scan. We applied a sequential test generation procedure to transparent-DFT and transparent-scan circuits. We also introduced a procedure that requires only combinational test generation. The results indicated the following advantages of the transparent-DFT approach. 1) It results in short test application times due to the nonscan DFT modes and the ability to use limited scan operations. 2) It is able to detect all the combinationally irredundant faults due to the scan mode. We only considered stuck-at faults in this work. To consider delay faults under transparent scan or transparent DFT, it is possible to use one of several approaches. 1) Methods developed for sequential circuits can be applied to a transparent-scan or transparent-DFT circuit. The sequential test generation procedure will be able to use the DFT modes of operation to facilitate test generation similar to stuck-at faults. 2) Transparent-scan and transparent DFT allow us to scan in the first pattern of a two-pattern test for delay faults similar to conventional scan. The second pattern can then be applied using any of the DFT modes available, or under the functional mode of operation. The final values latched in the flip-flops can then be scanned out. A combination of these approaches can be used as well. Both transparent scan and transparent DFT can be used in conjunction with test data compression methods. For example, it is possible to drive several scan chains from the same external scan input in order to support a large number of internal scan chains, or use a decompression circuit to drive the scan chains from a small number of external inputs.
R EFERENCES [1] I. Pomeranz and S. M. Reddy, “A new approach to test generation and test compaction for scan circuits,” in Proc. Design Automation and Test Europe, Munich, Germany, Mar. 2003, pp. 1000–1005. [2] S. P. Morley and R. A. Marlett, “Selected length partial scan: A method to reduce vector length,” in Proc. Int. Test Conf., Nashville, TN, 1991, pp. 385–392. [3] P.-C. Chen, B.-D. Liu, and J.-F. Wang, “Overall consideration of scan design and test generation,” in Proc. Int. Conf. Computer-Aided Design, Santa Clara, CA, 1992, pp. 9–12. [4] W.-J. Lai, C.-P. Kung, and C.-S. Lin, “Test time reduction in scan designed circuits,” in Proc. Eur. Design Automation Conf., Paris, France, 1993, pp. 489–493. [5] I. Pomeranz and S. M. Reddy, “On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations,” in Proc. Int. Test Conf., Baltimore, MD, 2001, pp. 211–220. [6] J. Grodstein, D. Bhavsar, V. Bettada, and R. Davies, “Automatic generation of critical-path tests for a partial-scan microprocessor,” in Proc. Int. Conf. Computer Design, San Jose, CA, Oct. 2003, pp. 180–186. [7] M. Abramovici, K. B. Rajan, and D. T. Miller, “FREEZE: A new approach for testing sequential circuits,” in Proc. Design Automation Conf., Anaheim, CA, Jun. 1992, pp. 22–25.
[8] D. K. Das and B. B. Bhattacharya, “Testable design of non-scan sequential circuits using extra logic,” in Proc. Asian Test Symp., Bangalore, India, Nov. 1995, pp. 176–182. [9] I. Pomeranz and S. M. Reddy, “On the use of fully specified initial states for testing of synchronous sequential circuits,” IEEE Trans. Comput., vol. 49, no. 2, pp. 175–182, Feb. 2000. [10] H. Fujiwara, “A new class of sequential circuits with combinational test generation complexity,” IEEE Trans. Comput., vol. 49, no. 9, pp. 895– 905, Sep. 2000. [11] M. Abramovici, X. Yu, and E. M. Rudnick, “Low-cost sequential ATPG with clock-control DFT,” in Proc. 39th Design Automation Conf., New Orleans, LA, Jun. 2002, pp. 243–248. [12] O. Sinanoglu and A. Orailoglu, “Aggressive test power reduction through test stimuli transformation,” in Proc. Int. Conf. Computer Design, San Jose, CA, Oct. 2003, pp. 542–547. [13] ——, “Modeling scan chain modifications for scan-in test power minimization,” in Proc. Int. Test Conf., Charlotte, NC, Sep. 2003, pp. 602–611. [14] T. Niermann and J. H. Patel, “HITEC: A test generation package for sequential circuits,” in Proc. Eur. Design Automation Conf., Amsterdam, The Netherlands, 1991, pp. 214–218. [15] X. Lin, I. Pomeranz, and S. M. Reddy, “Techniques for improving the efficiency of sequential circuit test generation,” in Proc. Int. Conf. ComputerAided Design, San Jose, CA, 1999, pp. 147–151. [16] R. Guo and S. Venkataraman, “A technique for fault diagnosis of defects in scan chains,” in Proc. Int. Test Conf., Baltimore, MD, Oct. 2002, pp. 268–277. [17] Y. Huang, W. T. Cheng, C. J. Hsieh, H. Y. Tseng, A. Huang, and Y. T. Hung, “Intermittent scan chain fault diagnosis based on signal probability analysis,” in Proc. Design Automation and Test Europe Conf., Paris, France, Feb. 2004, pp. 1072–1077. [18] I. Pomeranz and S. M. Reddy, “Vector restoration based static compaction of test sequences for synchronous sequential circuits,” in Proc. Int. Conf. Computer Design, Austin, TX, Oct. 1997, pp. 360–365. [19] ——, “On static compaction of test sequences for synchronous sequential circuits,” in Proc. 33rd Design Automation Conf., Las Vegas, NV, Jun. 1996, pp. 215–220.
