Uncalibrated automatic bridge-based CMOS ... - Semantic Scholar
Microelectronics Journal 45 (2014) 589–596
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Uncalibrated automatic bridge-based CMOS integrated interfaces for wide-range resistive sensors portable applications P. Mantenuto, G. Ferri, A. De Marcellis n Department of Industrial and Information Engineering and Economics, University of L’Aquila, Via G. Gronchi 18, 67100 L’Aquila, Italy
art ic l e i nf o
a b s t r a c t
Article history: Received 14 October 2013 Received in revised form 1 April 2014 Accepted 8 April 2014
In this work the authors describe improved solutions on automatic fully-analog uncalibrated Wheatstone bridge-based interfaces suitable for wide-range resistive sensors. The proposed topologies are enhanced and integrated interfaces, based on automatic bridge configurations, completely designed in a standard CMOS technology (AMS 0.35 μm), where Voltage Controlled Resistors (VCRs), formed by MOS transistors, have been properly tuned through the use of a suitable closed feedback loop that continuously ensures the bridge equilibrium condition. The microelectronic design has been performed through the use of symmetrical Operational Transconductance Amplifiers (OTAs) with low-voltage (2 V, single supply) and low-power (63.5 μW) characteristics, so the overall system can be fabricated in a single chip suitable for portable applications. Referring to the first configuration where only one VCR has been employed for both grounded and floating resistive sensors, Orcad PSpice simulations have confirmed the interface capability to estimate the sensor resistance for about 2.7 decades variations (430 Ω; 220 kΩ), with a relative error of about 74%. Moreover, in the second version for an extended estimation range, the interface is able to evaluate the sensor resistance for about 6.6 decades (0.1 Ω; 400 kΩ) with a reduced relative error within ( 1.5%; þ 4%). & 2014 Elsevier Ltd. All rights reserved.
Keywords: Autobalancing Wheatstone bridges CMOS integrated circuit design Portable applications Uncalibrated circuits Voltage Controlled Resistors Wide-range resistive sensor interfaces
1. Introduction The necessity of different chemical species detection in both commercial and military applications and, in particular, in dangerous environment, have led to the development of high-accuracy selective sensors [1–5]. Sensor behavior can be described through a number of features, the most important of them being sensitivity and resolution, which are the output variations with respect to the input measurand change and the minimum detectable quantity, respectively [6]. In the market, a number of sensors (such as MEMS) are actually available but, in most of the cases, they have high costs and relatively shorter lifetime so are unsuitable for simple gas detection systems [7–11]. Recently, a new class of low-cost semiconductor-based sensors, named MOX devices [12–18], has been developed. Thanks to many constructive possibilities, their response to a specific gas mixture in terms of resolution and sensitivity can be easily set. Unfortunately, due to fabrication processes, each set of sensors has different features in terms of baseline and variation range. This implies that the proposed architectures must be optimized to work without the necessity of knowing both sensor baseline and variation range (uncalibrated interface), so they are suitable for the majority of this kind of sensors. n
Corresponding author. Tel.: þ 39 0862 434446; fax: þ39 08624 34403. E-mail address: [email protected] (A. De Marcellis).
http://dx.doi.org/10.1016/j.mejo.2014.04.010 0026-2692/& 2014 Elsevier Ltd. All rights reserved.
For these reasons, in [19–21] we have proposed uncalibrated sensor systems which have satisfied our theoretical expectations in terms of sensitivity, accuracy and wide estimation range. They
Fig. 1. Proposed symmetrical OTA schematic (a) and its symbol (b).
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are bridge-based interfaces developed with discrete components, employing a feedback circuit and a Voltage Controlled Resistor (VCR) properly tuned to force the bridge to work in the equilibrium condition. In this paper, we have designed CMOS solutions of bridge-based front-ends also after suitable modifications of the proposed topologies using microelectronic techniques for integrated circuit design, also in terms of W and L transistor size choice, for a single-chip in the low-cost standard AMS 0.35 μm CMOS technology. Concerning the VCR, since the commercial device AD633 is a discrete component which cannot be integrated, it has been replaced with a MOS transistor, so to obtain an equivalent resistance driven by a suitable biasing signal produced by the feedback loop that always ensures the bridge equilibrium. This choice has also allowed to avoid the need of the exact knowledge of the MOS working region which is, on the contrary, necessary in other solutions presented in the literature [22–26].
Moreover, with respect to traditional design at a discrete level, based on a Operational Amplifier (OA), in the microelectronics design the Operational Transconductance Amplifier (OTA) has been preferred as the voltage amplifier [6,27–35]. When compared to our previous studies [19–21], the present solutions perform better characteristics in terms of lower supply voltage (from 15 V to 2 V), power consumption (from mW to μW range), circuit size and portable applications, dynamic range (6.6 resistive decades, in the last configuration here presented, instead of 6 in [19], 5 in [20] and 3 decades in [21]) and a comparable accuracy. The paper is organized as follows: in Section 2, the OTA schematic and its features will be detailed; in Section 3, the VCR value estimation technique will be described; in Sections 4 and 5, theoretical expectations on simple and extended estimation ranges will be shown, respectively; in Section 6, simulation results will be discussed and, finally, conclusions will be drawn.
Fig. 2. OTA curve of transconductance gain vs. the input voltage.
Fig. 3. OTA input (a) and output (b) impedance vs. frequency.
P. Mantenuto et al. / Microelectronics Journal 45 (2014) 589–596
2. Operational transconductance amplifier design As usually done in the CMOS microelectronics analog design, amplifiers are implemented by OTAs. For this reason, first of all, in this integrated version, all the OAs employed in [19–21] have been replaced with suitably designed low-voltage and low-power OTAs. In particular, the symmetrical OTA (see Fig. 1) represents one of the most effective topologies proposed in the literature for its good performance (e.g., low input offset) and simplicity. A PMOS differential pair (Q1, Q2) has been chosen in input stage so to further reduce the input amplifier noise; then, a 2 V supply voltage has been set so to make it suitable for portable applications. The designed symmetrical OTA is characterized by a high open loop gain and slew-rate and, in particular, labeling B the current mirror (Q3–Q7) and (Q4–Q8) gains, the OTA open loop gain AO is equal to AO ¼ Bg m1 ROUT ;
ð1Þ
where gm1 is the input transistor transconductance, whose trend (as a function of the input voltage) has been shown in Fig. 2, and ROUT is the equivalent resistance calculated at the output terminal, which, taking into account Fig. 1a schematic, can be expressed by the Q6 and Q8 transistors equivalent drain-source resistances rDS6 and rDS8 (or, equivalently, by their drain-source transconductances gDS6 and gDS8), as follows: ROUT ¼ r DS6 ==r DS8 ¼
1 g DS6 þg DS8
ð2Þ
However, the complete frequency dependent behavior of OTA input and output impedances must be underlined in Fig. 3. In particular. the input impedance is a pure capacitance 1.85 pF Table 1 OTA main characteristics. OTA parameter
Value
Single supply voltage Power consumption Input voltage offset GBW Cut-off frequency (f0) Phase margin Open loop voltage gain (AO) Common mode voltage gain Input capacitance Output impedance (R, C) Input equivalent noise Slew rate CMRR PSRR FOMS FOML
2V 63.5 μW E8 nV 13.4 MHz 19.2 kHz 46.51 63.7 dB 40.5 dB 1.85 pF 2.74 MΩ, 50 fF 130 nV at 1 kHz 3.2 V μs 104.2 dB 110.9 dB 1055 254
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valued (see Fig. 3a), while the output impedance can be modeled through a parallel (R,C) of about 2.74 MΩ and 50 fF, respectively (as shown in Fig. 3b). The OTA Gain Band Width (GBW) is related to the input transistor transconductance (gm1) and the load capacitance CL, as follows: g m1 GBW ¼ B 2π ðC OUT þ C L Þ
ð3Þ
where COUT represents the parasitic capacitance at the OTA output node. The slew-rate (SR) depends mainly on the biasing current IB and the load capacitance CL, as follows: SR ¼ B
IB C OUT þ C L
ð4Þ
This means that the higher the mirrors gain, the better the OTA performances, even though power consumption could reach higher values. The differential input stage (Q1, Q2) needs a constant biasing current which is provided by the current mirror (Q9–Q10) thanks to a suitable choice of the resistance R1 value. Taking into account the PMOS Q10 diode connection (i.e., VDS10 ¼VGS10 EVTh,P, being VTh,P the PMOS threshold voltage) and, supposing that transistors Q9 and Q10 are size matched (i.e., (W/L)9 ¼ (W/L)10)), the biasing current IB can be expressed as follows: IB ¼
V DD V Th;P R1
ð5Þ
The designed OTA has been aimed to have low-voltage and low-power characteristics. Its main features, obtained through Orcad PSpice simulations, are here listed in Table 1; in particular, in Fig. 4, the OTA open-loop frequency behavior is shown and its properties have been highlighted. The main constraints about lowoffset (8 nV, see Table 1) and low-noise (130 nV at 1 kHz) features have been considered, so the OTA non-idealities have negligible effects on the interface accuracy. Test results have been conducted thanks to a suitable choice of transistor sizes (shown in Table 2), and also employing proper values of both the mirror biasing resistance (i.e., R1 ¼2 kΩ) and the load capacitance CL. The latter represents the parasitic capacitance of the connection between the OTA output and the external case pin and, according to the CMOS technology employed, has been set to about 5 pF. Circuit performance can be further described through two quality parameters, here named as figures of merit (FOM) [36], which expresses the OTA behavior for both small (FOMS, in terms of frequency response) and large signals (FOML, in terms of circuit speed response) for a determined load capacitance and considering its power consumption; they are expressed as follows: FOM S ¼
GBW ½MHzC L ½pF P ½mW
Fig. 4. OTA open-loop frequency response: the open loop gain AO, the cut-off frequency f0 and the GBW have been marked.
ð6Þ
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Table 2 Designed OTA transistor sizes. Transistor
Q1, Q2 Q3, Q4 Q5, Q6 Q7, Q8 Q9 Q10
FOM L ¼
SR ½V=μsC L ½pF P ½mW
ð7Þ
Dimension [μm] W
L
2000 17.5 64.4 35 30 8
0.35 1.05 20 1.05 9 9
The higher the FOMs the better the OTA behavior. However, as a practical design solution, to have FOMS,L 4100 represents a good compromise between power consumption and circuit response in terms of bandwidth and speed.
3. Integrated voltage controlled resistor solution CMOS transistors have different behaviors and mathematical models, according to their working regions [27]. For this reason it is necessary to exactly know the transistor bias point to have a correct estimation of MOS features in the circuit where it is utilized. Thus, when a MOS is considered as a VCR, in the literature [22–26], it is supposed that it is operative only inside one of its working regions. In this manner, the equivalent resistance is univocally expressed by one of its well-known constitutive relationships. On the contrary, we determine the equivalent resistance given by the MOS transistor drain (here expressed as REQ) through the use of the voltage divider reading, as shown in Fig. 5, by adding a fixed value series resistance (R1). In this way, the REQ value of the VCR, seen from the MOS drain, is simply calculated as V OUT REQ ¼ R1 ð8Þ V DD V OUT
Fig. 5. Resistive voltage divider applied to the REQ transistor drain equivalent resistance.
where VOUT is the voltage divider output. Consequently, from Eq. (8), REQ value can be estimated even if it is still directly related
Fig. 6. Equivalent resistance REQ vs. VCTRL trend, for two possible transistor (W/L) ratio values.
Fig. 7. Proposed autobalancing bridge-based wide-range resistive sensor interface employing only one VCR for both grounded (a) and floating (b) resistive sensor RSENS configurations.
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to the input biasing signal VCTRL, as shown in Fig. 6. Here we have shown equivalent transistor drain resistance (REQ) behaviors with respect to the variations of the control signal VCTRL, in the case of two possible transistors geometrical structures, and in terms of different values of the ratio (W/L). In particular, as described in the following sections, we have shown those (W/L) values which optimize the sensor resistance estimation for both the basic grounded and floating sensor configuration, (W/L)G,F, and for the estimation range extended architecture, (W/L)EXT. Referring to Fig. 6, it is possible to highlight that the less the ratio, the more the equivalent resistance.
4. Proposed integrated single-VCR sensor interface In Fig. 7a the proposed interface schematic is depicted. A simple and low-power dissipation architecture has been developed through a reduced number of active devices (OTAs); in particular, taking into account the traditional resistive Wheatstone bridge architecture, two fixed value resistances (RA and RB) have been employed together with the sensor RSENS and the active tunable resistance performed by the transistor Q1 drain which is necessary for the bridge balancing. The latter is tuned by a suitable control signal (VCTRL) produced by a feedback loop mainly based on the OTA2 connected in the integrator differential configuration.
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The OTA1 buffer has been added to avoid any load effect between the resistive bridge and the control feedback loop. The circuits are based on the following operating principle: when the resistive sensor changes its value, the bridge becomes unbalanced (ΔV¼VA VB a0) and its differential output voltage is not zero. The voltage integrator senses this difference and produces an output ramp signal, having a time constant τINT ¼ RINTCINT, which tunes the transistor so that its drain equivalent resistance forces the bridge into a new equilibrium condition (ΔV¼ 0). In this sense, it is possible to continuously estimate any sensor variation. In particular, the VCTRL control signal can be directly related to the bridge differential output voltage through the following equation: V CTRL ¼ V B
1 RINT C INT
Z
T 0
ΔVðtÞdt
ð9Þ
However, it must be taken into account that, according to its operating principles and fabrication processes, attention should be paid on the sensor characteristics; in particular, sensor can be always considered as grounded (as in Fig. 7a), and its value can be estimated through the expression reported in Eq. (10), where REQ is the equivalent MOS drain resistance calculated by Eq. (8): REQ RB 1 ðΔV=V DD ÞðRA þ REQ =REQ Þ ð10Þ RSENS;G ¼ 1 þ ðΔV =V DD ÞðRA þ REQ =RA Þ RA In the cases where the sensor cannot be employed in a grounded configuration (i.e., both its terminals have to be connected to not zero references), it is enough to switch the sensor branch devices RB with RSENS, as shown in Fig. 7b. Here, the sensor value can be estimated by the following equation: R RB 1 þ ðΔV=V DD ÞðRA þ REQ =RA Þ ð11Þ RSENS;F ¼ A REQ 1 ðΔV=V DD ÞðRA þREQ =REQ Þ It must be highlighted that VCTRL values vary between the OTA output saturation limits, so the REQ can assume a limited set of values between (RMIN; RMAX). Anyway, Eqs. (10) and (11) take into account this effect and allows the sensor resistance value estimation by also reading the bridge differential output ΔV. Note that in case of bridge equilibrium condition, the resistance estimation is the same of the typical Wheatstone bridge architecture, that is respectively
Fig. 8. Proposed autobalancing bridge-based wide-range resistive sensor interface for the extended estimation range, employing two VCRs.
RSENS;G ¼
REQ RB RA
ð12Þ
RSENS;F ¼
RA RB REQ
ð13Þ
Fig. 9. Main signal dynamic results of the grounded configuration: bridge branches signals (VA, VB) and tuning voltage VCTRL.
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5. Proposed integrated double-VCR sensor interface In order to increase the bridge autobalancing range, the modified topology shown in Fig. 8 has been developed. In particular, another MOS transistor has been employed in a VCR configuration, but driven by an opposite biasing control voltage VCTRL2 ¼ VCTRL1, generated by a simple unity gain inverting amplifier obtained by setting R1 ¼ R2. Thus, the two VCRs vary in an opposite way. In this modified version of the interface the sensor can only be employed in a floating configuration and it is not possible to directly estimate the sensor resistance value as before, since three devices simultaneously change their values; in fact, reminding that the MOS transistors follow three working region behaviors, only by reading the VCTRL it is not possible to have any sensor estimation. This problem has been overcome by adding, as in [19], a known resistance (RB) in the right bridge branch, so that, by reading the differential voltage across its terminals, another information is obtained. In this manner, after some calculation, the sensor resistance can be estimated as follows: V DD V C RSENS ¼ RB ð14Þ VC VB
6. Simulation results In order to verify the theoretical results, after a careful designing of the value of both MOS sizes and external passive components, suitable simulations have been conducted through the use of the Orcad PSpice. The device sizing has been aimed to the
Fig. 10. Grounded sensor resistance estimation with respect to the theoretical value and its percentage relative error.
reduction of the estimation relative error and a number of simulations have been conducted in order to find the best setup. In particular, for both (Fig. 7) grounded and floating sensor configuration interfaces, we have chosen: RA ¼RB ¼ 10 kΩ, RINT ¼ 33 kΩ and CINT ¼47 pF. In particular, in Fig. 9, dynamical simulation results about the single VCR grounded resistive sensor interface are depicted. We can see that, when the sensor changes its value the bridge becomes unbalanced and, after a reduced transient time, voltage VCTRL assumes those values which force the bridge to reach a new equilibrium condition ΔV¼ 0, since the two bridge branches voltages VA and VB become equal. Through Eqs. (8)–(13) the sensor resistance is easily estimated and simulation results have demonstrated that the estimation percentage relative error is confined within 75% inside the resistance range (430 Ω; 220 kΩ), of about 2.7 decades, as shown in Fig. 10. A more detailed results analysis has shown that the error is much lower, less than 70.5%, in the decade (2.2 kΩ; 22 kΩ). Fig. 11 shows simulation results for the single VCR floating resistive sensor configuration; as for the former front-end, when a sensor variation occurs, the feedback loop generates a suitable VCTRL value that equilibrates the bridge output voltages. As reported in Fig. 12, a deep analysis about the optimization of circuit behavior has demonstrated that it is possible to limit the estimation relative error under 7 5% (calculated through Eq. (11)) inside the resistance range (430 Ω; 220 kΩ) of about 2.7 decades. In particular, it has been highlighted that inside the decade (4.7 kΩ; 47 kΩ) the estimation error is confined within 7 0.5%. Concerning the last solution reported in Fig. 8, the device sizing has been chosen so that the estimation relative error was reduced.
Fig. 12. Floating sensor resistance estimation with respect to the theoretical value and its percentage relative error.
Fig. 11. Main signal dynamic results of the floating configuration: bridge branches signals (VA, VB) and tuning voltage VCTRL.
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Fig. 13. Main signal dynamic results of the extended configuration: bridge branches signals (VA, VB), transistors Q1 and Q2 tuning voltages VCTRL2 and VCTRL1, respectively.
References
Fig. 14. Estimated sensor resistance with respect to the theoretical value and its percentage relative error.
Thus, we have chosen: RA ¼100 kΩ, RB ¼ 47 kΩ, RINT ¼ 63 kΩ, CINT ¼ 47 pF and R1 ¼ R2 ¼100 kΩ. More in detail, from Fig. 13, it can be seen that when a sensor variation occurs, the system is able to produce the correct VCTRL value which forces the bridge to reach a new equilibrium condition. It must be highlighted that the extended architecture is capable to estimate up to 6.6 resistive variation decades, through Eq. (14), within (0.1 Ω; 400 kΩ), with a percentage relative error in the range 1.5%; þ4%, as shown in Fig. 14. A deeper analysis on results have shown that the error flattens to about 0.4% inside the range 1 Ω; 10 kΩ.
7. Conclusions In this work we have presented two novel solutions for integrated CMOS-based auto balancing bridge wide-range resistive sensor interfaces which overcome the reduced operative range of the traditional Wheatstone bridge. With respect to previous topologies based on discrete devices, here the proposed solutions have been designed in a standard CMOS technology so to be cost effective since the entire system can be integrated inside the same chip. Simulation results have confirmed the theoretical expectations and, in particular, the sensor resistance can be easily and accurately determined. Furthermore, through the use of two MOS transistors as Voltage Controlled Resistors, the estimation range has been further enlarged still maintaining a reduced estimation percentage relative error.
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Uncalibrated automatic bridge-based CMOS integrated interfaces for wide-range resistive sensors portable applications P. Mantenuto, G. Ferri, A. De Marcellis n Department of Industrial and Information Engineering and Economics, University of L’Aquila, Via G. Gronchi 18, 67100 L’Aquila, Italy
art ic l e i nf o
a b s t r a c t
Article history: Received 14 October 2013 Received in revised form 1 April 2014 Accepted 8 April 2014
In this work the authors describe improved solutions on automatic fully-analog uncalibrated Wheatstone bridge-based interfaces suitable for wide-range resistive sensors. The proposed topologies are enhanced and integrated interfaces, based on automatic bridge configurations, completely designed in a standard CMOS technology (AMS 0.35 μm), where Voltage Controlled Resistors (VCRs), formed by MOS transistors, have been properly tuned through the use of a suitable closed feedback loop that continuously ensures the bridge equilibrium condition. The microelectronic design has been performed through the use of symmetrical Operational Transconductance Amplifiers (OTAs) with low-voltage (2 V, single supply) and low-power (63.5 μW) characteristics, so the overall system can be fabricated in a single chip suitable for portable applications. Referring to the first configuration where only one VCR has been employed for both grounded and floating resistive sensors, Orcad PSpice simulations have confirmed the interface capability to estimate the sensor resistance for about 2.7 decades variations (430 Ω; 220 kΩ), with a relative error of about 74%. Moreover, in the second version for an extended estimation range, the interface is able to evaluate the sensor resistance for about 6.6 decades (0.1 Ω; 400 kΩ) with a reduced relative error within ( 1.5%; þ 4%). & 2014 Elsevier Ltd. All rights reserved.
Keywords: Autobalancing Wheatstone bridges CMOS integrated circuit design Portable applications Uncalibrated circuits Voltage Controlled Resistors Wide-range resistive sensor interfaces
1. Introduction The necessity of different chemical species detection in both commercial and military applications and, in particular, in dangerous environment, have led to the development of high-accuracy selective sensors [1–5]. Sensor behavior can be described through a number of features, the most important of them being sensitivity and resolution, which are the output variations with respect to the input measurand change and the minimum detectable quantity, respectively [6]. In the market, a number of sensors (such as MEMS) are actually available but, in most of the cases, they have high costs and relatively shorter lifetime so are unsuitable for simple gas detection systems [7–11]. Recently, a new class of low-cost semiconductor-based sensors, named MOX devices [12–18], has been developed. Thanks to many constructive possibilities, their response to a specific gas mixture in terms of resolution and sensitivity can be easily set. Unfortunately, due to fabrication processes, each set of sensors has different features in terms of baseline and variation range. This implies that the proposed architectures must be optimized to work without the necessity of knowing both sensor baseline and variation range (uncalibrated interface), so they are suitable for the majority of this kind of sensors. n
Corresponding author. Tel.: þ 39 0862 434446; fax: þ39 08624 34403. E-mail address: [email protected] (A. De Marcellis).
http://dx.doi.org/10.1016/j.mejo.2014.04.010 0026-2692/& 2014 Elsevier Ltd. All rights reserved.
For these reasons, in [19–21] we have proposed uncalibrated sensor systems which have satisfied our theoretical expectations in terms of sensitivity, accuracy and wide estimation range. They
Fig. 1. Proposed symmetrical OTA schematic (a) and its symbol (b).
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are bridge-based interfaces developed with discrete components, employing a feedback circuit and a Voltage Controlled Resistor (VCR) properly tuned to force the bridge to work in the equilibrium condition. In this paper, we have designed CMOS solutions of bridge-based front-ends also after suitable modifications of the proposed topologies using microelectronic techniques for integrated circuit design, also in terms of W and L transistor size choice, for a single-chip in the low-cost standard AMS 0.35 μm CMOS technology. Concerning the VCR, since the commercial device AD633 is a discrete component which cannot be integrated, it has been replaced with a MOS transistor, so to obtain an equivalent resistance driven by a suitable biasing signal produced by the feedback loop that always ensures the bridge equilibrium. This choice has also allowed to avoid the need of the exact knowledge of the MOS working region which is, on the contrary, necessary in other solutions presented in the literature [22–26].
Moreover, with respect to traditional design at a discrete level, based on a Operational Amplifier (OA), in the microelectronics design the Operational Transconductance Amplifier (OTA) has been preferred as the voltage amplifier [6,27–35]. When compared to our previous studies [19–21], the present solutions perform better characteristics in terms of lower supply voltage (from 15 V to 2 V), power consumption (from mW to μW range), circuit size and portable applications, dynamic range (6.6 resistive decades, in the last configuration here presented, instead of 6 in [19], 5 in [20] and 3 decades in [21]) and a comparable accuracy. The paper is organized as follows: in Section 2, the OTA schematic and its features will be detailed; in Section 3, the VCR value estimation technique will be described; in Sections 4 and 5, theoretical expectations on simple and extended estimation ranges will be shown, respectively; in Section 6, simulation results will be discussed and, finally, conclusions will be drawn.
Fig. 2. OTA curve of transconductance gain vs. the input voltage.
Fig. 3. OTA input (a) and output (b) impedance vs. frequency.
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2. Operational transconductance amplifier design As usually done in the CMOS microelectronics analog design, amplifiers are implemented by OTAs. For this reason, first of all, in this integrated version, all the OAs employed in [19–21] have been replaced with suitably designed low-voltage and low-power OTAs. In particular, the symmetrical OTA (see Fig. 1) represents one of the most effective topologies proposed in the literature for its good performance (e.g., low input offset) and simplicity. A PMOS differential pair (Q1, Q2) has been chosen in input stage so to further reduce the input amplifier noise; then, a 2 V supply voltage has been set so to make it suitable for portable applications. The designed symmetrical OTA is characterized by a high open loop gain and slew-rate and, in particular, labeling B the current mirror (Q3–Q7) and (Q4–Q8) gains, the OTA open loop gain AO is equal to AO ¼ Bg m1 ROUT ;
ð1Þ
where gm1 is the input transistor transconductance, whose trend (as a function of the input voltage) has been shown in Fig. 2, and ROUT is the equivalent resistance calculated at the output terminal, which, taking into account Fig. 1a schematic, can be expressed by the Q6 and Q8 transistors equivalent drain-source resistances rDS6 and rDS8 (or, equivalently, by their drain-source transconductances gDS6 and gDS8), as follows: ROUT ¼ r DS6 ==r DS8 ¼
1 g DS6 þg DS8
ð2Þ
However, the complete frequency dependent behavior of OTA input and output impedances must be underlined in Fig. 3. In particular. the input impedance is a pure capacitance 1.85 pF Table 1 OTA main characteristics. OTA parameter
Value
Single supply voltage Power consumption Input voltage offset GBW Cut-off frequency (f0) Phase margin Open loop voltage gain (AO) Common mode voltage gain Input capacitance Output impedance (R, C) Input equivalent noise Slew rate CMRR PSRR FOMS FOML
2V 63.5 μW E8 nV 13.4 MHz 19.2 kHz 46.51 63.7 dB 40.5 dB 1.85 pF 2.74 MΩ, 50 fF 130 nV at 1 kHz 3.2 V μs 104.2 dB 110.9 dB 1055 254
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valued (see Fig. 3a), while the output impedance can be modeled through a parallel (R,C) of about 2.74 MΩ and 50 fF, respectively (as shown in Fig. 3b). The OTA Gain Band Width (GBW) is related to the input transistor transconductance (gm1) and the load capacitance CL, as follows: g m1 GBW ¼ B 2π ðC OUT þ C L Þ
ð3Þ
where COUT represents the parasitic capacitance at the OTA output node. The slew-rate (SR) depends mainly on the biasing current IB and the load capacitance CL, as follows: SR ¼ B
IB C OUT þ C L
ð4Þ
This means that the higher the mirrors gain, the better the OTA performances, even though power consumption could reach higher values. The differential input stage (Q1, Q2) needs a constant biasing current which is provided by the current mirror (Q9–Q10) thanks to a suitable choice of the resistance R1 value. Taking into account the PMOS Q10 diode connection (i.e., VDS10 ¼VGS10 EVTh,P, being VTh,P the PMOS threshold voltage) and, supposing that transistors Q9 and Q10 are size matched (i.e., (W/L)9 ¼ (W/L)10)), the biasing current IB can be expressed as follows: IB ¼
V DD V Th;P R1
ð5Þ
The designed OTA has been aimed to have low-voltage and low-power characteristics. Its main features, obtained through Orcad PSpice simulations, are here listed in Table 1; in particular, in Fig. 4, the OTA open-loop frequency behavior is shown and its properties have been highlighted. The main constraints about lowoffset (8 nV, see Table 1) and low-noise (130 nV at 1 kHz) features have been considered, so the OTA non-idealities have negligible effects on the interface accuracy. Test results have been conducted thanks to a suitable choice of transistor sizes (shown in Table 2), and also employing proper values of both the mirror biasing resistance (i.e., R1 ¼2 kΩ) and the load capacitance CL. The latter represents the parasitic capacitance of the connection between the OTA output and the external case pin and, according to the CMOS technology employed, has been set to about 5 pF. Circuit performance can be further described through two quality parameters, here named as figures of merit (FOM) [36], which expresses the OTA behavior for both small (FOMS, in terms of frequency response) and large signals (FOML, in terms of circuit speed response) for a determined load capacitance and considering its power consumption; they are expressed as follows: FOM S ¼
GBW ½MHzC L ½pF P ½mW
Fig. 4. OTA open-loop frequency response: the open loop gain AO, the cut-off frequency f0 and the GBW have been marked.
ð6Þ
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Table 2 Designed OTA transistor sizes. Transistor
Q1, Q2 Q3, Q4 Q5, Q6 Q7, Q8 Q9 Q10
FOM L ¼
SR ½V=μsC L ½pF P ½mW
ð7Þ
Dimension [μm] W
L
2000 17.5 64.4 35 30 8
0.35 1.05 20 1.05 9 9
The higher the FOMs the better the OTA behavior. However, as a practical design solution, to have FOMS,L 4100 represents a good compromise between power consumption and circuit response in terms of bandwidth and speed.
3. Integrated voltage controlled resistor solution CMOS transistors have different behaviors and mathematical models, according to their working regions [27]. For this reason it is necessary to exactly know the transistor bias point to have a correct estimation of MOS features in the circuit where it is utilized. Thus, when a MOS is considered as a VCR, in the literature [22–26], it is supposed that it is operative only inside one of its working regions. In this manner, the equivalent resistance is univocally expressed by one of its well-known constitutive relationships. On the contrary, we determine the equivalent resistance given by the MOS transistor drain (here expressed as REQ) through the use of the voltage divider reading, as shown in Fig. 5, by adding a fixed value series resistance (R1). In this way, the REQ value of the VCR, seen from the MOS drain, is simply calculated as V OUT REQ ¼ R1 ð8Þ V DD V OUT
Fig. 5. Resistive voltage divider applied to the REQ transistor drain equivalent resistance.
where VOUT is the voltage divider output. Consequently, from Eq. (8), REQ value can be estimated even if it is still directly related
Fig. 6. Equivalent resistance REQ vs. VCTRL trend, for two possible transistor (W/L) ratio values.
Fig. 7. Proposed autobalancing bridge-based wide-range resistive sensor interface employing only one VCR for both grounded (a) and floating (b) resistive sensor RSENS configurations.
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to the input biasing signal VCTRL, as shown in Fig. 6. Here we have shown equivalent transistor drain resistance (REQ) behaviors with respect to the variations of the control signal VCTRL, in the case of two possible transistors geometrical structures, and in terms of different values of the ratio (W/L). In particular, as described in the following sections, we have shown those (W/L) values which optimize the sensor resistance estimation for both the basic grounded and floating sensor configuration, (W/L)G,F, and for the estimation range extended architecture, (W/L)EXT. Referring to Fig. 6, it is possible to highlight that the less the ratio, the more the equivalent resistance.
4. Proposed integrated single-VCR sensor interface In Fig. 7a the proposed interface schematic is depicted. A simple and low-power dissipation architecture has been developed through a reduced number of active devices (OTAs); in particular, taking into account the traditional resistive Wheatstone bridge architecture, two fixed value resistances (RA and RB) have been employed together with the sensor RSENS and the active tunable resistance performed by the transistor Q1 drain which is necessary for the bridge balancing. The latter is tuned by a suitable control signal (VCTRL) produced by a feedback loop mainly based on the OTA2 connected in the integrator differential configuration.
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The OTA1 buffer has been added to avoid any load effect between the resistive bridge and the control feedback loop. The circuits are based on the following operating principle: when the resistive sensor changes its value, the bridge becomes unbalanced (ΔV¼VA VB a0) and its differential output voltage is not zero. The voltage integrator senses this difference and produces an output ramp signal, having a time constant τINT ¼ RINTCINT, which tunes the transistor so that its drain equivalent resistance forces the bridge into a new equilibrium condition (ΔV¼ 0). In this sense, it is possible to continuously estimate any sensor variation. In particular, the VCTRL control signal can be directly related to the bridge differential output voltage through the following equation: V CTRL ¼ V B
1 RINT C INT
Z
T 0
ΔVðtÞdt
ð9Þ
However, it must be taken into account that, according to its operating principles and fabrication processes, attention should be paid on the sensor characteristics; in particular, sensor can be always considered as grounded (as in Fig. 7a), and its value can be estimated through the expression reported in Eq. (10), where REQ is the equivalent MOS drain resistance calculated by Eq. (8): REQ RB 1 ðΔV=V DD ÞðRA þ REQ =REQ Þ ð10Þ RSENS;G ¼ 1 þ ðΔV =V DD ÞðRA þ REQ =RA Þ RA In the cases where the sensor cannot be employed in a grounded configuration (i.e., both its terminals have to be connected to not zero references), it is enough to switch the sensor branch devices RB with RSENS, as shown in Fig. 7b. Here, the sensor value can be estimated by the following equation: R RB 1 þ ðΔV=V DD ÞðRA þ REQ =RA Þ ð11Þ RSENS;F ¼ A REQ 1 ðΔV=V DD ÞðRA þREQ =REQ Þ It must be highlighted that VCTRL values vary between the OTA output saturation limits, so the REQ can assume a limited set of values between (RMIN; RMAX). Anyway, Eqs. (10) and (11) take into account this effect and allows the sensor resistance value estimation by also reading the bridge differential output ΔV. Note that in case of bridge equilibrium condition, the resistance estimation is the same of the typical Wheatstone bridge architecture, that is respectively
Fig. 8. Proposed autobalancing bridge-based wide-range resistive sensor interface for the extended estimation range, employing two VCRs.
RSENS;G ¼
REQ RB RA
ð12Þ
RSENS;F ¼
RA RB REQ
ð13Þ
Fig. 9. Main signal dynamic results of the grounded configuration: bridge branches signals (VA, VB) and tuning voltage VCTRL.
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5. Proposed integrated double-VCR sensor interface In order to increase the bridge autobalancing range, the modified topology shown in Fig. 8 has been developed. In particular, another MOS transistor has been employed in a VCR configuration, but driven by an opposite biasing control voltage VCTRL2 ¼ VCTRL1, generated by a simple unity gain inverting amplifier obtained by setting R1 ¼ R2. Thus, the two VCRs vary in an opposite way. In this modified version of the interface the sensor can only be employed in a floating configuration and it is not possible to directly estimate the sensor resistance value as before, since three devices simultaneously change their values; in fact, reminding that the MOS transistors follow three working region behaviors, only by reading the VCTRL it is not possible to have any sensor estimation. This problem has been overcome by adding, as in [19], a known resistance (RB) in the right bridge branch, so that, by reading the differential voltage across its terminals, another information is obtained. In this manner, after some calculation, the sensor resistance can be estimated as follows: V DD V C RSENS ¼ RB ð14Þ VC VB
6. Simulation results In order to verify the theoretical results, after a careful designing of the value of both MOS sizes and external passive components, suitable simulations have been conducted through the use of the Orcad PSpice. The device sizing has been aimed to the
Fig. 10. Grounded sensor resistance estimation with respect to the theoretical value and its percentage relative error.
reduction of the estimation relative error and a number of simulations have been conducted in order to find the best setup. In particular, for both (Fig. 7) grounded and floating sensor configuration interfaces, we have chosen: RA ¼RB ¼ 10 kΩ, RINT ¼ 33 kΩ and CINT ¼47 pF. In particular, in Fig. 9, dynamical simulation results about the single VCR grounded resistive sensor interface are depicted. We can see that, when the sensor changes its value the bridge becomes unbalanced and, after a reduced transient time, voltage VCTRL assumes those values which force the bridge to reach a new equilibrium condition ΔV¼ 0, since the two bridge branches voltages VA and VB become equal. Through Eqs. (8)–(13) the sensor resistance is easily estimated and simulation results have demonstrated that the estimation percentage relative error is confined within 75% inside the resistance range (430 Ω; 220 kΩ), of about 2.7 decades, as shown in Fig. 10. A more detailed results analysis has shown that the error is much lower, less than 70.5%, in the decade (2.2 kΩ; 22 kΩ). Fig. 11 shows simulation results for the single VCR floating resistive sensor configuration; as for the former front-end, when a sensor variation occurs, the feedback loop generates a suitable VCTRL value that equilibrates the bridge output voltages. As reported in Fig. 12, a deep analysis about the optimization of circuit behavior has demonstrated that it is possible to limit the estimation relative error under 7 5% (calculated through Eq. (11)) inside the resistance range (430 Ω; 220 kΩ) of about 2.7 decades. In particular, it has been highlighted that inside the decade (4.7 kΩ; 47 kΩ) the estimation error is confined within 7 0.5%. Concerning the last solution reported in Fig. 8, the device sizing has been chosen so that the estimation relative error was reduced.
Fig. 12. Floating sensor resistance estimation with respect to the theoretical value and its percentage relative error.
Fig. 11. Main signal dynamic results of the floating configuration: bridge branches signals (VA, VB) and tuning voltage VCTRL.
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Fig. 13. Main signal dynamic results of the extended configuration: bridge branches signals (VA, VB), transistors Q1 and Q2 tuning voltages VCTRL2 and VCTRL1, respectively.
References
Fig. 14. Estimated sensor resistance with respect to the theoretical value and its percentage relative error.
Thus, we have chosen: RA ¼100 kΩ, RB ¼ 47 kΩ, RINT ¼ 63 kΩ, CINT ¼ 47 pF and R1 ¼ R2 ¼100 kΩ. More in detail, from Fig. 13, it can be seen that when a sensor variation occurs, the system is able to produce the correct VCTRL value which forces the bridge to reach a new equilibrium condition. It must be highlighted that the extended architecture is capable to estimate up to 6.6 resistive variation decades, through Eq. (14), within (0.1 Ω; 400 kΩ), with a percentage relative error in the range 1.5%; þ4%, as shown in Fig. 14. A deeper analysis on results have shown that the error flattens to about 0.4% inside the range 1 Ω; 10 kΩ.
7. Conclusions In this work we have presented two novel solutions for integrated CMOS-based auto balancing bridge wide-range resistive sensor interfaces which overcome the reduced operative range of the traditional Wheatstone bridge. With respect to previous topologies based on discrete devices, here the proposed solutions have been designed in a standard CMOS technology so to be cost effective since the entire system can be integrated inside the same chip. Simulation results have confirmed the theoretical expectations and, in particular, the sensor resistance can be easily and accurately determined. Furthermore, through the use of two MOS transistors as Voltage Controlled Resistors, the estimation range has been further enlarged still maintaining a reduced estimation percentage relative error.
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