Uninterruptible Power Supply
UNINTERRUPTIBLE POWER SUPPLY
Project Design Report
Design Team #6 Donald J. Firca, Jr. Donald J. Fisher Jr. Dung Nguyen
Faculty Advisor: Dr. Malik Elbuluk
Submitted December 5, 2005
TABLE OF CONTENTS ABSTRACT ........................................................................................................................... 2 INTRODUCTION .................................................................................................................... 3 Statement of Need…………………………………………………………………3 Problem Definition………………………………………………………...………3 DESIGN SPECIFICATIONS……………………………………………………………...……4 ALTERNATIVE DESIGN ANALYSIS …………………………………………………………7 Overall System Design …………………………………………………………...7 Individual Component Design - Hardware ……………………………...………10 ACCEPTED TECHNICAL DESIGN ……………………………………………………….…14 Introduction and Overall System Summary……………………………………..14 Power Analysis…………………………………………………………………..16 Control Circuit..………………………………………………………………....18 Hardware ………………………………………………………………………………..18 Control Scheme ………………………………………………………………................19 Inverter …………………………………………………………………………..26 TESTING PROCEDURES …………………………………………………………………..34 FINANCIAL BUDGET ……………………………………………………………………..35 Design Team Information ……………………………………………………………
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ABSTRACT An uninterruptible power supply for providing backup power in the event of a disruption in the utility-supplied power. A microcontroller controls the operation of the various components and generates a pulse-width modulation control signal. When a disruption of the utility power occurs, the microcontroller detects such an event, activates the pulse-width-modulation inverter, and seamlessly transfers the load from utilitysupplied power to backup power. Backup power of 1 kW for approximately three minutes will provide a user with time to save unsaved data on a desktop PC and properly shut it down.
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INTRODUCTION Statement of Need: As the general population continues to grow, there is an ever-increasing demand for electricity placed on the world’s power-generation and distribution facilities. Although significant measures are taken to ensure a reliable supply of electric power, the significant demand for power increases the likelihood that power outages and other electrical disruptions such as brownouts will occur. Uninterruptible power supplies (hereinafter “UPS”) that currently exist offer users extended periods of backup power during which they can continue to use electronic equipment such as a personal computer. However, such UPS’s are expensive and can be priced up to several hundreds of dollars. Further, the extended periods of backup power are typically not needed by users because other electronic equipment such as lights, a cable/DSL modem and printer, and other office equipment required by users to perform work on the PC are not available. Problem Definition: Goals: • • • • •
Provide backup power to a PC and light in the event of a power outage. Limit the duration of backup power to a suitable length to permit a user of the PC to save unsaved data and properly shut the PC down. Warn a user of an impending expiration of the backup power during a power outage. Seamlessly return the user’s PC and light to electric power supplied by the utility in the event power is restored before the expiration of backup power occurs. Clearly indicate to the user the status of the system.
Objectives: • • • • •
Detect the occurrence of a power outage and transfer the load from utility power to backup power rapidly enough to prevent loss of unsaved data on a PC. Provide backup power of 1 kW for a duration of 3 minutes. Sound an audible warning to the user to indicate approximately 30 seconds of backup power remaining. Synchronize phase of backup power with that of utility power if the utility power is restored while backup power is being supplied. Visually display the approximate battery level and the system status.
Constraints: •
Transfer the load from utility power to backup power within 4 ms upon the occurrence of a power outage. 3
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• •
Must approximately match the phase of the backup power to that of the utility power just prior to the disruption of utility power to minimize the effect on the load stemming from significant phase differences. Must provide backup power for a suitable period of time to allow the user to save unsaved data on the PC and properly shut it down. The overall cost of the prototype unit must be within the budgeted $300 to minimize the cost of each mass-produced unit, which is preferably under $75.
DESIGN SPECIFICATIONS •
Detect the occurrence of a power outage and transfer the load from utility power to backup power rapidly enough to prevent loss of unsaved data on a PC. Research revealed that the universally-accepted safe harbor for restoring the supply of power to a sensitive load such as a PC is 4 ms, with 5 ms being the absolute maximum allowable time frame. To offer a response within this time frame, a low-voltage detector is to be provided to output a blackout signal to the microcontroller in the event of a complete loss of utility-supplied power (referred to herein as “line power”). Similarly, voltage fluctuations of a lesser degree, commonly called brownouts, will also be followed by the transmission of a brownout signal to the microcontroller. The blackout and brownout signals are represented by varying voltage levels of the respective signals transmitted to the microcontroller. Disturbances of the line-power frequency are to be detected and compensated for by converting the frequency of the line power to a voltage level with a frequency-to-voltage converter. Again, a frequency fault signal is to be output to the microcontroller in the form of a voltage level different from that of the signals discussed above. A balance must be struck by establishing tolerable limits for each of the fault conditions to prevent the unnecessary, repeated operation of the UPS, but to also ensure proper operation of the UPS when the intolerable fault conditions actually exist. Line-power voltage disturbances of ±10% and frequency disturbances of ± 1Hz for three consecutive cycles were determined to allow for proper operation of the UPS, without exposing the connected load to significant risk of damage.
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Provide backup power of 1 kW for a duration of 3 minutes.
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The power rating of an average Pentium™ 4 PC running the Windows XP operating system is approximately 385 W. Likewise, an average CRT monitor has a power rating of about 220 W while a 100 W light bulb obviously consumes approximately 100 W of power. Combined, this amounts to 705 W of required power. The remaining 295 W of power allows for system expansion or prolonged backup running times in the event that the system remains as is. When the load is transferred from line power to the backup power supplied by the UPS, the phase of the voltage waveform generated by the UPS must be similar to that of the line power when the power disruption occurred. Drastically mismatched voltage phases can damage the load. Thus, the microcontroller is to implement an internal phase-locked loop to ensure that the phase of the backup voltage waveform is approximately the same as the phase of the line voltage waveform immediately prior to the disruption of line power. •
Sound an audible warning to the user to indicate approximately 30 seconds of backup power remaining. Assuming a backup running time of approximately 3 minutes, 10% of the backup running time would equal 18 seconds. Feeling that 18 seconds was too short of a warning period during which a user can save unsaved data and shutdown the PC, the designers decided to provide a warning sound at 30 seconds prior to exhaustion of the system’s batteries.
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Synchronize phase of backup power with that of utility power if the utility power is restored while backup power is being supplied. If a temporary disruption of line power occurs, then the line power can possibly be restored during operation of the UPS. In such a case, the UPS is to sense the return of line power and gradually modulate the phase of the backup voltage waveform until it matches the phase of the line voltage waveform. Only when the two phases are reasonably close will the microcontroller actuate the transfer switch to seamlessly return the load to the line power.
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Visually display the approximate battery level and the system status. Among the microcontroller’s duties will be controlling a display that will indicate to the user the status of the system, i.e., whether line power or backup power is being supplied, and the strength of the battery bank. A
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dual LED display will be implemented to indicate system status while an 8-digit LED bar graph will display the battery level from a scale of zero to seven. A scale consisting of 8 digits provides a reasonable resolution that can be easily viewed and grasped by the user. And although the analogto-digital converter of the microcontroller that was selected can operate in a 10-bit mode, three bits are all that are necessary to display the eight possible battery-level states (i.e., 23=8).
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ALTERNATIVE DESIGN ANALYSIS Overall System Design From the perspective of the overall UPS system, the first design step was to select a system-wide topology for implementing the UPS. There are primarily three different UPS topologies from which to choose, each having its own advantages and disadvantages. The first topology considered was the topology that is commonly referred to as “passive standby,” or “off-line,” which is shown below in Figure 1. Basically, the passive-standby UPS supplies the AC input voltage directly to the load when it is available, bypassing the backup power portion of the UPS. When a disruption of the AC input voltage occurs, the DC voltage waveform from the battery is inverted by an inverter into an AC output voltage waveform approximately the same as that of the AC input voltage. A transfer switch is provided to selectively control which AC output voltage waveform is delivered to the load: the AC input supplied by the utility, or the AC output waveform from the inverter.
Figure 1. Passive-standby, or off-line UPS topology. The passive-standby UPS offers the advantages of a simple design, relatively small size and low cost. However isolation of the load from the upstream distribution system and line power is limited at best, and should only be used for applications with power ratings less than 2 kVA. And for critical loads such as corporate computer centers,
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medical applications and telephone exchanges, the time required to transfer the load from line power to that from the inverter can be unacceptably long. And while the passivestandby UPS offers suitable protection from loads like home computers, there is no output voltage or output frequency regulation. Next, the line-interactive UPS topology shown schematically in Figure 2 was considered. According to this topology, the inverter is connected to the load parallel to the AC input voltage from the utility. When line power is being delivered, the inverter is also operational to charge the battery and to condition the line power. If a disruption to the line power occurs, the battery/inverter combination maintain continuity of power to the load. Once this occurs, the static transfer switch is opened to prevent power from the inverter from being introduced to the line-power distribution system.
STATIC SWITCH AC INPUT LOAD
INVERTER
BATTERY
Figure 2. Line-interactive UPS topology. The advantage of the liner-interactive UPS topology is that transferring the load from line power to backup power is almost instantaneous since the backup power is generated in parallel with the line power. Thus, the load sees a seamless transition. However, like the passive-standby UPS topology, the line-interactive topology suffers from a lack of isolation of the load from the line power, including all spikes and overvoltages. Further, there is no regulation of the output frequency since the output frequency depends on the frequency of the line power, which is a primary reason why this type of UPS is typically not used for sensitive loads with high power ratings.
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The third and final topology considered was the double-conversion UPS topology shown below in Figure 3. According to this topology, the inverter is connected in series between the AC line-power input and the load. The inverter is operational regardless of whether line power is available. When line power is available, the AC input voltage waveform is rectified, the rectified DC waveform is inverted, and the inverted AC waveform is then supplied to the load. If the line power is disrupted, or otherwise falls outside of the tolerable limits of the load, the battery power is inverted and supplied to the load. Since the battery is parallel with the line-power input, the transition from line power to backup power is seamless. Additionally, there is a static bypass switch that allows line power to bypass the inverter and be delivered directly to the load as desired.
Figure 3. Double-conversion UPS topology. This configuration offers many advantages over those topologies discussed above. Primary among those advantages is that the double-conversion UPS offers isolation to the load from upstream voltage disruptions in the AC input voltage waveform. Thus, voltage spikes and over voltages in the AC input waveform are not transmitted through to the load. Further, since all AC output voltage waveforms (during normal operation) are generated by the inverter, this topology allows for precise control and fine tolerances. For these reasons, the double-conversion UPS topology is used almost universally for critical and high-power-rating applications requiring 10 kVA and up. To offer all these advantages, however, the double-conversion topology is relatively complex and very expensive.
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After weighing the various advantages and disadvantages of each of these topologies, it was concluded that the passive-standby UPS topology would be pursued. First, its relative simplicity will allow for the research and development of such a UPS to be completed within the budget constraints imposed. And second, its widespread adoption for applications with power ratings equal to or less than 2 kVA coincide with the application for which it is being designed.
Individual Component Design - Hardware Once the passive-standby topology was selected, the next step was to determine how best to implement the design. From Figure 1, it can be seen that a passive standby UPS includes three primary components: the rectifier/charger, inverter and transfer switch. In addition to these illustrated components, the control circuitry must also be considered. For purposes of the design, the members of the design team focused their efforts on designing the inverter, transfer switch, and control circuit. The remaining components, such as the rectifier/charger and the DC/DC converter necessary for providing the desired power supply to the microcontroller are to be purchased as discrete components according to the specified design parameters. Inverter For the inverter, a number of configurations and control routines were considered before settling on a full-bridge inverter controlled according to pulse-width modulation (“PWM”) with a switching frequency of 2.5 kHz. It was first determined that a sine wave output waveform was desired as opposed to quasi sine or square wave waveforms. Sine waves bear the closest resemblance to the actual voltage waveforms produced by the AC mains, which requires less filtering and is less likely to damage the load to which it is delivered. Although sine wave output is closest to replicating the AC mains supply, it is also likely to be the most costly and least efficient. In contrast, a square wave is the cheapest, and probably the most efficient, but it is also the most likely to cause operational problems due to its non-sinusoidal waveform. The quasi-sine wave is an intermediate waveform, which can replicate the key characteristics of a true sine wave if properly controlled. But the advantages in filtering and powering the load make the sine wave the most-ideal candidate for the UPS. Constant-voltage transformers (“CVT's”) have traditionally been the method of generating a pure sine wave, and they include large transformers in which an oscillation is established. Although they are simple devices and are relatively durable, they tend to be inefficient, large and heavy, and sometimes very noisy. Further, there is a tendency for the waveform to become severely distorted when delivered to certain types of loads. In contrast, a series of switches can be employed along with a PWM switching strategy to replicate a pure sine wave. Despite being more complex than a CVT, a PWM
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inverter is relatively small and light, making it an ideal DC to AC inverter option. Additionally, PWM control strategies involve either unipolar or bipolar switching, and push the harmonics having significant amplitudes into the high frequency range near the PWM switching frequency. As the switching frequency is increased, a high quality output voltage waveform can be more easily recovered by low-pass filtering. The higher the switching frequency, the less stringent are the demands placed on the low-pass filter. For a switching frequency of 2.5 kHz, the corner frequency of an acceptable low-pass filter can be between 60 Hz and 2.5 kHz since the desired output waveform is approximately 60 Hz. The full-bridge topology, shown below in Figure 4, is such a configuration of switches and was chosen to generate the sine wave voltage waveform. Other topologies, such as the half-bridge inverter, exist but offer efficiencies approximately half that offered by the full-bridge inverter. The increased efficiency over the half-bridge inverter is attainable without significantly adding to the complexity or cost of the device.
Q1
Q3
V1 Low Pass Filter
Load
C
Q2
Q4
Figure 4. Full-bridge inverter configuration. With regard to the individual components chosen for the full-bridge inverter in Figure 4, the voltage across each power device remains close to the DC bus voltage for a significant portion of the switching transient, while a relatively large current is being commutated during a typical turn-on or turn-off operation. Therefore, the switch chosen for implementing the full-bridge inverter had to be able to efficiently handle the high currents involved. Accordingly, the insulated gate bipolar transistor (hereinafter “IGBT”) was chosen as the switches for the full-bridge inverter. IGBTs were also chosen over MOSFETs due to their lower ON resistance, high-voltage applications (>1,000 V), high temperature tolerance (>100oC) and their relatively-constant saturation voltage of about 3 V, even when several hundred amps are flowing through the device. This makes for an inverter that offers high efficiency at high output currents. And although IGBTs have a slower turn on time than MOSFETs, the relatively low switching frequency of the PWM strategy to be employed (PWM frequency ≈ 2.5 kHz) can easily be handled by an IGBT.
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Transfer Switch The objective of the transfer switch is to do what its name implies: transfer the load from line power to backup power in the event that a parameter of the line power falls outside its tolerable limits. Actually, the transfer switch includes two switches, one for the line power and one for the backup power. From a design perspective, each switch must selectively conduct both the positive and negative halves of the output voltage waveform of either the line power or the inverter output. But it must also prevent feedback to the inactive voltage source from the active voltage source. Because of the selective nature of the transfer switch, the initial stages of the design process were focused on a fully-controllable switch such as a transistor. However, it wasn’t long before the fully-controllable nature of the transistor was viewed as a drawback. Fully controllable meant that the control circuitry would not only have to take action to turn the appropriate switch on, but it would also have to act to turn the switches off. This was seen as an unnecessary step that could complicate the control circuitry. Instead, the focus was turned towards semi-controllable switches that would automatically turn themselves off when appropriate. The first such switch considered was a triac. The triac was appealing because it was a single device that could controllably conduct both the positive and negative half of the voltage waveform. Unfortunately, the triac experiences difficulties turning off when connected to an inductive load, thus requiring a snubber circuit to improve its off performance. Although not overly complicated, the inclusion of a RC snubber circuit would unnecessarily complicate the transfer switch. 1 Finally, the triac for each switch was replaced with a complementary pair of silicon controlled rectifiers (“SCR’s”). The SCR pair was chosen because of its ability to automatically turn itself off when it becomes reverse biased without the aid of an auxiliary circuit. Selection of the appropriate SCR must satisfy the reverse-bias characteristics to prevent an avalanche breakdown from occurring, allowing backfeed to either the inverter or the utility. Control Circuit The decision making process to select the control strategy was the least iterative process of the of those to select the three primary components of the design. From the outset it was known that the design must react to its environment, yet be flexible to permit the designers to alter one or more hardware aspects of the UPS without having to redesign other hardware aspects. Hence, it was decided that the a microcontroller would
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Although research on “snubberless triacs” has improved the off performance of the triac, it is still not suitable to use such a device under all circumstances. The possibility of driving an inductive load with a UPS would preclude use of the snubberless triac until further advances are made.
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allow for the desired flexibility in the hardware design, if needed, and would efficiently handle generation of the PWM control signals needed to control the full-bridge inverter. To determine which microcontroller was best suited to control the different aspects of the UPS, the design team considered the demands that would be placed on the microcontroller. It must first and foremost be able to react to a disruption of line power and output the PWM control signals to generate the backup power. One PWM control signal would be needed for each pair of IGBT’s in the inverter, an analog input would be needed for analog-to-digital conversion of a utility-voltage signal, and a switching signal must be output for each pair of SCR’s that form the transfer switch. A microprocessor that offers all of these features was identified as the PIC18F452 produced by Microchip, Inc.
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ACCEPTED TECHNICAL DESIGN Introduction and Overall System Summary In summary of the discussion of alternative design analysis, the design group decided to design a UPS that generates backup power with a PWM, full-bridge inverter. A transfer switch comprising complementary SCR pairs will control whether the load is being supplied power from the utility or the inverter. Control of the entire UPS system will rest with the PIC18F452 microcontroller. The overall system schematic is shown in Figure 5 on the following page. The description of the overall system will be broken into the various major sub-components, beginning with the general description of the theory of operation, followed by a description of the power requirements, control circuit, inverter, and finally the transfer switch. The description of the accepted technical design will conclude with a section that harmonizes the sub-components into the complete system. In general, the UPS works on the following principle. During normal operation, the line power from the AC mains is delivered to the load as if the load was plugged directly into the AC mains. If a parameter of the line power, whether voltage or frequency, falls outside of a tolerable limit for that parameter, the control circuitry reacts to this condition and generates an AC voltage waveform from a battery. The DC battery voltage is inverted into a PWM waveform, which is then filtered with a low-pass filter to remove the switching harmonics. A phase-locked loop ensures that the phase of the voltage waveform from the inverter is reasonably close to the phase of the voltage waveform supplied by the AC mains. The resulting AC waveform is then stepped up to the desired voltage with a transformer before being delivered to the load through the action of the transfer switch. In the event that the line power is restored while backup power is being supplied, the control circuit must compare the phase of the voltage waveform from the inverter, and gradually correct it to closely resemble the phase of the voltage waveform from the AC mains. Once the phase of each voltage waveform approximately matches the other, the transfer switch is actuated to seamlessly return the load to the line power, and the inverter operation is discontinued. At all times, the control circuit is to provide an indication to the user about the status of the system and the battery life remaining. Displaying the system status is simply a matter of illuminating an LED corresponding to whether the load is running on line power or backup power. The battery life, however, is displayed by performing an analog-to-digital conversion (“ADC”) of the battery level, followed by displaying the results of the ADC on an eight-digit LED array.
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Figure 5. Overall UPS system block diagram
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Power Analysis The power calculations herein were based on an assumption of 100% efficiency, which is obviously not realistic. The design specifications call for a maximum power output of 1kW over a three-minute time interval using a 12 volt battery as the DC source. In DC analysis, power is simply the product of the voltage times current. Therefore, a battery at 12 volts must supply a current of 83 amps to achieve the 1 kW requirement. Batteries are rated based on amp-hours. This is the rate of current that can be sustained over a period of one hour. The power calculations were based on sustaining a load for only 1/2 hour. The design only calls for a peak run time of 3 minutes. This extra time allotted in the calculations adds a margin of performance to the system. A 12 volt deep cycle lead acid battery was selected having an amp-hr rating of 40. The selected battery will be of sufficient capacity to easily sustain such a power level without sustaining damage. The output form the PWM inverter is a 12 volt sine wave at 60 Hz. The resulting RMS signal is 8.5 Vac. The average power is the product of the RMS voltage and current. Again, to sustain a 1 kW load, an 8.5 Vac must carry 117.6 amps. Remember, this is an alternating current and voltage, not a direct current and voltage like the battery. The voltage is then stepped up using a transformer where it is transformed to a more common 120 AC voltage. At this voltage level, the current has a much lower value of 8.3 amps. The above power calculations were based on the devices operating at 100% efficiency. A simple way to think of this is power in equal’s power out. This most likely is not true. In electrical terms, inefficiency is generally associated with devices heating up. This is basically wasted energy. Figure 6 shows two possible scenarios for power utilization of the inverter. The first plot shows the required input power based on maintaining a 1kW load. As efficiency decrease the power demand grows rapidly placing more strain on the devices. Also, this increase may not be attainable, limited by the capacity of the battery and devices. The second plot shows the deteriorating effect a loss in efficiency has on performance. That is, as efficiency decreases so does the output power. At low efficiencies, the UPS system is a better heater that it is a power converter.
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Power Vs. Efficiency 10000 9000 8000
Power
7000 6000 5000 4000 3000 2000 1000 0 0%
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60% Effieciency
Required Input Pow er for 1k
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De-Rated Pow er Output 10%?
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Figure 8. Flow diagram illustrating process flow of the overall-system control scheme.
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ADCON1,2 = right justified ADC, channel 0 analog input CCP1 = PWM 2.5 kHz switching frequency CCP2 = PWM 2.5 kHz switching frequency TRISD=Line Power Output, Backup Power Input enable interrupts enter compatibility mode Listing 1. Initialization pseudocode. The interrupts enabled in Listing 1 will notify the microcontroller when the line power has been restored after a blackout has occurred. A voltage detection circuit is to output a voltage of approximately 4 V when the AC mains voltage once again falls within the tolerable voltage limits. This 4 V signal is input to a digital I/O pin of the microcontroller, triggering the interrupt. The interrupt routine is to initiate the synchronization of the backup power with the line power and actuate the transfer switch to return the load from the backup power to the line power when synchronization is complete. Then, the logic flow reenters the endless loop from where the line power is monitored until another disruption occurs. By entering compatibility mode, all interrupts are assigned the same priority. This means that all interrupts are high priority, and they will occur in the order in which their triggering events arise.
Endless Loop Once initialization is complete, the main( ) function enters the endless loop. From Figure 8, it is apparent that the endless loop repeatedly monitors the AC mains voltage to detect a voltage fault condition. The endless loop was designed to minimize the time in between successive checks of the AC mains voltage. Since time is critical in transferring the load to backup power following a disruption of line power, continually monitoring the line power will prevent a lengthy delay from happening before an outage is detected. Pseudocode for performing the monitoring function can be a simple if/then statement such as: again IF (line power = 0){ begin PWM( ) } ELSE goto again Listing 2. Line power monitoring routine.
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The statement “begin PWM” in Listing 2 calls the PWM subroutine that governs the PWM control signal to be output to the inverter. This corresponds to the step of controlling operation of the inverter in Figure 8. During normal operation of the UPS, the AC mains voltage is to be conducted directly to the load. A zero-crossing detector, shown in Figure 9, was designed by the design team to provide the microcontroller with a reference point with respect to the phase of the AC mains voltage when a power outage occurs. At each downward zero crossing of the AC mains voltage waveform there is a 4 V pulse at the output of the zero-crossing detector, as shown in Figure 10. The pulse is shut off at each upward zero crossing of the voltage waveform. A timer in the microcontroller is reset at each rising or falling edge of the pulse output by the zerocrossing detector. Thus, when a disruption of the AC mains voltage waveform is detected, the value of the timer since the last zero crossing is checked to give the microcontroller a rough idea of where the AC mains voltage waveform was when the disruption took place. In this manner, the PWM control signal can send the appropriate starting duty-cycle signal to the inverter, allowing the backup voltage waveform to pick up at approximately the same phase as the AC mains voltage waveform left off.
Figure 9. Zero-crossing detector.
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12V
8V
4V
0V
-4V
-8V
-12V 0s V(V1:+)
10ms V(R3:1)
20ms
30ms
40ms
50ms
60ms
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80ms
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Time
Figure 10. Simulation results for the zero-crossing detector. The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON) • TOSC • (TMR2 prescale value) This internal phase-locked loop will be implemented with the begin PWM( ) call referenced above in Listing 2. Again, the pseudocode is merely a series of if/then statements. The if statement will inquire into whether the timer is within a certain time frame, and if so, a corresponding duty cycle is sent to the CCPR1L register and to the CCP1CON bits. For example, consider the following pseudocode: if(1ms ≥ TMR3 ≥ 2ms) then {CCPR1L = 0B00001100; CCP1CON = 0B10;} else if(2ms ≥ TMR3 ≥ 3ms) then { CCPR1L = 0B10001011; CCP1CON = 0B01;} * * * Listing 3. Internal phase-locked loop pseudocode. Although the duty cycle of each pulse may vary to create a sinusoidal voltage waveform, the switching period remains constant. A switching frequency of 2.5 kHz was 7
selected to provide good resolution (i.e., number of pulses per cycle) and to minimize the filtering demands. As mentioned above, switching at a high frequency is beneficial because the significant harmonics that can affect the output waveform are very close to the switching frequency. Thus, to pass a voltage waveform at a frequency of 60 Hz, a low-pass filter with a corner frequency between 60 Hz and the switching frequency must be employed. Because the switching frequency is so much higher than 60 Hz, there is a considerable range of frequencies to choose from. As a rule of thumb, a corner frequency near the midway point between 60 Hz and 2.5 kHz was chosen to ensure proper filtering without incurring detrimental affects from the harmonics. The corner frequency of the low-pass filter was chosen to be 1 kHz. A detailed description of the filter design is set forth below. For a switching frequency of 2.5 kHz, the switching period is 0.0004 seconds. Likewise, for a 60 Hz sinusoidal waveform, the period is 1/60, or about 1.67E-2 seconds. A quarter wave is ¼ of that time, or 4.167E-3 seconds. Thus, there are 4.167E-3 / 0.0004 ≈ 10 PWM pulses per quarter cycle. The PWM control signal can be simulated by comparing a saw-tooth waveform with the sinusoidal waveform with the circuit shown in Figure 11, where V3 and V11 are the saw tooth voltage sources.
Figure 11. PWM control signal simulation.
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The comparison of the two waveforms in the simulation appeared as shown in Figure 12. The falling edge of each sawtooth begins a pulse, and the rising edge ends it. 20V
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-4V 0s V(U2:+)
1.0ms V(V3:+)
2.0ms
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8.0ms 8.5ms
Time
Figure 12. Comparator simulation. Finally, with the positive and negative circuits in Figure 11, the complete PWM control signal is shown in Figure 13 for a full cycle of a sinusoidal voltage waveform. Obviously, the control signal for the positive half cycle is input to one set of IGBT’s, while the control signal for the negative half cycle is input to the other set. 20V
10V
0V
-10V
-20V 0s V(R14:2)
2ms V(R12:2)
4ms
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8ms
V(U2:+) Time
Figure 13. Full PWM control signal.
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Inverter DC to AC inverters are widely used in many applications such as motor drives, and UPS’s. The full bridge inverter configuration shown in Figure 14 is frequently employed, wherein the power semiconductor switches, Q1 to Q4, can be controlled by a variety of Pulse Width Modulation (PWM) techniques. PWM control strategies involving either unipolar or bipolar switching are common since the harmonics of significant amplitude are pushed into the high frequency range near the switching frequency. As the switching frequency is increased, a high quality output voltage waveform can be more easily recovered by low-pass filtering.
Q1
Q3
V1 Low Pass Filter
Load
C
Q2
Q4
Figure 14. Full-Bridge Inverter During a typical turn-on or turn-off operation, the voltage across each power device remains near to the dc bus voltage for a significant portion of the switching transient, while a relatively large current is being commutated. Therefore, it was important to choose a switch that could efficiently handle the significantly high current. For this type of application, the IGBT was chosen. IGBTs are used for the H-Bridge rather than MOSFETs due to their lower ON resistance, high-voltage applications (>1,000V), high temperature tolerance (>100°C) and their saturation voltage is a relatively-constant 3 volts even when many hundreds of amperes are flowing through the device. This makes for an inverter which has high efficiency at high output currents. Although IGBTs have a slower turn on time than MOSFETs, the relatively low frequency of operation (PWM frequency = 20 kHz) make this property irrelevant. The IGBT has been chosen for this project is the SGF80N60UF which is manufactured by Fairchild semiconductor. The SGF80N60UF was chosen because it has low conduction and switching losses, high speed switching and low saturation voltage V CE ( sat ) = 2.1V @ I C = 40 A . With higher switching frequency it means more heat
dissipation. Assume all the wire connectors are rated about 75 0 C and will be working in an ambient temperature of 30 0 C . The thermal resistance is
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R= Where
ΔT
P
=
D
75 − 30 = 0.410 C / W 110
PD is the maximum power dissipation, ΔT is the change in temperature of a
maximum of 75 0 C and R is the thermal resistance. The thermal resistance should be below 1.1 0 C / W for the IGBTs working under normal conditions In order to optimize the turn on and turn off speed of IGBTs, the gate resistors R1 to R4 shown in Figure 2 must carefully choose. The values of these resistors determine the maximum amount of gate charging/discharging current and should ensure correct and safe commutation of the IGBT. For turn-on, the current required to charge the gate source capacitor C iss in the specified time can be calculated as
IP =
Q t
g
=
r
Where
Q
g
250nC = 7.14 A 35ns
is the IGBT gate charge and
t
r
is peak current for rise time.
The peak current for turn-off can be obtained in the same way as for turn-on, with the exception that peak current for fall time, t f , is substituted for t r
I
P
=
Q t
g
=
f
250nC = 7.14 A 35ns
The equivalent input gate emitter capacitance (the true capacitance seen by the drive during the commutation process) of the IGBT is next calculated as
C
in
=
Q ΔV
g
where
ΔV
gate
= V gate ( on ) − V gate ( off ) = 20 − (−20) = 40V
gate
+ 20 V, Q = 250 nC, g − IGBT part # SGF80N60UF and the drive HIP4080
The values V gate ( on ) = V gate ( off ) =
t
f
=
t
r
= 35 ns come from the
The total power used to for driving the IGBT is P = f(Khz) *
C
in
*
ΔV
2 gate
= 2.5Khz * 250nC * 40V = 0.025 W
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The turn – on gate resistor will be selected:
R
gate ( on )
=
V
gate ( on )
I
=
P
20V = 2.8Ω 7.14 A
The turn – off gate resistor for turn off can be obtained in the same way as the turn on gate resistor.
R
gate ( off )
=
V
gate ( off )
I
P
=
20V = 2.8Ω 7.14 A
Inverter control signals connect the PIC18F452 and the inverter through the IGBT driver. The driver has been chosen for this project is the HIP4080, which is manufactured by Intersil. The HIP4080 was chosen because of its high frequency and ability to operate from 8VDC to 80VDC busses for driving IGBTs H-Bridge. Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-time which can be adjusted to near zero minimize distortion, resulting in precise control of the driven load. The HIP4080 has built a combination of bootstrap and charge-pumping techniques is used to power the circuitry which drives the upper IGBTs of the H-Bridge. The bootstrap technique supplies the high instantaneous current needed for turning on the power devices, while the charge pump provides enough current to maintain bias voltage on the upper driver section of IGBTs. The pin 8 (HEDL) and pin 9 (LEDL) are high-side and low-side turn on delay. Connect resistor from this pin to pin 4 (VSS) to set timing current that defines the turn-on delay of both high and low side drivers. Intersil recommends using R5 and R6 ranging from 10k to 100k. Base on the typical performance curve from the HIP4080 data sheet, the value of R5 = R6 = 50k was selected. The two bootstrap capacitors, C1 and C2, and the high voltage bus bypass capacitors are 0.1 uF, 100V ceramic. Ceramic is used here because of the low inductance required of these capacitors in this design. The two bootstrap diodes, D1 and D2, are 1A, 100V fast recovery to minimize the charge loss from the bootstrap capacitors when the diodes become reverse-biased. The HIP4080 is powered by 12 VDC to VCC (pin 15) and VDD (pin 16). VCC, VDD are positive supply to gate drivers and positive supply to lower gate drivers. For this design VCC and VDD ties together and connect to anodes of two bootstrap diodes D1 and D2. The input signals from the PIC18F452 enter to HEN (pin 2), IN + and IN- . Logic level input that when low overrides IN+/IN- (pin 6 and 7) to put AHO and BHO drivers (pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- . The pin can be driven by signal has a range 0V to 15V.
12
R3
2.8 Ohm
Q4 IGBT 2.8 Ohm
Q2 IGBT
R5 50 k 50 k
R6
D2
D1
12 V
C2 0.1 uF
15 16 VCC 4 VDD VSS
10 1 AHB BHB
19 17 BHS BLS
12 14 AHS ALS
3 2 DIS HEN
20 BHO 18 BLO
8 9 HDEL LDEL
11 AHO 13 ALO
R2
2.8 Ohm OUT
6 7 IN+ IN-
HIP4080
5
R1
Q1 IGBT
R4
2.8 Ohm
Q3 IGBT 12 V
C 1 0 .1 u F
Figure 15. Inverter-Driver Circuit Schematic
The selected inverter design was simulated using PSpice. The basic full bridge inverter was assembled and driven with the PWM control signal discussed above. Figure 16 shows the devices used to simulate the inverter portion of the design.
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Figure 16. PWM and Inverter Simulation Schematic
The resulting output signal shown in Figure 17 shows the required PWM signal operating at 2.5 kHz. Also, the resulting waveform is at the 12 Vdc level super imposed over a 60Hz sine wave. 20V
10V
0V
-10V
-20V 0s V(R47:2)
2ms V(Vupper,Vlower)
4ms
6ms
8ms
10ms
12ms
14ms
Time
Figure 17. PWM Output Signal
The next logical step in simulation was to implement the filter required to generate the 60 Hz output signal. The filter design selected was a LC low pass filter. This filter would block the higher frequencies. The filter is shown in Figure 18.
Figure 18. LC Low Pass Filter
14
16ms
17ms
The filter parameters depend on two components; an inductor and a capacitor. Each component needs to be properly specified and selected. A cutoff frequency of 1 kHz was selected. This would filter out the higher frequencies of the PWM signal and allow the production of a smooth sine wave. The value R is the impedance seen by inverter. At full load this value is .07 Ohms. The following equations were used to calculate the values for the filter. The resulting transfer function of the filter is found in Equation III. R L= 2 * π * fo Equation I: Inductor Calculation
C=
1 2 * π * R * fo
Equation II: Capacitor Calculation
G ( s) =
1 LCs 2 + s
L +1 R
=
5.995x10
-006
1 s + 0.002449 s + 1 2
Equation III: Filter Transfer Function
The transfer function was then simulated in Matlab to show its filtering capabilities. Figure 19 shown the cutoff frequency at 1 kHz.
Figure 19. Bode Magnitude Plot of Filter
15
The filter was then simulated in pSpice using the circuit in Figure 16 designed for PWM simulation. The resulting output signal from the filter was captured. The output waveform is a 12 volt sinusoid with a frequency of 60 Hz, shown in Figure 20. 20V 18V 16V 14V 12V 10V 8V 6V 4V 2V 0V -2V -4V -6V -8V -10V -12V -14V -16V -18V -20V 0s
10ms V(L9:2,C9:1)
20ms
30ms
40ms
50ms
60ms
70ms
80ms
90ms
100ms
Time
Figure 20. Filtered PWM Sinusoid Output Signal
The final portion of the design to be simulated is the step-up transformer used to convert the 12 volt signal to a 170 volts signal. Figure 21 shows a simple step-up circuit. A 12 volt AC source is fed through a transformer having a turns ratio of .072. This is the ratio of the primary windings to the secondary windings. The load modeled in the impedance seen at the full load of 1 kW.
Figure 21. Transformer & Load Simulation
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200
200
100
100
0 0
-100 -100
-200 0s
10ms I(R4) V(V3:+)
20ms
30ms
40ms
50ms
60ms
70ms
80ms
90ms
100ms
-200 0s
Time
50ms
100ms
150ms
200ms
250ms
V(R2:2) -I(R2) Time
Figure 22. Transformer Input & Output Voltage and Currents
The transformer simulation of figure 22 shows exactly what is to be expected form the circuit. The input is a low voltage, high current signal. The output is a high voltage, low current signal.
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TESTING PROCEDURES 1.
Preliminary Inspection – Following computer simulation and construction of the UPS and its individual components, an initial, visual inspection of the device shall be conducted to ensure against any assembly errors. Further, the separate components that collectively makeup the UPS are to be energized individually to prevent unexpected performance of one component from damaging others.
2.
Control – Proper operation of the software routines embedded in the microprocessor responsible for coordinating the interaction of the individual components of the UPS will be confirmed. First, the microprocessor will be installed on a developmental board and programmed to generate two PWM control signals, one to control the switching of each set of IGBTs that form the inverter. Each PWM waveform will be captured using the oscilloscope. Next, the microprocessor will be required to monitor an input signal that simulates electric power supplied by a utility. Various disruptions of the input signal will be induced to represent disturbances of utility-supplied power, and the microprocessor’s ability to activate the static transfer switch will be monitored using the oscilloscope. After the proper operation of both functions has been confirmed, the microprocessor will be required to control operation of both the inverter and static transfer switch in response to simulated power disruptions in real time.
3.
Circuit Protection – Protective measures built into the UPS design will be tested to minimize cascading damage to any system components in the event that the behavior of the assembled system or any individual component differs from the simulated behavior.
4.
Circuit Operation – Gate-triggering signals will be applied to each SCR in the transfer switch as well as to each IGBT in the inverter to ensure that each component is operational.
5.
System Performance – Following testing of each individual component, the system as a whole will be subjected to a variety of test conditions. Both the input and output voltage waveforms will be monitored to ensure that the output voltage is approximately a 120 V, 60 Hz voltage waveform regardless of disruptions in utility-supplied electric power.
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FINANCIAL BUDGET
Design Team Member
Hourly Rate
Don Fisher Dung Nguyen Don Firca
$10.00 $10.00 $10.00
Estimated Hour Requirement 320 320 320
Labor Subtotal Part PIC18F452 Microprocessor Silicon Controlled Rectifier (“SCR”) SCR Driver Insulated Gate Bipolar Transistor (“IGBT”) IGBT Driver Pulse Transformer Step-Up Transformer 12V, 5+ mAH Sealed, Lead-Acid Battery Battery Charger 10-Segment LED Array 2-Segment LED Array Miscellaneous
Estimated Labor Cost $3,200 $3,200 $3,200 $9,600.00
Quantity 1 4 1 4
Price per Unit $6.00 $1.25 $1.00 16.50
Total Cost $6.00 $5.00 $1.00 $66.00
1 8 1 2
$1.00 $10.00 $50.00 $30.00
$1.00 $80.00 $50.00 $60.00
1 1 1 N/A
$25.00 $2.00 $1.00 N/A
$25.00 $2.00 $1.00 $25.00
Materials Subtotal Total
$322.00 $9,922.00 1
1
DESIGN TEAM INFORMATION TEAM: D3 ENGINEERING FACULTY ADVISOR Professor Malik E. Elbuluk, D.Sc., P.E.
TEAM MEMBERS Don Fisher – ECE - Project Manager Don Firca – ECE - Microprocessor Specialist Dung Nguyen – ECE - Electronic Hardware Engineer Special Thanks Dr. James Grover – Microprocessor Guru
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Project Design Report
Design Team #6 Donald J. Firca, Jr. Donald J. Fisher Jr. Dung Nguyen
Faculty Advisor: Dr. Malik Elbuluk
Submitted December 5, 2005
TABLE OF CONTENTS ABSTRACT ........................................................................................................................... 2 INTRODUCTION .................................................................................................................... 3 Statement of Need…………………………………………………………………3 Problem Definition………………………………………………………...………3 DESIGN SPECIFICATIONS……………………………………………………………...……4 ALTERNATIVE DESIGN ANALYSIS …………………………………………………………7 Overall System Design …………………………………………………………...7 Individual Component Design - Hardware ……………………………...………10 ACCEPTED TECHNICAL DESIGN ……………………………………………………….…14 Introduction and Overall System Summary……………………………………..14 Power Analysis…………………………………………………………………..16 Control Circuit..………………………………………………………………....18 Hardware ………………………………………………………………………………..18 Control Scheme ………………………………………………………………................19 Inverter …………………………………………………………………………..26 TESTING PROCEDURES …………………………………………………………………..34 FINANCIAL BUDGET ……………………………………………………………………..35 Design Team Information ……………………………………………………………
1
37
ABSTRACT An uninterruptible power supply for providing backup power in the event of a disruption in the utility-supplied power. A microcontroller controls the operation of the various components and generates a pulse-width modulation control signal. When a disruption of the utility power occurs, the microcontroller detects such an event, activates the pulse-width-modulation inverter, and seamlessly transfers the load from utilitysupplied power to backup power. Backup power of 1 kW for approximately three minutes will provide a user with time to save unsaved data on a desktop PC and properly shut it down.
2
INTRODUCTION Statement of Need: As the general population continues to grow, there is an ever-increasing demand for electricity placed on the world’s power-generation and distribution facilities. Although significant measures are taken to ensure a reliable supply of electric power, the significant demand for power increases the likelihood that power outages and other electrical disruptions such as brownouts will occur. Uninterruptible power supplies (hereinafter “UPS”) that currently exist offer users extended periods of backup power during which they can continue to use electronic equipment such as a personal computer. However, such UPS’s are expensive and can be priced up to several hundreds of dollars. Further, the extended periods of backup power are typically not needed by users because other electronic equipment such as lights, a cable/DSL modem and printer, and other office equipment required by users to perform work on the PC are not available. Problem Definition: Goals: • • • • •
Provide backup power to a PC and light in the event of a power outage. Limit the duration of backup power to a suitable length to permit a user of the PC to save unsaved data and properly shut the PC down. Warn a user of an impending expiration of the backup power during a power outage. Seamlessly return the user’s PC and light to electric power supplied by the utility in the event power is restored before the expiration of backup power occurs. Clearly indicate to the user the status of the system.
Objectives: • • • • •
Detect the occurrence of a power outage and transfer the load from utility power to backup power rapidly enough to prevent loss of unsaved data on a PC. Provide backup power of 1 kW for a duration of 3 minutes. Sound an audible warning to the user to indicate approximately 30 seconds of backup power remaining. Synchronize phase of backup power with that of utility power if the utility power is restored while backup power is being supplied. Visually display the approximate battery level and the system status.
Constraints: •
Transfer the load from utility power to backup power within 4 ms upon the occurrence of a power outage. 3
•
• •
Must approximately match the phase of the backup power to that of the utility power just prior to the disruption of utility power to minimize the effect on the load stemming from significant phase differences. Must provide backup power for a suitable period of time to allow the user to save unsaved data on the PC and properly shut it down. The overall cost of the prototype unit must be within the budgeted $300 to minimize the cost of each mass-produced unit, which is preferably under $75.
DESIGN SPECIFICATIONS •
Detect the occurrence of a power outage and transfer the load from utility power to backup power rapidly enough to prevent loss of unsaved data on a PC. Research revealed that the universally-accepted safe harbor for restoring the supply of power to a sensitive load such as a PC is 4 ms, with 5 ms being the absolute maximum allowable time frame. To offer a response within this time frame, a low-voltage detector is to be provided to output a blackout signal to the microcontroller in the event of a complete loss of utility-supplied power (referred to herein as “line power”). Similarly, voltage fluctuations of a lesser degree, commonly called brownouts, will also be followed by the transmission of a brownout signal to the microcontroller. The blackout and brownout signals are represented by varying voltage levels of the respective signals transmitted to the microcontroller. Disturbances of the line-power frequency are to be detected and compensated for by converting the frequency of the line power to a voltage level with a frequency-to-voltage converter. Again, a frequency fault signal is to be output to the microcontroller in the form of a voltage level different from that of the signals discussed above. A balance must be struck by establishing tolerable limits for each of the fault conditions to prevent the unnecessary, repeated operation of the UPS, but to also ensure proper operation of the UPS when the intolerable fault conditions actually exist. Line-power voltage disturbances of ±10% and frequency disturbances of ± 1Hz for three consecutive cycles were determined to allow for proper operation of the UPS, without exposing the connected load to significant risk of damage.
•
Provide backup power of 1 kW for a duration of 3 minutes.
4
The power rating of an average Pentium™ 4 PC running the Windows XP operating system is approximately 385 W. Likewise, an average CRT monitor has a power rating of about 220 W while a 100 W light bulb obviously consumes approximately 100 W of power. Combined, this amounts to 705 W of required power. The remaining 295 W of power allows for system expansion or prolonged backup running times in the event that the system remains as is. When the load is transferred from line power to the backup power supplied by the UPS, the phase of the voltage waveform generated by the UPS must be similar to that of the line power when the power disruption occurred. Drastically mismatched voltage phases can damage the load. Thus, the microcontroller is to implement an internal phase-locked loop to ensure that the phase of the backup voltage waveform is approximately the same as the phase of the line voltage waveform immediately prior to the disruption of line power. •
Sound an audible warning to the user to indicate approximately 30 seconds of backup power remaining. Assuming a backup running time of approximately 3 minutes, 10% of the backup running time would equal 18 seconds. Feeling that 18 seconds was too short of a warning period during which a user can save unsaved data and shutdown the PC, the designers decided to provide a warning sound at 30 seconds prior to exhaustion of the system’s batteries.
•
Synchronize phase of backup power with that of utility power if the utility power is restored while backup power is being supplied. If a temporary disruption of line power occurs, then the line power can possibly be restored during operation of the UPS. In such a case, the UPS is to sense the return of line power and gradually modulate the phase of the backup voltage waveform until it matches the phase of the line voltage waveform. Only when the two phases are reasonably close will the microcontroller actuate the transfer switch to seamlessly return the load to the line power.
•
Visually display the approximate battery level and the system status. Among the microcontroller’s duties will be controlling a display that will indicate to the user the status of the system, i.e., whether line power or backup power is being supplied, and the strength of the battery bank. A
5
dual LED display will be implemented to indicate system status while an 8-digit LED bar graph will display the battery level from a scale of zero to seven. A scale consisting of 8 digits provides a reasonable resolution that can be easily viewed and grasped by the user. And although the analogto-digital converter of the microcontroller that was selected can operate in a 10-bit mode, three bits are all that are necessary to display the eight possible battery-level states (i.e., 23=8).
6
ALTERNATIVE DESIGN ANALYSIS Overall System Design From the perspective of the overall UPS system, the first design step was to select a system-wide topology for implementing the UPS. There are primarily three different UPS topologies from which to choose, each having its own advantages and disadvantages. The first topology considered was the topology that is commonly referred to as “passive standby,” or “off-line,” which is shown below in Figure 1. Basically, the passive-standby UPS supplies the AC input voltage directly to the load when it is available, bypassing the backup power portion of the UPS. When a disruption of the AC input voltage occurs, the DC voltage waveform from the battery is inverted by an inverter into an AC output voltage waveform approximately the same as that of the AC input voltage. A transfer switch is provided to selectively control which AC output voltage waveform is delivered to the load: the AC input supplied by the utility, or the AC output waveform from the inverter.
Figure 1. Passive-standby, or off-line UPS topology. The passive-standby UPS offers the advantages of a simple design, relatively small size and low cost. However isolation of the load from the upstream distribution system and line power is limited at best, and should only be used for applications with power ratings less than 2 kVA. And for critical loads such as corporate computer centers,
7
medical applications and telephone exchanges, the time required to transfer the load from line power to that from the inverter can be unacceptably long. And while the passivestandby UPS offers suitable protection from loads like home computers, there is no output voltage or output frequency regulation. Next, the line-interactive UPS topology shown schematically in Figure 2 was considered. According to this topology, the inverter is connected to the load parallel to the AC input voltage from the utility. When line power is being delivered, the inverter is also operational to charge the battery and to condition the line power. If a disruption to the line power occurs, the battery/inverter combination maintain continuity of power to the load. Once this occurs, the static transfer switch is opened to prevent power from the inverter from being introduced to the line-power distribution system.
STATIC SWITCH AC INPUT LOAD
INVERTER
BATTERY
Figure 2. Line-interactive UPS topology. The advantage of the liner-interactive UPS topology is that transferring the load from line power to backup power is almost instantaneous since the backup power is generated in parallel with the line power. Thus, the load sees a seamless transition. However, like the passive-standby UPS topology, the line-interactive topology suffers from a lack of isolation of the load from the line power, including all spikes and overvoltages. Further, there is no regulation of the output frequency since the output frequency depends on the frequency of the line power, which is a primary reason why this type of UPS is typically not used for sensitive loads with high power ratings.
8
The third and final topology considered was the double-conversion UPS topology shown below in Figure 3. According to this topology, the inverter is connected in series between the AC line-power input and the load. The inverter is operational regardless of whether line power is available. When line power is available, the AC input voltage waveform is rectified, the rectified DC waveform is inverted, and the inverted AC waveform is then supplied to the load. If the line power is disrupted, or otherwise falls outside of the tolerable limits of the load, the battery power is inverted and supplied to the load. Since the battery is parallel with the line-power input, the transition from line power to backup power is seamless. Additionally, there is a static bypass switch that allows line power to bypass the inverter and be delivered directly to the load as desired.
Figure 3. Double-conversion UPS topology. This configuration offers many advantages over those topologies discussed above. Primary among those advantages is that the double-conversion UPS offers isolation to the load from upstream voltage disruptions in the AC input voltage waveform. Thus, voltage spikes and over voltages in the AC input waveform are not transmitted through to the load. Further, since all AC output voltage waveforms (during normal operation) are generated by the inverter, this topology allows for precise control and fine tolerances. For these reasons, the double-conversion UPS topology is used almost universally for critical and high-power-rating applications requiring 10 kVA and up. To offer all these advantages, however, the double-conversion topology is relatively complex and very expensive.
9
After weighing the various advantages and disadvantages of each of these topologies, it was concluded that the passive-standby UPS topology would be pursued. First, its relative simplicity will allow for the research and development of such a UPS to be completed within the budget constraints imposed. And second, its widespread adoption for applications with power ratings equal to or less than 2 kVA coincide with the application for which it is being designed.
Individual Component Design - Hardware Once the passive-standby topology was selected, the next step was to determine how best to implement the design. From Figure 1, it can be seen that a passive standby UPS includes three primary components: the rectifier/charger, inverter and transfer switch. In addition to these illustrated components, the control circuitry must also be considered. For purposes of the design, the members of the design team focused their efforts on designing the inverter, transfer switch, and control circuit. The remaining components, such as the rectifier/charger and the DC/DC converter necessary for providing the desired power supply to the microcontroller are to be purchased as discrete components according to the specified design parameters. Inverter For the inverter, a number of configurations and control routines were considered before settling on a full-bridge inverter controlled according to pulse-width modulation (“PWM”) with a switching frequency of 2.5 kHz. It was first determined that a sine wave output waveform was desired as opposed to quasi sine or square wave waveforms. Sine waves bear the closest resemblance to the actual voltage waveforms produced by the AC mains, which requires less filtering and is less likely to damage the load to which it is delivered. Although sine wave output is closest to replicating the AC mains supply, it is also likely to be the most costly and least efficient. In contrast, a square wave is the cheapest, and probably the most efficient, but it is also the most likely to cause operational problems due to its non-sinusoidal waveform. The quasi-sine wave is an intermediate waveform, which can replicate the key characteristics of a true sine wave if properly controlled. But the advantages in filtering and powering the load make the sine wave the most-ideal candidate for the UPS. Constant-voltage transformers (“CVT's”) have traditionally been the method of generating a pure sine wave, and they include large transformers in which an oscillation is established. Although they are simple devices and are relatively durable, they tend to be inefficient, large and heavy, and sometimes very noisy. Further, there is a tendency for the waveform to become severely distorted when delivered to certain types of loads. In contrast, a series of switches can be employed along with a PWM switching strategy to replicate a pure sine wave. Despite being more complex than a CVT, a PWM
10
inverter is relatively small and light, making it an ideal DC to AC inverter option. Additionally, PWM control strategies involve either unipolar or bipolar switching, and push the harmonics having significant amplitudes into the high frequency range near the PWM switching frequency. As the switching frequency is increased, a high quality output voltage waveform can be more easily recovered by low-pass filtering. The higher the switching frequency, the less stringent are the demands placed on the low-pass filter. For a switching frequency of 2.5 kHz, the corner frequency of an acceptable low-pass filter can be between 60 Hz and 2.5 kHz since the desired output waveform is approximately 60 Hz. The full-bridge topology, shown below in Figure 4, is such a configuration of switches and was chosen to generate the sine wave voltage waveform. Other topologies, such as the half-bridge inverter, exist but offer efficiencies approximately half that offered by the full-bridge inverter. The increased efficiency over the half-bridge inverter is attainable without significantly adding to the complexity or cost of the device.
Q1
Q3
V1 Low Pass Filter
Load
C
Q2
Q4
Figure 4. Full-bridge inverter configuration. With regard to the individual components chosen for the full-bridge inverter in Figure 4, the voltage across each power device remains close to the DC bus voltage for a significant portion of the switching transient, while a relatively large current is being commutated during a typical turn-on or turn-off operation. Therefore, the switch chosen for implementing the full-bridge inverter had to be able to efficiently handle the high currents involved. Accordingly, the insulated gate bipolar transistor (hereinafter “IGBT”) was chosen as the switches for the full-bridge inverter. IGBTs were also chosen over MOSFETs due to their lower ON resistance, high-voltage applications (>1,000 V), high temperature tolerance (>100oC) and their relatively-constant saturation voltage of about 3 V, even when several hundred amps are flowing through the device. This makes for an inverter that offers high efficiency at high output currents. And although IGBTs have a slower turn on time than MOSFETs, the relatively low switching frequency of the PWM strategy to be employed (PWM frequency ≈ 2.5 kHz) can easily be handled by an IGBT.
11
Transfer Switch The objective of the transfer switch is to do what its name implies: transfer the load from line power to backup power in the event that a parameter of the line power falls outside its tolerable limits. Actually, the transfer switch includes two switches, one for the line power and one for the backup power. From a design perspective, each switch must selectively conduct both the positive and negative halves of the output voltage waveform of either the line power or the inverter output. But it must also prevent feedback to the inactive voltage source from the active voltage source. Because of the selective nature of the transfer switch, the initial stages of the design process were focused on a fully-controllable switch such as a transistor. However, it wasn’t long before the fully-controllable nature of the transistor was viewed as a drawback. Fully controllable meant that the control circuitry would not only have to take action to turn the appropriate switch on, but it would also have to act to turn the switches off. This was seen as an unnecessary step that could complicate the control circuitry. Instead, the focus was turned towards semi-controllable switches that would automatically turn themselves off when appropriate. The first such switch considered was a triac. The triac was appealing because it was a single device that could controllably conduct both the positive and negative half of the voltage waveform. Unfortunately, the triac experiences difficulties turning off when connected to an inductive load, thus requiring a snubber circuit to improve its off performance. Although not overly complicated, the inclusion of a RC snubber circuit would unnecessarily complicate the transfer switch. 1 Finally, the triac for each switch was replaced with a complementary pair of silicon controlled rectifiers (“SCR’s”). The SCR pair was chosen because of its ability to automatically turn itself off when it becomes reverse biased without the aid of an auxiliary circuit. Selection of the appropriate SCR must satisfy the reverse-bias characteristics to prevent an avalanche breakdown from occurring, allowing backfeed to either the inverter or the utility. Control Circuit The decision making process to select the control strategy was the least iterative process of the of those to select the three primary components of the design. From the outset it was known that the design must react to its environment, yet be flexible to permit the designers to alter one or more hardware aspects of the UPS without having to redesign other hardware aspects. Hence, it was decided that the a microcontroller would
1
Although research on “snubberless triacs” has improved the off performance of the triac, it is still not suitable to use such a device under all circumstances. The possibility of driving an inductive load with a UPS would preclude use of the snubberless triac until further advances are made.
12
allow for the desired flexibility in the hardware design, if needed, and would efficiently handle generation of the PWM control signals needed to control the full-bridge inverter. To determine which microcontroller was best suited to control the different aspects of the UPS, the design team considered the demands that would be placed on the microcontroller. It must first and foremost be able to react to a disruption of line power and output the PWM control signals to generate the backup power. One PWM control signal would be needed for each pair of IGBT’s in the inverter, an analog input would be needed for analog-to-digital conversion of a utility-voltage signal, and a switching signal must be output for each pair of SCR’s that form the transfer switch. A microprocessor that offers all of these features was identified as the PIC18F452 produced by Microchip, Inc.
13
ACCEPTED TECHNICAL DESIGN Introduction and Overall System Summary In summary of the discussion of alternative design analysis, the design group decided to design a UPS that generates backup power with a PWM, full-bridge inverter. A transfer switch comprising complementary SCR pairs will control whether the load is being supplied power from the utility or the inverter. Control of the entire UPS system will rest with the PIC18F452 microcontroller. The overall system schematic is shown in Figure 5 on the following page. The description of the overall system will be broken into the various major sub-components, beginning with the general description of the theory of operation, followed by a description of the power requirements, control circuit, inverter, and finally the transfer switch. The description of the accepted technical design will conclude with a section that harmonizes the sub-components into the complete system. In general, the UPS works on the following principle. During normal operation, the line power from the AC mains is delivered to the load as if the load was plugged directly into the AC mains. If a parameter of the line power, whether voltage or frequency, falls outside of a tolerable limit for that parameter, the control circuitry reacts to this condition and generates an AC voltage waveform from a battery. The DC battery voltage is inverted into a PWM waveform, which is then filtered with a low-pass filter to remove the switching harmonics. A phase-locked loop ensures that the phase of the voltage waveform from the inverter is reasonably close to the phase of the voltage waveform supplied by the AC mains. The resulting AC waveform is then stepped up to the desired voltage with a transformer before being delivered to the load through the action of the transfer switch. In the event that the line power is restored while backup power is being supplied, the control circuit must compare the phase of the voltage waveform from the inverter, and gradually correct it to closely resemble the phase of the voltage waveform from the AC mains. Once the phase of each voltage waveform approximately matches the other, the transfer switch is actuated to seamlessly return the load to the line power, and the inverter operation is discontinued. At all times, the control circuit is to provide an indication to the user about the status of the system and the battery life remaining. Displaying the system status is simply a matter of illuminating an LED corresponding to whether the load is running on line power or backup power. The battery life, however, is displayed by performing an analog-to-digital conversion (“ADC”) of the battery level, followed by displaying the results of the ADC on an eight-digit LED array.
14
Figure 5. Overall UPS system block diagram
15
Power Analysis The power calculations herein were based on an assumption of 100% efficiency, which is obviously not realistic. The design specifications call for a maximum power output of 1kW over a three-minute time interval using a 12 volt battery as the DC source. In DC analysis, power is simply the product of the voltage times current. Therefore, a battery at 12 volts must supply a current of 83 amps to achieve the 1 kW requirement. Batteries are rated based on amp-hours. This is the rate of current that can be sustained over a period of one hour. The power calculations were based on sustaining a load for only 1/2 hour. The design only calls for a peak run time of 3 minutes. This extra time allotted in the calculations adds a margin of performance to the system. A 12 volt deep cycle lead acid battery was selected having an amp-hr rating of 40. The selected battery will be of sufficient capacity to easily sustain such a power level without sustaining damage. The output form the PWM inverter is a 12 volt sine wave at 60 Hz. The resulting RMS signal is 8.5 Vac. The average power is the product of the RMS voltage and current. Again, to sustain a 1 kW load, an 8.5 Vac must carry 117.6 amps. Remember, this is an alternating current and voltage, not a direct current and voltage like the battery. The voltage is then stepped up using a transformer where it is transformed to a more common 120 AC voltage. At this voltage level, the current has a much lower value of 8.3 amps. The above power calculations were based on the devices operating at 100% efficiency. A simple way to think of this is power in equal’s power out. This most likely is not true. In electrical terms, inefficiency is generally associated with devices heating up. This is basically wasted energy. Figure 6 shows two possible scenarios for power utilization of the inverter. The first plot shows the required input power based on maintaining a 1kW load. As efficiency decrease the power demand grows rapidly placing more strain on the devices. Also, this increase may not be attainable, limited by the capacity of the battery and devices. The second plot shows the deteriorating effect a loss in efficiency has on performance. That is, as efficiency decreases so does the output power. At low efficiencies, the UPS system is a better heater that it is a power converter.
1
Power Vs. Efficiency 10000 9000 8000
Power
7000 6000 5000 4000 3000 2000 1000 0 0%
20%
40%
60% Effieciency
Required Input Pow er for 1k
80%
100%
De-Rated Pow er Output 10%?
N
Figure 8. Flow diagram illustrating process flow of the overall-system control scheme.
4
ADCON1,2 = right justified ADC, channel 0 analog input CCP1 = PWM 2.5 kHz switching frequency CCP2 = PWM 2.5 kHz switching frequency TRISD=Line Power Output, Backup Power Input enable interrupts enter compatibility mode Listing 1. Initialization pseudocode. The interrupts enabled in Listing 1 will notify the microcontroller when the line power has been restored after a blackout has occurred. A voltage detection circuit is to output a voltage of approximately 4 V when the AC mains voltage once again falls within the tolerable voltage limits. This 4 V signal is input to a digital I/O pin of the microcontroller, triggering the interrupt. The interrupt routine is to initiate the synchronization of the backup power with the line power and actuate the transfer switch to return the load from the backup power to the line power when synchronization is complete. Then, the logic flow reenters the endless loop from where the line power is monitored until another disruption occurs. By entering compatibility mode, all interrupts are assigned the same priority. This means that all interrupts are high priority, and they will occur in the order in which their triggering events arise.
Endless Loop Once initialization is complete, the main( ) function enters the endless loop. From Figure 8, it is apparent that the endless loop repeatedly monitors the AC mains voltage to detect a voltage fault condition. The endless loop was designed to minimize the time in between successive checks of the AC mains voltage. Since time is critical in transferring the load to backup power following a disruption of line power, continually monitoring the line power will prevent a lengthy delay from happening before an outage is detected. Pseudocode for performing the monitoring function can be a simple if/then statement such as: again IF (line power = 0){ begin PWM( ) } ELSE goto again Listing 2. Line power monitoring routine.
5
The statement “begin PWM” in Listing 2 calls the PWM subroutine that governs the PWM control signal to be output to the inverter. This corresponds to the step of controlling operation of the inverter in Figure 8. During normal operation of the UPS, the AC mains voltage is to be conducted directly to the load. A zero-crossing detector, shown in Figure 9, was designed by the design team to provide the microcontroller with a reference point with respect to the phase of the AC mains voltage when a power outage occurs. At each downward zero crossing of the AC mains voltage waveform there is a 4 V pulse at the output of the zero-crossing detector, as shown in Figure 10. The pulse is shut off at each upward zero crossing of the voltage waveform. A timer in the microcontroller is reset at each rising or falling edge of the pulse output by the zerocrossing detector. Thus, when a disruption of the AC mains voltage waveform is detected, the value of the timer since the last zero crossing is checked to give the microcontroller a rough idea of where the AC mains voltage waveform was when the disruption took place. In this manner, the PWM control signal can send the appropriate starting duty-cycle signal to the inverter, allowing the backup voltage waveform to pick up at approximately the same phase as the AC mains voltage waveform left off.
Figure 9. Zero-crossing detector.
6
12V
8V
4V
0V
-4V
-8V
-12V 0s V(V1:+)
10ms V(R3:1)
20ms
30ms
40ms
50ms
60ms
70ms
80ms
90ms
100ms
Time
Figure 10. Simulation results for the zero-crossing detector. The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON) • TOSC • (TMR2 prescale value) This internal phase-locked loop will be implemented with the begin PWM( ) call referenced above in Listing 2. Again, the pseudocode is merely a series of if/then statements. The if statement will inquire into whether the timer is within a certain time frame, and if so, a corresponding duty cycle is sent to the CCPR1L register and to the CCP1CON bits. For example, consider the following pseudocode: if(1ms ≥ TMR3 ≥ 2ms) then {CCPR1L = 0B00001100; CCP1CON = 0B10;} else if(2ms ≥ TMR3 ≥ 3ms) then { CCPR1L = 0B10001011; CCP1CON = 0B01;} * * * Listing 3. Internal phase-locked loop pseudocode. Although the duty cycle of each pulse may vary to create a sinusoidal voltage waveform, the switching period remains constant. A switching frequency of 2.5 kHz was 7
selected to provide good resolution (i.e., number of pulses per cycle) and to minimize the filtering demands. As mentioned above, switching at a high frequency is beneficial because the significant harmonics that can affect the output waveform are very close to the switching frequency. Thus, to pass a voltage waveform at a frequency of 60 Hz, a low-pass filter with a corner frequency between 60 Hz and the switching frequency must be employed. Because the switching frequency is so much higher than 60 Hz, there is a considerable range of frequencies to choose from. As a rule of thumb, a corner frequency near the midway point between 60 Hz and 2.5 kHz was chosen to ensure proper filtering without incurring detrimental affects from the harmonics. The corner frequency of the low-pass filter was chosen to be 1 kHz. A detailed description of the filter design is set forth below. For a switching frequency of 2.5 kHz, the switching period is 0.0004 seconds. Likewise, for a 60 Hz sinusoidal waveform, the period is 1/60, or about 1.67E-2 seconds. A quarter wave is ¼ of that time, or 4.167E-3 seconds. Thus, there are 4.167E-3 / 0.0004 ≈ 10 PWM pulses per quarter cycle. The PWM control signal can be simulated by comparing a saw-tooth waveform with the sinusoidal waveform with the circuit shown in Figure 11, where V3 and V11 are the saw tooth voltage sources.
Figure 11. PWM control signal simulation.
8
The comparison of the two waveforms in the simulation appeared as shown in Figure 12. The falling edge of each sawtooth begins a pulse, and the rising edge ends it. 20V
16V
12V
8V
4V
0V
-4V 0s V(U2:+)
1.0ms V(V3:+)
2.0ms
3.0ms
4.0ms
5.0ms
6.0ms
7.0ms
8.0ms 8.5ms
Time
Figure 12. Comparator simulation. Finally, with the positive and negative circuits in Figure 11, the complete PWM control signal is shown in Figure 13 for a full cycle of a sinusoidal voltage waveform. Obviously, the control signal for the positive half cycle is input to one set of IGBT’s, while the control signal for the negative half cycle is input to the other set. 20V
10V
0V
-10V
-20V 0s V(R14:2)
2ms V(R12:2)
4ms
6ms
8ms
V(U2:+) Time
Figure 13. Full PWM control signal.
9
10ms
12ms
14ms
16ms
Inverter DC to AC inverters are widely used in many applications such as motor drives, and UPS’s. The full bridge inverter configuration shown in Figure 14 is frequently employed, wherein the power semiconductor switches, Q1 to Q4, can be controlled by a variety of Pulse Width Modulation (PWM) techniques. PWM control strategies involving either unipolar or bipolar switching are common since the harmonics of significant amplitude are pushed into the high frequency range near the switching frequency. As the switching frequency is increased, a high quality output voltage waveform can be more easily recovered by low-pass filtering.
Q1
Q3
V1 Low Pass Filter
Load
C
Q2
Q4
Figure 14. Full-Bridge Inverter During a typical turn-on or turn-off operation, the voltage across each power device remains near to the dc bus voltage for a significant portion of the switching transient, while a relatively large current is being commutated. Therefore, it was important to choose a switch that could efficiently handle the significantly high current. For this type of application, the IGBT was chosen. IGBTs are used for the H-Bridge rather than MOSFETs due to their lower ON resistance, high-voltage applications (>1,000V), high temperature tolerance (>100°C) and their saturation voltage is a relatively-constant 3 volts even when many hundreds of amperes are flowing through the device. This makes for an inverter which has high efficiency at high output currents. Although IGBTs have a slower turn on time than MOSFETs, the relatively low frequency of operation (PWM frequency = 20 kHz) make this property irrelevant. The IGBT has been chosen for this project is the SGF80N60UF which is manufactured by Fairchild semiconductor. The SGF80N60UF was chosen because it has low conduction and switching losses, high speed switching and low saturation voltage V CE ( sat ) = 2.1V @ I C = 40 A . With higher switching frequency it means more heat
dissipation. Assume all the wire connectors are rated about 75 0 C and will be working in an ambient temperature of 30 0 C . The thermal resistance is
10
R= Where
ΔT
P
=
D
75 − 30 = 0.410 C / W 110
PD is the maximum power dissipation, ΔT is the change in temperature of a
maximum of 75 0 C and R is the thermal resistance. The thermal resistance should be below 1.1 0 C / W for the IGBTs working under normal conditions In order to optimize the turn on and turn off speed of IGBTs, the gate resistors R1 to R4 shown in Figure 2 must carefully choose. The values of these resistors determine the maximum amount of gate charging/discharging current and should ensure correct and safe commutation of the IGBT. For turn-on, the current required to charge the gate source capacitor C iss in the specified time can be calculated as
IP =
Q t
g
=
r
Where
Q
g
250nC = 7.14 A 35ns
is the IGBT gate charge and
t
r
is peak current for rise time.
The peak current for turn-off can be obtained in the same way as for turn-on, with the exception that peak current for fall time, t f , is substituted for t r
I
P
=
Q t
g
=
f
250nC = 7.14 A 35ns
The equivalent input gate emitter capacitance (the true capacitance seen by the drive during the commutation process) of the IGBT is next calculated as
C
in
=
Q ΔV
g
where
ΔV
gate
= V gate ( on ) − V gate ( off ) = 20 − (−20) = 40V
gate
+ 20 V, Q = 250 nC, g − IGBT part # SGF80N60UF and the drive HIP4080
The values V gate ( on ) = V gate ( off ) =
t
f
=
t
r
= 35 ns come from the
The total power used to for driving the IGBT is P = f(Khz) *
C
in
*
ΔV
2 gate
= 2.5Khz * 250nC * 40V = 0.025 W
11
The turn – on gate resistor will be selected:
R
gate ( on )
=
V
gate ( on )
I
=
P
20V = 2.8Ω 7.14 A
The turn – off gate resistor for turn off can be obtained in the same way as the turn on gate resistor.
R
gate ( off )
=
V
gate ( off )
I
P
=
20V = 2.8Ω 7.14 A
Inverter control signals connect the PIC18F452 and the inverter through the IGBT driver. The driver has been chosen for this project is the HIP4080, which is manufactured by Intersil. The HIP4080 was chosen because of its high frequency and ability to operate from 8VDC to 80VDC busses for driving IGBTs H-Bridge. Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-time which can be adjusted to near zero minimize distortion, resulting in precise control of the driven load. The HIP4080 has built a combination of bootstrap and charge-pumping techniques is used to power the circuitry which drives the upper IGBTs of the H-Bridge. The bootstrap technique supplies the high instantaneous current needed for turning on the power devices, while the charge pump provides enough current to maintain bias voltage on the upper driver section of IGBTs. The pin 8 (HEDL) and pin 9 (LEDL) are high-side and low-side turn on delay. Connect resistor from this pin to pin 4 (VSS) to set timing current that defines the turn-on delay of both high and low side drivers. Intersil recommends using R5 and R6 ranging from 10k to 100k. Base on the typical performance curve from the HIP4080 data sheet, the value of R5 = R6 = 50k was selected. The two bootstrap capacitors, C1 and C2, and the high voltage bus bypass capacitors are 0.1 uF, 100V ceramic. Ceramic is used here because of the low inductance required of these capacitors in this design. The two bootstrap diodes, D1 and D2, are 1A, 100V fast recovery to minimize the charge loss from the bootstrap capacitors when the diodes become reverse-biased. The HIP4080 is powered by 12 VDC to VCC (pin 15) and VDD (pin 16). VCC, VDD are positive supply to gate drivers and positive supply to lower gate drivers. For this design VCC and VDD ties together and connect to anodes of two bootstrap diodes D1 and D2. The input signals from the PIC18F452 enter to HEN (pin 2), IN + and IN- . Logic level input that when low overrides IN+/IN- (pin 6 and 7) to put AHO and BHO drivers (pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- . The pin can be driven by signal has a range 0V to 15V.
12
R3
2.8 Ohm
Q4 IGBT 2.8 Ohm
Q2 IGBT
R5 50 k 50 k
R6
D2
D1
12 V
C2 0.1 uF
15 16 VCC 4 VDD VSS
10 1 AHB BHB
19 17 BHS BLS
12 14 AHS ALS
3 2 DIS HEN
20 BHO 18 BLO
8 9 HDEL LDEL
11 AHO 13 ALO
R2
2.8 Ohm OUT
6 7 IN+ IN-
HIP4080
5
R1
Q1 IGBT
R4
2.8 Ohm
Q3 IGBT 12 V
C 1 0 .1 u F
Figure 15. Inverter-Driver Circuit Schematic
The selected inverter design was simulated using PSpice. The basic full bridge inverter was assembled and driven with the PWM control signal discussed above. Figure 16 shows the devices used to simulate the inverter portion of the design.
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Figure 16. PWM and Inverter Simulation Schematic
The resulting output signal shown in Figure 17 shows the required PWM signal operating at 2.5 kHz. Also, the resulting waveform is at the 12 Vdc level super imposed over a 60Hz sine wave. 20V
10V
0V
-10V
-20V 0s V(R47:2)
2ms V(Vupper,Vlower)
4ms
6ms
8ms
10ms
12ms
14ms
Time
Figure 17. PWM Output Signal
The next logical step in simulation was to implement the filter required to generate the 60 Hz output signal. The filter design selected was a LC low pass filter. This filter would block the higher frequencies. The filter is shown in Figure 18.
Figure 18. LC Low Pass Filter
14
16ms
17ms
The filter parameters depend on two components; an inductor and a capacitor. Each component needs to be properly specified and selected. A cutoff frequency of 1 kHz was selected. This would filter out the higher frequencies of the PWM signal and allow the production of a smooth sine wave. The value R is the impedance seen by inverter. At full load this value is .07 Ohms. The following equations were used to calculate the values for the filter. The resulting transfer function of the filter is found in Equation III. R L= 2 * π * fo Equation I: Inductor Calculation
C=
1 2 * π * R * fo
Equation II: Capacitor Calculation
G ( s) =
1 LCs 2 + s
L +1 R
=
5.995x10
-006
1 s + 0.002449 s + 1 2
Equation III: Filter Transfer Function
The transfer function was then simulated in Matlab to show its filtering capabilities. Figure 19 shown the cutoff frequency at 1 kHz.
Figure 19. Bode Magnitude Plot of Filter
15
The filter was then simulated in pSpice using the circuit in Figure 16 designed for PWM simulation. The resulting output signal from the filter was captured. The output waveform is a 12 volt sinusoid with a frequency of 60 Hz, shown in Figure 20. 20V 18V 16V 14V 12V 10V 8V 6V 4V 2V 0V -2V -4V -6V -8V -10V -12V -14V -16V -18V -20V 0s
10ms V(L9:2,C9:1)
20ms
30ms
40ms
50ms
60ms
70ms
80ms
90ms
100ms
Time
Figure 20. Filtered PWM Sinusoid Output Signal
The final portion of the design to be simulated is the step-up transformer used to convert the 12 volt signal to a 170 volts signal. Figure 21 shows a simple step-up circuit. A 12 volt AC source is fed through a transformer having a turns ratio of .072. This is the ratio of the primary windings to the secondary windings. The load modeled in the impedance seen at the full load of 1 kW.
Figure 21. Transformer & Load Simulation
16
200
200
100
100
0 0
-100 -100
-200 0s
10ms I(R4) V(V3:+)
20ms
30ms
40ms
50ms
60ms
70ms
80ms
90ms
100ms
-200 0s
Time
50ms
100ms
150ms
200ms
250ms
V(R2:2) -I(R2) Time
Figure 22. Transformer Input & Output Voltage and Currents
The transformer simulation of figure 22 shows exactly what is to be expected form the circuit. The input is a low voltage, high current signal. The output is a high voltage, low current signal.
17
TESTING PROCEDURES 1.
Preliminary Inspection – Following computer simulation and construction of the UPS and its individual components, an initial, visual inspection of the device shall be conducted to ensure against any assembly errors. Further, the separate components that collectively makeup the UPS are to be energized individually to prevent unexpected performance of one component from damaging others.
2.
Control – Proper operation of the software routines embedded in the microprocessor responsible for coordinating the interaction of the individual components of the UPS will be confirmed. First, the microprocessor will be installed on a developmental board and programmed to generate two PWM control signals, one to control the switching of each set of IGBTs that form the inverter. Each PWM waveform will be captured using the oscilloscope. Next, the microprocessor will be required to monitor an input signal that simulates electric power supplied by a utility. Various disruptions of the input signal will be induced to represent disturbances of utility-supplied power, and the microprocessor’s ability to activate the static transfer switch will be monitored using the oscilloscope. After the proper operation of both functions has been confirmed, the microprocessor will be required to control operation of both the inverter and static transfer switch in response to simulated power disruptions in real time.
3.
Circuit Protection – Protective measures built into the UPS design will be tested to minimize cascading damage to any system components in the event that the behavior of the assembled system or any individual component differs from the simulated behavior.
4.
Circuit Operation – Gate-triggering signals will be applied to each SCR in the transfer switch as well as to each IGBT in the inverter to ensure that each component is operational.
5.
System Performance – Following testing of each individual component, the system as a whole will be subjected to a variety of test conditions. Both the input and output voltage waveforms will be monitored to ensure that the output voltage is approximately a 120 V, 60 Hz voltage waveform regardless of disruptions in utility-supplied electric power.
18
FINANCIAL BUDGET
Design Team Member
Hourly Rate
Don Fisher Dung Nguyen Don Firca
$10.00 $10.00 $10.00
Estimated Hour Requirement 320 320 320
Labor Subtotal Part PIC18F452 Microprocessor Silicon Controlled Rectifier (“SCR”) SCR Driver Insulated Gate Bipolar Transistor (“IGBT”) IGBT Driver Pulse Transformer Step-Up Transformer 12V, 5+ mAH Sealed, Lead-Acid Battery Battery Charger 10-Segment LED Array 2-Segment LED Array Miscellaneous
Estimated Labor Cost $3,200 $3,200 $3,200 $9,600.00
Quantity 1 4 1 4
Price per Unit $6.00 $1.25 $1.00 16.50
Total Cost $6.00 $5.00 $1.00 $66.00
1 8 1 2
$1.00 $10.00 $50.00 $30.00
$1.00 $80.00 $50.00 $60.00
1 1 1 N/A
$25.00 $2.00 $1.00 N/A
$25.00 $2.00 $1.00 $25.00
Materials Subtotal Total
$322.00 $9,922.00 1
1
DESIGN TEAM INFORMATION TEAM: D3 ENGINEERING FACULTY ADVISOR Professor Malik E. Elbuluk, D.Sc., P.E.
TEAM MEMBERS Don Fisher – ECE - Project Manager Don Firca – ECE - Microprocessor Specialist Dung Nguyen – ECE - Electronic Hardware Engineer Special Thanks Dr. James Grover – Microprocessor Guru
2
