Validated 90nm CMOS technology platform with low-k ... - Semiconsultor
Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC) T.Devoivre1, M.Lunenborg2, C.Julien1, J-P.Carrere1, P.Ferreira1, W.J.Toren2, A.VandeGoor2, P.Gayet1, T.Berger1, O.Hinsinger1, P.Vannier1, Y.Trouiller3, Y.Rody2, P-J.Goirand1, R.Palla1, I.Thomas1, F.Guyader1, D.Roy1, B.Borot1, N. Planes1, S.Naudet1, F.Pico1, D.Duca1, F.Lalanne1, D.Heslinga2 and M.Haond1 1
2
STMicroelectronics, Crolles, France, PHILIPS Semiconductors, Crolles, France, 3LETI, Grenoble, France [email protected] Table I : 90nm CMOS platform
Abstract This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16 (27-70nm transistors (standard process) or 21 -90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1Mbit SRAM instances, based on a highly manufacturable 6T 1.36µm² memory cell, have been processed. The cell is detailed and its features, both electrical and morphological, are discussed.
Vdd (V) Tox (A) optical Lgate (nm) NMOS Ion (µA/µm) Ioff (nA/µm) Jg (A/cm²) PMOS Ion (µA/µm) Ioff (nA/µm) Jg (A/cm²)
640 10
520 1
Low Power Low Vt Nom Vt 1.2 21 ≤ 90 540 0.4
2 280 10
415 0.01 0.005
215 1
250 0.4
1
170 0.01 0.002
Table II : Main design Rules
Process integration The strong demand for total solution SoC results in a continuously increased technology complexity. The concerns are both system performance and stand-by power, as well as convenient chip interfaces. This requires different transistor flavors, low-k IMD, multi power supply management, triple well technology, as well as powerful embedded memories. The technology platform presented in this work is a 90nm CMOS process suitable for both logic and analog applications that support 2.5V or 3.3V I/O circuits. In fact, the offer is twofold : a General Purpose platform featuring a 16 (27 JDWH R[LGH ZLWK 70nm gate length 1.0V transistors suitable for ASIC applications and a Low Power one featuring 21 - 90nm 1.2V transistors suitable for mobile applications. For both platforms, two transistor flavors are proposed, allowing stand-by power management : a high speed and a low leakage transistor, using multiple Vt adjustments (see Table I).
General Purpose Low Vt Nom Vt 1.0 16 ≤ 70
Active Poly Contact M1 Via1-Via6 M2-M7 Via7-Via8 M8-M9 PO Endcap Poly-CT N+/P+
Design Rule Line Space 0.12 0.14 0.10 0.14 0.12 0.14 0.12 0.12 0.13 0.15 0.14 0.14 0.36 0.34 0.42 0.42 0.16 0.14 0.08 0.44
SRAM Line 0.12 0.11 0.12 0.16 0.13 0.18
Space 0.14 0.27* 0.14 0.14 0.30 0.18
0.14
0.12 0.075 0.30
* Except Poly Endcap Space
The process flow is based on a standard CMOS process with STI, retrograde Arsenic and Boron/Indium channels and a modular dual gate oxide process. 70nm or 90nm gate lengths are obtained from a resist trimming performed on 0.1µm printed lines (see Fig. 1). After gate patterning, ULE Ldd implants with As and BF2, coupled with heavy ion pockets to control Short Channel Effect (SCE) are performed. Nitride L-shape spacers are formed
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002) 1087-4852/02 $17.00 © 2002 IEEE
transistors used in the SRAM periphery. Ion of 535 and 225µA/µm are obtained for NMOS and PMOS respectively for a maximum leakage of 10nA/µm. 2 Cumulative failure probability (Weibull scale)
before S/D Implant. Activation is performed through a high temperature spike anneal to control P-type S/D extensions, while maintaining a high level of dopant activation. CoSi2 is then formed. Finally W plugs contact a single damascene copper Metal1 (see Fig. 2).
1
17 Å
0 -1 21 Å
-2 -3
65 Å
-4 -5 -6
N+/P 10-4cm² capa, Vg ramp 0.2V/s, 25°C
-7 0.0
2.0
4.0 6.0 8.0 10.0 Voltage to breakdown (V)
12.0
Fig. 3 : Oxides integrity figures for the different oxides 10-04 Vdd = 1V Tox = 17A
10-05
Ioff [A/µm]
10-06
Fig. 1 : TEM cross-section of a 70nm transistor
PMOS
10-07
0.1µm
10-08 10-09
M1
NMOS
10-10 223 µA/µm
10-11 100
200
300
535 µA/µm
400
500
600
700
Ion [µA/µm] CT Si3N4
0.14µm
CoSi2
Fig. 4 : SRAM transistors Ion-Ioff figures for the General Purpose process 500
0.14µm
STI
NMOS
Vd = 0.025V
400
lin
300
Vd = 1.0V
Devices Performances The 16 (27 JDWH R[LGH LV IRUPHG WKURXJK DQ 12 Rapid Thermal Nitridation of a thermal pre-oxide, resulting in a well controlled gate leakage (
2
STMicroelectronics, Crolles, France, PHILIPS Semiconductors, Crolles, France, 3LETI, Grenoble, France [email protected] Table I : 90nm CMOS platform
Abstract This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16 (27-70nm transistors (standard process) or 21 -90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1Mbit SRAM instances, based on a highly manufacturable 6T 1.36µm² memory cell, have been processed. The cell is detailed and its features, both electrical and morphological, are discussed.
Vdd (V) Tox (A) optical Lgate (nm) NMOS Ion (µA/µm) Ioff (nA/µm) Jg (A/cm²) PMOS Ion (µA/µm) Ioff (nA/µm) Jg (A/cm²)
640 10
520 1
Low Power Low Vt Nom Vt 1.2 21 ≤ 90 540 0.4
2 280 10
415 0.01 0.005
215 1
250 0.4
1
170 0.01 0.002
Table II : Main design Rules
Process integration The strong demand for total solution SoC results in a continuously increased technology complexity. The concerns are both system performance and stand-by power, as well as convenient chip interfaces. This requires different transistor flavors, low-k IMD, multi power supply management, triple well technology, as well as powerful embedded memories. The technology platform presented in this work is a 90nm CMOS process suitable for both logic and analog applications that support 2.5V or 3.3V I/O circuits. In fact, the offer is twofold : a General Purpose platform featuring a 16 (27 JDWH R[LGH ZLWK 70nm gate length 1.0V transistors suitable for ASIC applications and a Low Power one featuring 21 - 90nm 1.2V transistors suitable for mobile applications. For both platforms, two transistor flavors are proposed, allowing stand-by power management : a high speed and a low leakage transistor, using multiple Vt adjustments (see Table I).
General Purpose Low Vt Nom Vt 1.0 16 ≤ 70
Active Poly Contact M1 Via1-Via6 M2-M7 Via7-Via8 M8-M9 PO Endcap Poly-CT N+/P+
Design Rule Line Space 0.12 0.14 0.10 0.14 0.12 0.14 0.12 0.12 0.13 0.15 0.14 0.14 0.36 0.34 0.42 0.42 0.16 0.14 0.08 0.44
SRAM Line 0.12 0.11 0.12 0.16 0.13 0.18
Space 0.14 0.27* 0.14 0.14 0.30 0.18
0.14
0.12 0.075 0.30
* Except Poly Endcap Space
The process flow is based on a standard CMOS process with STI, retrograde Arsenic and Boron/Indium channels and a modular dual gate oxide process. 70nm or 90nm gate lengths are obtained from a resist trimming performed on 0.1µm printed lines (see Fig. 1). After gate patterning, ULE Ldd implants with As and BF2, coupled with heavy ion pockets to control Short Channel Effect (SCE) are performed. Nitride L-shape spacers are formed
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002) 1087-4852/02 $17.00 © 2002 IEEE
transistors used in the SRAM periphery. Ion of 535 and 225µA/µm are obtained for NMOS and PMOS respectively for a maximum leakage of 10nA/µm. 2 Cumulative failure probability (Weibull scale)
before S/D Implant. Activation is performed through a high temperature spike anneal to control P-type S/D extensions, while maintaining a high level of dopant activation. CoSi2 is then formed. Finally W plugs contact a single damascene copper Metal1 (see Fig. 2).
1
17 Å
0 -1 21 Å
-2 -3
65 Å
-4 -5 -6
N+/P 10-4cm² capa, Vg ramp 0.2V/s, 25°C
-7 0.0
2.0
4.0 6.0 8.0 10.0 Voltage to breakdown (V)
12.0
Fig. 3 : Oxides integrity figures for the different oxides 10-04 Vdd = 1V Tox = 17A
10-05
Ioff [A/µm]
10-06
Fig. 1 : TEM cross-section of a 70nm transistor
PMOS
10-07
0.1µm
10-08 10-09
M1
NMOS
10-10 223 µA/µm
10-11 100
200
300
535 µA/µm
400
500
600
700
Ion [µA/µm] CT Si3N4
0.14µm
CoSi2
Fig. 4 : SRAM transistors Ion-Ioff figures for the General Purpose process 500
0.14µm
STI
NMOS
Vd = 0.025V
400
lin
300
Vd = 1.0V
Devices Performances The 16 (27 JDWH R[LGH LV IRUPHG WKURXJK DQ 12 Rapid Thermal Nitridation of a thermal pre-oxide, resulting in a well controlled gate leakage (
