Wide Temperature Spectrum Low Leakage Dynamic Circuit ...
Wide Temperature Spectrum Low Leakage Dynamic Circuit Technique for Sub-65nm CMOS Technologies Volkan Kursun and Zhiyu Liu Department of Electrical and Computer Engineering University of Wisconsin – Madison Madison, Wisconsin 53706 - 1691 Abstract-A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors are utilized along with a dual threshold voltage CMOS technology to place an idle domino circuit into a low leakage state. The effectiveness of the circuit technique is evaluated for a widetemperature spectrum, considering both long and short idle periods. Assuming a short idle period at a temperature of 110oC, up to 95.6% reduction in leakage power is observed as compared to standard dual threshold voltage domino circuits. Alternatively, assuming a long idle period at the room temperature, the circuit technique reduces the leakage power by up to 96.9% as compared to the standard dual threshold voltage domino logic circuits. Furthermore, by employing PMOS-only sleep transistors, the presented circuit technique reduces the total leakage power by up to 43.8% as compared to a previously published sleep scheme based on NMOS sleep transistors in a 45nm CMOS technology.
Similar subthreshold leakage current reduction techniques based on discharging and charging the dynamic and output nodes, respectively, of the domino circuits have been proposed in [3]-[5]. The effect of these CMOS circuit techniques on the gate oxide leakage current (Igate) characteristics, however, has not been explored. The high output of an idle domino circuit places the fan-out gates into the highest gate oxide leakage current state, as illustrated in Fig. 1. The techniques proposed in [2]-[5], therefore, increase the gate oxide leakage current while reducing the subthreshold leakage current. The Igate increases with the scaling of the gate insulator thickness (tox) in each new technology generation. The tox is in the range of 12 Å to 16 Å in the current CMOS technologies [6]. Such a thin insulator layer can conduct a significant gate tunneling current despite the scaling of the supply voltage. Variation of gate oxide and subthreshold leakage currents with the supply voltage and temperature in a 45nm CMOS technology is shown in Fig. 2. 1.E-05
I. INTRODUCTION
VDD
VDD
VDD
VDD
Fan-out gate VDD
45nm CMOS Technology Vtlow = 220 mV 1.E-06 Leakage Current (A)
Supply and threshold voltages are reduced with the scaling of CMOS technology. The lowering of threshold voltage leads to an exponential increase in the subthreshold leakage current [1]. A dual threshold voltage (dual-Vt) circuit technique is proposed in [2] for reducing the subthreshold leakage power consumption in domino logic circuits. With this technique, high threshold voltage (high-Vt) transistors are employed on the non-critical precharge paths as illustrated in Fig. 1. Alternatively, low threshold voltage (low-Vt) transistors are employed on the speed critical evaluation paths. Gating the inputs high to the first stage in a domino pipeline is proposed to place an idle circuit into a low leakage state [2]. Following the low-to-high transition of the outputs of the first stage domino gates, the subsequent gates also evaluate/discharge in a domino fashion. After the node voltages settle to a steady state, all of the high-Vt transistors are cut-off, reducing the subthreshold leakage current [1], [2].
6.8 x 2.5 x 1.E-07
Gate Oxide Leakage Current, T = 25 Gate Oxide Leakage Current, T = 110 Subthreshold Leakage Current, T = 25 Subthreshold Leakage Current, T = 47 Subthreshold Leakage Current, T = 110
1.E-08
1.E-09 0.1
0.3
0.5
0.7 VDD (V)
0.9
1.1
1.3
Fig. 2. Comparison of subthreshold and gate oxide leakage currents produced by an NMOS transistor for various supply voltages at three temperatures. Isubthreshold: VGS = 0 and VDS = VDD. Igate: VGS = VGD = VGB = VDD.
Keeper H
Pull-up
Pull-up
Clk = H
Clk = H Dynamic = L
In1 = H
Out = H
Dynamic2 = L
Ink = H
Subthreshold Leakage Current Gate Oxide Leakage Current
Fig. 1. A k-input standard dual-Vt domino OR gate with high inputs in the sleep mode. H: high voltage (VDD). L: low voltage (Gnd).
The relative contribution of the subthreshold and gate oxide leakage currents to the total leakage power consumption significantly varies with the die temperature. The subthreshold leakage current exponentially increases with the temperature. Alternatively, the gate oxide leakage current displays a weaker dependence on the temperature. At 110oC, the subthreshold leakage current produced by a low-Vt NMOS transistor is 6.8 x higher than the gate oxide leakage current (at the nominal supply voltage VDD = 0.8 V) as shown in Fig. 2. Alternatively, at the room temperature, the Igate is 2.5 × higher than the subthreshold leakage current. The gate dielectric tunneling can, therefore, no longer be ignored particularly at the low die temperatures. New circuit techniques aimed at reducing both the subthreshold and gate oxide leakage currents are highly desirable in deeply scaled nanometer CMOS technologies.
II. DUAL-Vt DOMINO LOGIC Several subthreshold leakage current reduction techniques for idle domino logic circuits have been proposed in [2]-[5]. These techniques, as described in Section 1, increase the gate oxide leakage current by maintaining the sleep mode inputs high in all of the domino gates in an idle circuit. In the sub-65 nm CMOS technologies, the significant increase in the gate oxide leakage current could negate the reduction in the subthreshold leakage current, thereby increasing the total leakage power consumption with the circuit techniques described in [2]-[5]. When the subthreshold and gate oxide leakage currents are simultaneously considered, in addition to setting the dynamic node voltage low for fully benefiting from a dual-Vt CMOS technology to reduce the subthreshold leakage current by cutting off all of the high-Vt transistors, the output node of a domino logic circuit should also be placed into a low voltage state in order to suppress the gate oxide leakage currents in the fan-out gates. A technique to place both the dynamic and the output nodes of a domino logic circuit into a low voltage state in the standby mode is proposed in [7]. Two NMOS sleep transistors N1 and N2 are placed at the dynamic and output nodes, respectively, in a domino gate as illustrated in Fig. 3. Gate Oxide Leakage Current Subthreshold Leakage Current VDD
VDD
VDD
Keeper
Dynamic Stagen
VDD
VDD
Sleep = H
H
P3
Pull-up
Pull-up P4
Clkn= H
Dynamicn = L
In1 = L
Dynamic Stagen+1
Ink = L
Sleep = H
Clkn+1= H Outn = L
N1
Sleep = H
N2
In1 = L
Fig. 3. A k-input dual-Vt-NMOS domino OR gate with NMOS (N1 and N2) and PMOS (P3) sleep transistors.
In the standby mode, the clock is gated high. The sleep signal is set high turning on N1 and N2 and turning off P3. The dynamic and output nodes are discharged through N1 and N2, respectively. Although this technique can be effective for suppressing the gate oxide leakage current produced by the pulldown network transistors, the two NMOS sleep transistors (N1 and N2) are both in the maximum gate oxide leakage current state during the sleep mode, as illustrated in Fig. 3. The
sleep transistors (N1, N2, and P3) are required within every domino gate in a dynamic circuit with the technique presented in [7]. The gate oxide leakage current overhead of the NMOS sleep transistors, therefore, imposes a serious limitation to the overall leakage current reduction that can be provided by this technique.
III. PMOS SLEEP SWITCH DUAL-Vt DOMINO LOGIC A new circuit technique with enhanced effectiveness to simultaneously reduce subthreshold and gate oxide leakage currents in domino logic circuits is presented in this section. Only P-type sleep transistors are employed in order to reduce the gate oxide leakage current overhead of the new sleep switch circuit technique. In a technology with silicon dioxide gate dielectric material, the tunneling barrier for holes is much higher than the barrier for electrons. The Igate of a PMOS device is, therefore, significantly smaller than an NMOS device with the same physical dimensions (including tox) and the same oxide voltage. A comparison of the gate oxide leakage currents produced by the N-channel and P-channel devices in a 45nm CMOS technology is provided in Fig. 4. The Igate produced by a PMOS transistor is 10.7 × to 46.9 × smaller than the Igate produced by an NMOS transistor depending on the voltage difference across the gate oxide, as illustrated in Fig. 4. 1.E-05 Gate Oxide Leakage Current, Low-Vt NMOS Subthreshold Leakage Current, High-Vt NMOS Subthreshold Leakage Current, High-Vt PMOS
1.E-06
Gate Oxide Leakage Current, High-Vt PMOS 46.9 x Leakage Current (A)
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS sleep transistors are utilized along with a dual-Vt CMOS technology to place an idle domino gate into a low leakage state. The effectiveness of the proposed technique for lowering the total leakage power is evaluated at both high and low temperatures considering short and long idle periods, respectively. Up to 96.9% reduction in leakage power is observed as compared to the standard dual-Vt domino circuits. Furthermore, by employing PMOS-only sleep transistors, the presented circuit technique reduces the total leakage power by up to 43.8% as compared to a previously published technique based on NMOS sleep transistors in a 45nm CMOS technology. The paper is organized as follows. The leakage current characteristics of the dual-Vt domino gates are described in Section 2. The new circuit technique is presented in Section 3. The simulation results at the extremes of a typical microprocessor die temperature spectrum are discussed in Section 4. Finally, some conclusions are offered in Section 5.
4.1 x
1.E-07
7.3 x 1.E-08
1.E-09
45nm CMOS Technology T = 110 °C |Vtlow| = 220 mV |Vthigh| = 350 mV
10.7 x 1.E-10 0.1
0.3
0.5
0.7 VDD (V)
0.9
1.1
1.3
Fig. 4. Comparison of subthreshold and gate oxide leakage currents produced by the same sized NMOS and PMOS transistors for various supply voltages.
The new circuit technique is illustrated in Fig. 5. Two PMOS sleep transistors P1 and P2 are added to the dynamic and output nodes, respectively. A high-Vt PMOS sleep transistor (P3) is also employed in the output inverter. Turning-off P3 in the sleep mode eliminates the static DC current path through P4 and P2 while suppressing the subthreshold leakage current produced by the output inverter. In the active mode, the sleep signal is set high. P1 and P2 are cut-off and P3 (driven by the inverted sleep signal) is turned on. The domino gate operates similar to a standard domino circuit. In the standby mode, the clock is gated high, turning off the high-Vt pull-up transistor. The sleep signal is set low, turning on P1 and P2. P3 is cut-off by the inverted sleep signal. The dynamic and output nodes are discharged to |Vtplow| (threshold voltage of a low-Vt PMOS transistor) through P1 and P2, respectively. The dynamic and output nodes are eventually discharged to a steadystate voltage less than |Vtplow| by the initially high subthreshold leakage currents produced by the low-Vt transistors in the pull-down network and the output inverter (after P1 and P2 are cut-off) and the initially high gate-oxide leakage current of the fan-out gates. After the node voltages settle to a steady state, all of the high-Vt transistors are strongly cut-off, significantly reducing the subthreshold leakage current. Similarly, the voltages across the gate insulating layers of all of the NMOS transistors in the pulldown networks of the fan-out gates
are suppressed, thereby lowering the gate oxide leakage current with the proposed circuit technique. VDD
VDD
VDD
VDD
Keeper
Clk
Sleep
Pull-up
P3
TABLE I STEADY-STATE DYNAMIC AND OUTPUT NODE VOLTAGES IN DUAL-Vt-PMOS CIRCUITS
P4 Dynamic
In1
offered by the proposed dual-Vt-PMOS circuit technique at the room temperature is listed in Table II. The dual-Vt-PMOS technique reduces the total leakage power consumption by 86.7% to 96.4% as compared to the standard dual-Vt circuits driven with low inputs, as listed in Table II. For a higher fanin, the leakage power reduction provided by the dual-Vt-PMOS is further enhanced (OR2: 91.6% versus OR8: 96.4%) since the subthreshold leakage current produced by the standard dual-Vt gates increases as the number of inputs is increased.
Ink
Sleep
Node Voltage
OR2
OR4
OR8
AND2
MUX16
Dynamic (mV)
17.9
5.5
2.0
82.9
41.7
Output (mV)
33.0
61.7
76.7
4.6
26.4
Output
P1
Sleep
P2
Cload
Fig. 5. A k-input dual-Vt-PMOS domino OR gate with PMOS-only sleep transistors (P1, P2, and P3).
IV. SIMULATION RESULTS BSIM4 device models are used in this paper for an accurate estimation of the gate oxide leakage current. The following circuits are simulated in a 45nm CMOS technology [8] (Vtnlow = |Vtplow| = 0.22V, Vtnhigh = |Vtphigh| = 0.35V, and VDD = 0.8V): 2-input and 4-input domino AND gates (AND2 and AND4), 2-input, 4-input, and 8-input domino OR gates (OR2, OR4, and OR8, respectively), and a 16-bit domino multiplexer (MUX16). All of the circuits (other than MUX16) are composed of three stages. Each gate drives a fan-out of four. The domino gates in the first stage are footed while the domino gates in the second and third stages are footless. The circuits are evaluated with the following three techniques: standard dual-Vt domino (dual-Vt), the technique presented in [7] (dual-Vt-NMOS), and the circuit technique proposed in this paper (dual-Vt-PMOS). A 3 GHz clock is applied to the circuits. To have a reasonable comparison, the circuits are sized to have a similar worst-case evaluation delay with each technique. The subthreshold leakage current produced by a domino logic circuit strongly depends on the voltages of the dynamic and output nodes [1]. Two input conditions are simulated to evaluate the leakage power in the sleep mode with the standard dualVt technique. The first condition assumes that all of the inputs applied to the first stage gates are gated low. The second condition assumes that all of the inputs applied to the first stage gates are gated high (as suggested in [2] and as implied in [3]-[5]). The simulation results at the room temperature are presented in Section A. The leakage power consumption at the worst-case high temperature of 110oC is characterized in Section B. A.
Leakage Power Characterization at Room Temperature
The data in this section is produced at the room temperature assuming the circuits are idle for a long time. In the dual-Vt-PMOS circuits, the PMOS sleep transistors are not capable of directly discharging the dynamic and output nodes to zero volts. After P1 and P2 are turned off, the initially high subthreshold leakage currents produced by the low-Vt transistors in the pull-down network and the output inverter and the initially high gate-oxide leakage current of the fan-out gates complete the discharging of the dynamic and output nodes. The steady-state dynamic and output node voltages in the dual-Vt-PMOS circuits are well below |Vtplow|, as listed in Table I. The total leakage power consumption of the domino circuits with the three techniques is shown in Fig. 6. The leakage power reduction
Normalized Leakage Power Consumption
2.8 2.6
Dual-Vt, Low Inputs
2.4
Dual-Vt, High Inputs
2.2
Dual-Vt-NMOS
2
Dual-Vt-PMOS
T = 25 °C
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 AND4
AND2
OR2
OR4
OR8
MUX16
Fig. 6. Comparison of total leakage power consumption of the domino circuits with the three circuit techniques. Leakage power is normalized to the leakage power of standard dual-Vt technique with low inputs for each circuit.
For a dual-Vt CMOS technology to be effective for reducing the subthreshold leakage current, the inputs to a standard dual-Vt domino gate must be maintained high during the sleep mode [1]-[5]. A high input vector, however, places the transistors in the pull-down network into the maximum gate oxide leakage current state, as illustrated in Fig. 1. The leakage power reduction provided by the proposed circuit technique is, therefore, more significant when the inputs are gated high in the standard dual-Vt domino logic circuits. The dual-Vt-PMOS technique reduces the total leakage power by 90.2% to 96.9% as compared to the standard dual-Vt circuits with high inputs, as listed in Table II. TABLE II TOTAL LEAKAGE POWER REDUCTION PROVIDED BY THE DUAL-VtPMOS TECHNIQUE AS COMPARED TO DUAL-Vt-NMOS AND STANDARD DUAL-Vt TECHNIQUES at 25oC AND4
AND2
OR2
OR4
OR8
MUX16
Dual-Vt-NMOS
39.6%
43.8%
35.5%
40.8%
41.1%
22.2%
*Dual-Vt –L
86.7%
90.4%
91.6%
94.0%
96.4%
87.7%
*Dual-Vt –H
95.0%
93.6%
90.2%
94.2%
96.9%
93.8%
*Dual-Vt–L (H): standard dual-Vt domino with inputs gated low (high).
Contrary to the results reported in [1]-[5], the standard dual-Vt circuits driven by high inputs consume more power than the standard dual-Vt circuits driven by low inputs, with the exception of OR2, as illustrated in Fig. 6. This result indicates a dramatic change in the low temperature leakage power characteristics of the domino logic circuits
in the scaled nanometer CMOS technologies. Previous dual-Vt domino logic circuit techniques ([2]-[5]) based on applying high input vectors to idle domino gates are, therefore, no longer effective for lowering the total leakage power consumption due to the significant increase in the gate dielectric tunneling current [9]. As previously described, the two NMOS sleep transistors are both in the maximum gate oxide leakage current state during the entire sleep mode, imposing a serious limitation to the overall leakage current reduction provided by the dual-Vt-NMOS technique. Alternatively, with the proposed dual-Vt-PMOS technique, only P-channel sleep transistors are employed. The gate tunneling current of a PMOS device is more than an order of magnitude smaller than an NMOS device under similar gate oxide bias conditions (see Fig. 4). Furthermore, after the sleep transistors are activated and the dynamic and output nodes are discharged, voltage difference across the gate oxide layers of P1 and P2 are maintained at approximately zero volts throughout the idle mode with the dual-Vt-PMOS technique (Vgs ≈ Vgd ≈ 0V, see Fig. 5). The proposed scheme therefore virtually eliminates the gate oxide leakage current overhead introduced by the sleep transistors. The dual-VtPMOS technique reduces the total leakage power consumption by 22.2% to 43.8% as compared to the dual-Vt-NMOS technique, as listed in Table II. B.
Leakage Power Characterization at High Temperature
Provided that the proposed sleep scheme is aggressively employed even during short idle periods, the die temperature would not decrease significantly before the circuit is reactivated. The data in this section is produced assuming a short idle period with a worst-case die temperature of 110oC. The total leakage power consumption of domino circuits with the three techniques at 110oC is shown in Fig. 7.
Normalized Leakage Power Consumption
1.2
1
Dual-Vt, Low Inputs
Dual-Vt, High Inputs
Dual-Vt-NMOS
Dual-Vt-PMOS
T = 110 °C
0.8
0.6
0.4
low-Vt NMOS transistor is 4.1 x (4.7 x) higher than the subthreshold leakage current produced by a high-Vt NMOS (PMOS) transistor with the same physical dimensions at 110oC. Dual-Vt-PMOS, therefore, significantly reduces the total leakage power by 40.4% (OR2) to 84.7% (MUX16) as compared to the standard dual-Vt circuits with high inputs even at this worst-case high temperature. The gate oxide leakage overhead of the small sleep transistors plays a less significant role on the total leakage power consumption as the temperature is increased. The leakage power characteristics of dual-VtPMOS and dual-Vt-NMOS are, therefore, similar at 110oC.
V. CONCLUSIONS In sub-65 nm CMOS technologies, both subthreshold and gate dielectric leakage currents need to be suppressed for reducing the standby power consumption. A domino circuit technique based on PMOS-only sleep transistors and a dual-Vt CMOS technology is presented in this paper for simultaneously reducing subthreshold and gate oxide leakage power consumption. With the circuit technique, both dynamic and output nodes in a domino logic circuit are discharged through PMOS sleep transistors in the idle mode. Placing the dynamic node into a low voltage state reduces the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Furthermore, placing the output node into a low voltage state suppresses the gate dielectric tunneling currents into the fan-out gates. The proposed circuit technique exploits initially high subthreshold and gate-oxide leakage currents in scaled nanometer CMOS technologies for placing an idle domino logic circuit into an ultimately low leakage state. Effectiveness of the proposed technique for lowering total leakage power consumption is evaluated at both high and low die temperatures. Assuming a short idle period at a worst-case high temperature of 110oC, the proposed circuit technique reduces the total leakage power by 40.4% to 95.6% as compared to the standard dual-Vt domino circuits. Alternatively, assuming a long idle period at the room temperature, the circuit technique reduces the leakage power by 86.7% to 96.9% as compared to the standard dual-Vt domino circuits. Furthermore, by employing PMOS-only sleep transistors, the presented circuit technique reduces the total leakage power by up to 43.8% as compared to a previously published sleep scheme based on NMOS sleep transistors.
VI. REFERENCES
0.2
0 AND4
AND2
OR2
OR4
OR8
MUX16
Fig. 7. Comparison of total leakage power consumption of the domino circuits with the three circuit techniques at 110oC. Leakage power is normalized to the leakage power of standard dual-Vt technique with low inputs for each circuit.
As discussed in Section 1, the subthreshold leakage current increases exponentially with the increased temperature while the gate oxide leakage displays a weaker dependence on the temperature. The relative contribution of the subthreshold and gate oxide leakage currents to the total leakage power consumption, therefore, changes as the temperature is increased. As shown in 7, a discharged dynamic node voltage state with inputs gated high is preferable for lower leakage power consumption in the standard dual-Vt circuits at 110oC. Despite the increase in the subthreshold leakage current, the proposed circuit technique continues to provide substantial power savings even at this high temperature since the subthreshold leakage current is produced by the high-Vt transistors when the inputs are high in the standard dual-Vt circuits. Alternatively, bulk of the gate oxide leakage current is produced by the low-Vt NMOS transistors in the pulldown network when the inputs are high. As shown in Fig. 4, the gate oxide leakage current produced by a
[1] V. Kursun and E. G. Friedman, “Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits,” Proceedings of the IEEE/ACM International Symposium of Quality Electronic Design, pp. 104-109, March 2004. [2] J. Kao, “Dual Threshold Voltage Domino Logic,” Proceedings of the European Solid-State Circuits Conference, pp. 118-121, September 1999. [3] M. W. Allam, M. H. Anis, and M. I. Elmasry, “High-Speed Dynamic Logic Styles for Scaled-Down CMOS and MTCMOS Technologies,” Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, pp. 145160, July 2000. [4] S. Heo and K. Asanovic, “Leakage-biased Domino Circuits for Dynamic Finegrain Leakage Reduction,” Proceedings of the IEEE International Symposium on VLSI Circuits, pp. 316-319, June 2002. [5] V. Kursun and E. G. Friedman, “Sleep Switch Dual Threshold Voltage Domino Logic With Reduced Standby Leakage Current,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 5, pp. 485-496, May 2004. [6] T. Ghani et al., “Scaling Challenges and Device Design Requirements for High Performance Sub-50 nm Gate Length Planar CMOS Transistors,” Proceedings of the IEEE International Symposium on VLSI Technology, pp. 174 - 175, June 2000. [7] G. Yang, Z. Wang, and S. Kang, “Leakage-Proof Domino Circuit Design for Deep Sub-100 nm Technologies,” Proceedings of the IEEE International Conference on VLSI Design, pp. 222-227, January 2004. [8] Berkeley Predictive Technology Model (BPTM), http://www.device .eecs.berkeley.edu/~ptm/download.html. [9] Z. Liu and V. Kursun, “Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling,” Proceedings of the IEEE International Systems-on-Chip (SOC) Conference, pp. 151-154, September 2005.
Similar subthreshold leakage current reduction techniques based on discharging and charging the dynamic and output nodes, respectively, of the domino circuits have been proposed in [3]-[5]. The effect of these CMOS circuit techniques on the gate oxide leakage current (Igate) characteristics, however, has not been explored. The high output of an idle domino circuit places the fan-out gates into the highest gate oxide leakage current state, as illustrated in Fig. 1. The techniques proposed in [2]-[5], therefore, increase the gate oxide leakage current while reducing the subthreshold leakage current. The Igate increases with the scaling of the gate insulator thickness (tox) in each new technology generation. The tox is in the range of 12 Å to 16 Å in the current CMOS technologies [6]. Such a thin insulator layer can conduct a significant gate tunneling current despite the scaling of the supply voltage. Variation of gate oxide and subthreshold leakage currents with the supply voltage and temperature in a 45nm CMOS technology is shown in Fig. 2. 1.E-05
I. INTRODUCTION
VDD
VDD
VDD
VDD
Fan-out gate VDD
45nm CMOS Technology Vtlow = 220 mV 1.E-06 Leakage Current (A)
Supply and threshold voltages are reduced with the scaling of CMOS technology. The lowering of threshold voltage leads to an exponential increase in the subthreshold leakage current [1]. A dual threshold voltage (dual-Vt) circuit technique is proposed in [2] for reducing the subthreshold leakage power consumption in domino logic circuits. With this technique, high threshold voltage (high-Vt) transistors are employed on the non-critical precharge paths as illustrated in Fig. 1. Alternatively, low threshold voltage (low-Vt) transistors are employed on the speed critical evaluation paths. Gating the inputs high to the first stage in a domino pipeline is proposed to place an idle circuit into a low leakage state [2]. Following the low-to-high transition of the outputs of the first stage domino gates, the subsequent gates also evaluate/discharge in a domino fashion. After the node voltages settle to a steady state, all of the high-Vt transistors are cut-off, reducing the subthreshold leakage current [1], [2].
6.8 x 2.5 x 1.E-07
Gate Oxide Leakage Current, T = 25 Gate Oxide Leakage Current, T = 110 Subthreshold Leakage Current, T = 25 Subthreshold Leakage Current, T = 47 Subthreshold Leakage Current, T = 110
1.E-08
1.E-09 0.1
0.3
0.5
0.7 VDD (V)
0.9
1.1
1.3
Fig. 2. Comparison of subthreshold and gate oxide leakage currents produced by an NMOS transistor for various supply voltages at three temperatures. Isubthreshold: VGS = 0 and VDS = VDD. Igate: VGS = VGD = VGB = VDD.
Keeper H
Pull-up
Pull-up
Clk = H
Clk = H Dynamic = L
In1 = H
Out = H
Dynamic2 = L
Ink = H
Subthreshold Leakage Current Gate Oxide Leakage Current
Fig. 1. A k-input standard dual-Vt domino OR gate with high inputs in the sleep mode. H: high voltage (VDD). L: low voltage (Gnd).
The relative contribution of the subthreshold and gate oxide leakage currents to the total leakage power consumption significantly varies with the die temperature. The subthreshold leakage current exponentially increases with the temperature. Alternatively, the gate oxide leakage current displays a weaker dependence on the temperature. At 110oC, the subthreshold leakage current produced by a low-Vt NMOS transistor is 6.8 x higher than the gate oxide leakage current (at the nominal supply voltage VDD = 0.8 V) as shown in Fig. 2. Alternatively, at the room temperature, the Igate is 2.5 × higher than the subthreshold leakage current. The gate dielectric tunneling can, therefore, no longer be ignored particularly at the low die temperatures. New circuit techniques aimed at reducing both the subthreshold and gate oxide leakage currents are highly desirable in deeply scaled nanometer CMOS technologies.
II. DUAL-Vt DOMINO LOGIC Several subthreshold leakage current reduction techniques for idle domino logic circuits have been proposed in [2]-[5]. These techniques, as described in Section 1, increase the gate oxide leakage current by maintaining the sleep mode inputs high in all of the domino gates in an idle circuit. In the sub-65 nm CMOS technologies, the significant increase in the gate oxide leakage current could negate the reduction in the subthreshold leakage current, thereby increasing the total leakage power consumption with the circuit techniques described in [2]-[5]. When the subthreshold and gate oxide leakage currents are simultaneously considered, in addition to setting the dynamic node voltage low for fully benefiting from a dual-Vt CMOS technology to reduce the subthreshold leakage current by cutting off all of the high-Vt transistors, the output node of a domino logic circuit should also be placed into a low voltage state in order to suppress the gate oxide leakage currents in the fan-out gates. A technique to place both the dynamic and the output nodes of a domino logic circuit into a low voltage state in the standby mode is proposed in [7]. Two NMOS sleep transistors N1 and N2 are placed at the dynamic and output nodes, respectively, in a domino gate as illustrated in Fig. 3. Gate Oxide Leakage Current Subthreshold Leakage Current VDD
VDD
VDD
Keeper
Dynamic Stagen
VDD
VDD
Sleep = H
H
P3
Pull-up
Pull-up P4
Clkn= H
Dynamicn = L
In1 = L
Dynamic Stagen+1
Ink = L
Sleep = H
Clkn+1= H Outn = L
N1
Sleep = H
N2
In1 = L
Fig. 3. A k-input dual-Vt-NMOS domino OR gate with NMOS (N1 and N2) and PMOS (P3) sleep transistors.
In the standby mode, the clock is gated high. The sleep signal is set high turning on N1 and N2 and turning off P3. The dynamic and output nodes are discharged through N1 and N2, respectively. Although this technique can be effective for suppressing the gate oxide leakage current produced by the pulldown network transistors, the two NMOS sleep transistors (N1 and N2) are both in the maximum gate oxide leakage current state during the sleep mode, as illustrated in Fig. 3. The
sleep transistors (N1, N2, and P3) are required within every domino gate in a dynamic circuit with the technique presented in [7]. The gate oxide leakage current overhead of the NMOS sleep transistors, therefore, imposes a serious limitation to the overall leakage current reduction that can be provided by this technique.
III. PMOS SLEEP SWITCH DUAL-Vt DOMINO LOGIC A new circuit technique with enhanced effectiveness to simultaneously reduce subthreshold and gate oxide leakage currents in domino logic circuits is presented in this section. Only P-type sleep transistors are employed in order to reduce the gate oxide leakage current overhead of the new sleep switch circuit technique. In a technology with silicon dioxide gate dielectric material, the tunneling barrier for holes is much higher than the barrier for electrons. The Igate of a PMOS device is, therefore, significantly smaller than an NMOS device with the same physical dimensions (including tox) and the same oxide voltage. A comparison of the gate oxide leakage currents produced by the N-channel and P-channel devices in a 45nm CMOS technology is provided in Fig. 4. The Igate produced by a PMOS transistor is 10.7 × to 46.9 × smaller than the Igate produced by an NMOS transistor depending on the voltage difference across the gate oxide, as illustrated in Fig. 4. 1.E-05 Gate Oxide Leakage Current, Low-Vt NMOS Subthreshold Leakage Current, High-Vt NMOS Subthreshold Leakage Current, High-Vt PMOS
1.E-06
Gate Oxide Leakage Current, High-Vt PMOS 46.9 x Leakage Current (A)
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS sleep transistors are utilized along with a dual-Vt CMOS technology to place an idle domino gate into a low leakage state. The effectiveness of the proposed technique for lowering the total leakage power is evaluated at both high and low temperatures considering short and long idle periods, respectively. Up to 96.9% reduction in leakage power is observed as compared to the standard dual-Vt domino circuits. Furthermore, by employing PMOS-only sleep transistors, the presented circuit technique reduces the total leakage power by up to 43.8% as compared to a previously published technique based on NMOS sleep transistors in a 45nm CMOS technology. The paper is organized as follows. The leakage current characteristics of the dual-Vt domino gates are described in Section 2. The new circuit technique is presented in Section 3. The simulation results at the extremes of a typical microprocessor die temperature spectrum are discussed in Section 4. Finally, some conclusions are offered in Section 5.
4.1 x
1.E-07
7.3 x 1.E-08
1.E-09
45nm CMOS Technology T = 110 °C |Vtlow| = 220 mV |Vthigh| = 350 mV
10.7 x 1.E-10 0.1
0.3
0.5
0.7 VDD (V)
0.9
1.1
1.3
Fig. 4. Comparison of subthreshold and gate oxide leakage currents produced by the same sized NMOS and PMOS transistors for various supply voltages.
The new circuit technique is illustrated in Fig. 5. Two PMOS sleep transistors P1 and P2 are added to the dynamic and output nodes, respectively. A high-Vt PMOS sleep transistor (P3) is also employed in the output inverter. Turning-off P3 in the sleep mode eliminates the static DC current path through P4 and P2 while suppressing the subthreshold leakage current produced by the output inverter. In the active mode, the sleep signal is set high. P1 and P2 are cut-off and P3 (driven by the inverted sleep signal) is turned on. The domino gate operates similar to a standard domino circuit. In the standby mode, the clock is gated high, turning off the high-Vt pull-up transistor. The sleep signal is set low, turning on P1 and P2. P3 is cut-off by the inverted sleep signal. The dynamic and output nodes are discharged to |Vtplow| (threshold voltage of a low-Vt PMOS transistor) through P1 and P2, respectively. The dynamic and output nodes are eventually discharged to a steadystate voltage less than |Vtplow| by the initially high subthreshold leakage currents produced by the low-Vt transistors in the pull-down network and the output inverter (after P1 and P2 are cut-off) and the initially high gate-oxide leakage current of the fan-out gates. After the node voltages settle to a steady state, all of the high-Vt transistors are strongly cut-off, significantly reducing the subthreshold leakage current. Similarly, the voltages across the gate insulating layers of all of the NMOS transistors in the pulldown networks of the fan-out gates
are suppressed, thereby lowering the gate oxide leakage current with the proposed circuit technique. VDD
VDD
VDD
VDD
Keeper
Clk
Sleep
Pull-up
P3
TABLE I STEADY-STATE DYNAMIC AND OUTPUT NODE VOLTAGES IN DUAL-Vt-PMOS CIRCUITS
P4 Dynamic
In1
offered by the proposed dual-Vt-PMOS circuit technique at the room temperature is listed in Table II. The dual-Vt-PMOS technique reduces the total leakage power consumption by 86.7% to 96.4% as compared to the standard dual-Vt circuits driven with low inputs, as listed in Table II. For a higher fanin, the leakage power reduction provided by the dual-Vt-PMOS is further enhanced (OR2: 91.6% versus OR8: 96.4%) since the subthreshold leakage current produced by the standard dual-Vt gates increases as the number of inputs is increased.
Ink
Sleep
Node Voltage
OR2
OR4
OR8
AND2
MUX16
Dynamic (mV)
17.9
5.5
2.0
82.9
41.7
Output (mV)
33.0
61.7
76.7
4.6
26.4
Output
P1
Sleep
P2
Cload
Fig. 5. A k-input dual-Vt-PMOS domino OR gate with PMOS-only sleep transistors (P1, P2, and P3).
IV. SIMULATION RESULTS BSIM4 device models are used in this paper for an accurate estimation of the gate oxide leakage current. The following circuits are simulated in a 45nm CMOS technology [8] (Vtnlow = |Vtplow| = 0.22V, Vtnhigh = |Vtphigh| = 0.35V, and VDD = 0.8V): 2-input and 4-input domino AND gates (AND2 and AND4), 2-input, 4-input, and 8-input domino OR gates (OR2, OR4, and OR8, respectively), and a 16-bit domino multiplexer (MUX16). All of the circuits (other than MUX16) are composed of three stages. Each gate drives a fan-out of four. The domino gates in the first stage are footed while the domino gates in the second and third stages are footless. The circuits are evaluated with the following three techniques: standard dual-Vt domino (dual-Vt), the technique presented in [7] (dual-Vt-NMOS), and the circuit technique proposed in this paper (dual-Vt-PMOS). A 3 GHz clock is applied to the circuits. To have a reasonable comparison, the circuits are sized to have a similar worst-case evaluation delay with each technique. The subthreshold leakage current produced by a domino logic circuit strongly depends on the voltages of the dynamic and output nodes [1]. Two input conditions are simulated to evaluate the leakage power in the sleep mode with the standard dualVt technique. The first condition assumes that all of the inputs applied to the first stage gates are gated low. The second condition assumes that all of the inputs applied to the first stage gates are gated high (as suggested in [2] and as implied in [3]-[5]). The simulation results at the room temperature are presented in Section A. The leakage power consumption at the worst-case high temperature of 110oC is characterized in Section B. A.
Leakage Power Characterization at Room Temperature
The data in this section is produced at the room temperature assuming the circuits are idle for a long time. In the dual-Vt-PMOS circuits, the PMOS sleep transistors are not capable of directly discharging the dynamic and output nodes to zero volts. After P1 and P2 are turned off, the initially high subthreshold leakage currents produced by the low-Vt transistors in the pull-down network and the output inverter and the initially high gate-oxide leakage current of the fan-out gates complete the discharging of the dynamic and output nodes. The steady-state dynamic and output node voltages in the dual-Vt-PMOS circuits are well below |Vtplow|, as listed in Table I. The total leakage power consumption of the domino circuits with the three techniques is shown in Fig. 6. The leakage power reduction
Normalized Leakage Power Consumption
2.8 2.6
Dual-Vt, Low Inputs
2.4
Dual-Vt, High Inputs
2.2
Dual-Vt-NMOS
2
Dual-Vt-PMOS
T = 25 °C
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 AND4
AND2
OR2
OR4
OR8
MUX16
Fig. 6. Comparison of total leakage power consumption of the domino circuits with the three circuit techniques. Leakage power is normalized to the leakage power of standard dual-Vt technique with low inputs for each circuit.
For a dual-Vt CMOS technology to be effective for reducing the subthreshold leakage current, the inputs to a standard dual-Vt domino gate must be maintained high during the sleep mode [1]-[5]. A high input vector, however, places the transistors in the pull-down network into the maximum gate oxide leakage current state, as illustrated in Fig. 1. The leakage power reduction provided by the proposed circuit technique is, therefore, more significant when the inputs are gated high in the standard dual-Vt domino logic circuits. The dual-Vt-PMOS technique reduces the total leakage power by 90.2% to 96.9% as compared to the standard dual-Vt circuits with high inputs, as listed in Table II. TABLE II TOTAL LEAKAGE POWER REDUCTION PROVIDED BY THE DUAL-VtPMOS TECHNIQUE AS COMPARED TO DUAL-Vt-NMOS AND STANDARD DUAL-Vt TECHNIQUES at 25oC AND4
AND2
OR2
OR4
OR8
MUX16
Dual-Vt-NMOS
39.6%
43.8%
35.5%
40.8%
41.1%
22.2%
*Dual-Vt –L
86.7%
90.4%
91.6%
94.0%
96.4%
87.7%
*Dual-Vt –H
95.0%
93.6%
90.2%
94.2%
96.9%
93.8%
*Dual-Vt–L (H): standard dual-Vt domino with inputs gated low (high).
Contrary to the results reported in [1]-[5], the standard dual-Vt circuits driven by high inputs consume more power than the standard dual-Vt circuits driven by low inputs, with the exception of OR2, as illustrated in Fig. 6. This result indicates a dramatic change in the low temperature leakage power characteristics of the domino logic circuits
in the scaled nanometer CMOS technologies. Previous dual-Vt domino logic circuit techniques ([2]-[5]) based on applying high input vectors to idle domino gates are, therefore, no longer effective for lowering the total leakage power consumption due to the significant increase in the gate dielectric tunneling current [9]. As previously described, the two NMOS sleep transistors are both in the maximum gate oxide leakage current state during the entire sleep mode, imposing a serious limitation to the overall leakage current reduction provided by the dual-Vt-NMOS technique. Alternatively, with the proposed dual-Vt-PMOS technique, only P-channel sleep transistors are employed. The gate tunneling current of a PMOS device is more than an order of magnitude smaller than an NMOS device under similar gate oxide bias conditions (see Fig. 4). Furthermore, after the sleep transistors are activated and the dynamic and output nodes are discharged, voltage difference across the gate oxide layers of P1 and P2 are maintained at approximately zero volts throughout the idle mode with the dual-Vt-PMOS technique (Vgs ≈ Vgd ≈ 0V, see Fig. 5). The proposed scheme therefore virtually eliminates the gate oxide leakage current overhead introduced by the sleep transistors. The dual-VtPMOS technique reduces the total leakage power consumption by 22.2% to 43.8% as compared to the dual-Vt-NMOS technique, as listed in Table II. B.
Leakage Power Characterization at High Temperature
Provided that the proposed sleep scheme is aggressively employed even during short idle periods, the die temperature would not decrease significantly before the circuit is reactivated. The data in this section is produced assuming a short idle period with a worst-case die temperature of 110oC. The total leakage power consumption of domino circuits with the three techniques at 110oC is shown in Fig. 7.
Normalized Leakage Power Consumption
1.2
1
Dual-Vt, Low Inputs
Dual-Vt, High Inputs
Dual-Vt-NMOS
Dual-Vt-PMOS
T = 110 °C
0.8
0.6
0.4
low-Vt NMOS transistor is 4.1 x (4.7 x) higher than the subthreshold leakage current produced by a high-Vt NMOS (PMOS) transistor with the same physical dimensions at 110oC. Dual-Vt-PMOS, therefore, significantly reduces the total leakage power by 40.4% (OR2) to 84.7% (MUX16) as compared to the standard dual-Vt circuits with high inputs even at this worst-case high temperature. The gate oxide leakage overhead of the small sleep transistors plays a less significant role on the total leakage power consumption as the temperature is increased. The leakage power characteristics of dual-VtPMOS and dual-Vt-NMOS are, therefore, similar at 110oC.
V. CONCLUSIONS In sub-65 nm CMOS technologies, both subthreshold and gate dielectric leakage currents need to be suppressed for reducing the standby power consumption. A domino circuit technique based on PMOS-only sleep transistors and a dual-Vt CMOS technology is presented in this paper for simultaneously reducing subthreshold and gate oxide leakage power consumption. With the circuit technique, both dynamic and output nodes in a domino logic circuit are discharged through PMOS sleep transistors in the idle mode. Placing the dynamic node into a low voltage state reduces the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Furthermore, placing the output node into a low voltage state suppresses the gate dielectric tunneling currents into the fan-out gates. The proposed circuit technique exploits initially high subthreshold and gate-oxide leakage currents in scaled nanometer CMOS technologies for placing an idle domino logic circuit into an ultimately low leakage state. Effectiveness of the proposed technique for lowering total leakage power consumption is evaluated at both high and low die temperatures. Assuming a short idle period at a worst-case high temperature of 110oC, the proposed circuit technique reduces the total leakage power by 40.4% to 95.6% as compared to the standard dual-Vt domino circuits. Alternatively, assuming a long idle period at the room temperature, the circuit technique reduces the leakage power by 86.7% to 96.9% as compared to the standard dual-Vt domino circuits. Furthermore, by employing PMOS-only sleep transistors, the presented circuit technique reduces the total leakage power by up to 43.8% as compared to a previously published sleep scheme based on NMOS sleep transistors.
VI. REFERENCES
0.2
0 AND4
AND2
OR2
OR4
OR8
MUX16
Fig. 7. Comparison of total leakage power consumption of the domino circuits with the three circuit techniques at 110oC. Leakage power is normalized to the leakage power of standard dual-Vt technique with low inputs for each circuit.
As discussed in Section 1, the subthreshold leakage current increases exponentially with the increased temperature while the gate oxide leakage displays a weaker dependence on the temperature. The relative contribution of the subthreshold and gate oxide leakage currents to the total leakage power consumption, therefore, changes as the temperature is increased. As shown in 7, a discharged dynamic node voltage state with inputs gated high is preferable for lower leakage power consumption in the standard dual-Vt circuits at 110oC. Despite the increase in the subthreshold leakage current, the proposed circuit technique continues to provide substantial power savings even at this high temperature since the subthreshold leakage current is produced by the high-Vt transistors when the inputs are high in the standard dual-Vt circuits. Alternatively, bulk of the gate oxide leakage current is produced by the low-Vt NMOS transistors in the pulldown network when the inputs are high. As shown in Fig. 4, the gate oxide leakage current produced by a
[1] V. Kursun and E. G. Friedman, “Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits,” Proceedings of the IEEE/ACM International Symposium of Quality Electronic Design, pp. 104-109, March 2004. [2] J. Kao, “Dual Threshold Voltage Domino Logic,” Proceedings of the European Solid-State Circuits Conference, pp. 118-121, September 1999. [3] M. W. Allam, M. H. Anis, and M. I. Elmasry, “High-Speed Dynamic Logic Styles for Scaled-Down CMOS and MTCMOS Technologies,” Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, pp. 145160, July 2000. [4] S. Heo and K. Asanovic, “Leakage-biased Domino Circuits for Dynamic Finegrain Leakage Reduction,” Proceedings of the IEEE International Symposium on VLSI Circuits, pp. 316-319, June 2002. [5] V. Kursun and E. G. Friedman, “Sleep Switch Dual Threshold Voltage Domino Logic With Reduced Standby Leakage Current,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 5, pp. 485-496, May 2004. [6] T. Ghani et al., “Scaling Challenges and Device Design Requirements for High Performance Sub-50 nm Gate Length Planar CMOS Transistors,” Proceedings of the IEEE International Symposium on VLSI Technology, pp. 174 - 175, June 2000. [7] G. Yang, Z. Wang, and S. Kang, “Leakage-Proof Domino Circuit Design for Deep Sub-100 nm Technologies,” Proceedings of the IEEE International Conference on VLSI Design, pp. 222-227, January 2004. [8] Berkeley Predictive Technology Model (BPTM), http://www.device .eecs.berkeley.edu/~ptm/download.html. [9] Z. Liu and V. Kursun, “Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling,” Proceedings of the IEEE International Systems-on-Chip (SOC) Conference, pp. 151-154, September 2005.
