A 12-bit, 270MS/s Pipelined ADC with SHA ... - Semantic Scholar
A 12-bit, 270MS/s Pipelined ADC with SHA-Eliminating Front End Xuan Wang, Changyi Yang, Xiaoxiao Zhao, Chao Wu, Fule Li, Zhihua Wang
Bin Wu
Institute of Microelectronics Tsinghua University Beijing, P.R.China [email protected]
Institute of Microelectronics Chinese Academy of Sciences Beijing, P.R.China
Abstract—This paper presents a 12-bit 270MS/s pipelined analog-to-digital converter (ADC) without employing a frontend sample-and-hold amplifier. A novel strategy is established to diminish the aperture error while maintaining both the original tracking time and amplifying time of multiplying digital-toanalog converter (MDAC). It matches the signal paths between comparators and MDAC in the first stage by using proper timing sequence and high-speed dynamic comparators. The measurement results show 63.7dB SNR and 76.1dBc SFDR at 120.1MHz input frequency while the chip’s total power dissipation is 250mW (excluding LVDS drivers) at 1.2V supply. The ADC core occupies 1.7mm2 and is implemented in a 130nm CMOS process.
frequency increases; therefore the sampling paths of both comparator and MDAC still have to be designed carefully.
I.
Several SHA-eliminating methods with aperture error minimizing have been established in [2][3][4] as is discussed in Section II. But all of the mentioned methods need partially occupy tracking time or amplifying time during the converting cycle, which increases the bandwidth requirements on the ADC driver or the first MDAC’s op-amp respectively, and more power consumption is caused in turn on system level, especially in a high-speed application. Moreover, the modified timing control will greatly complicate the design process. In this paper, a novel SHA-eliminating method which is more suitable for operating at high sampling rate and low power condition is introduced, of which principle is discussed in Section II. Section III provides analysis on its circuit implementation. Section IV & V reveal the design and the measurement results of a 12-bit pipelined ADC prototype. The conclusion is drawn in Section VI.
INTRODUCTION
With the development of wireless communication technology, the demand for high-speed and high-resolution analog-to-digital converters (ADCs) is increasing over the last decades. Besides, to confirm the trend of Software Radio, IFsampling is another issue deserves to be focused on. In order to convert high-frequency signals with low effective resolution deterioration, sample-and–hold amplifier (SHA) is widely introduced in high-speed designs. However, SHA brings in extra noise and causes more than one third of the circuit’s total power consumption [1], which is a huge disadvantage when power specification is concerned equally important in portable products.
II.
A. Conventional Designs One most directly and commonly used SHA-eliminating architecture [2] is shown in Fig.1 (a). This method guarantees that the signal paths of comparators and MDAC match each other during the tracking phase, which is implemented by using identical RC delay and timing. Besides, the dummy elements are also employed in front of pre-amplifier to copy the op-amp’s input parasitics. A separate comparison phase CK1c is introduced letting decisions to be done before the beginning of the amplifying phase.
Thus, for the purpose of lowing power consumption, noise contribution and reducing die area as well, the most transparent way is to remove the front-end SHA. This, unfortunately, introduces destructive effects to the first stage, because the sampled and held input signal is no longer provided. In this case, mismatch between sampling paths of comparator and MDAC leads to aperture error, which equivalently increases the comparators’ offset at the input. Thanks to the digital correction technique, the tolerance to the aperture error enlarges to a great extend, such as ±0.125Vref in a 2.5-bit stage. However, the situation gets worse when input
Another strategy [4] is exhibited in Fig.1 (b). Separated capacitors are used in comparators allowing that they sample the input and threshold voltage at the same time while the input signal is also being tracked by MDAC. During the amplifying phase, those separated capacitors switch on to virtual ground, thus the difference between sampled signal and
This work was supported by the Major National Science & Technology Program of China under Grant No. 2009ZX03007 002. / 2010ZX03001-00402.
978-1-4673-0219-7/12/$31.00 ©2012 IEEE
SHA-ELIMINATING STRATEGIES
798
remove the pulse and simplify the timing sequence compared with the traditional designs. In order to realize the assumption, the following requirements need to be met: firstly, the continuing subtraction between signal and threshold should be done during the tracking phase; secondly, the pre-amplifier with its input path should be rapidly responded to catch up with the highly fluctuated signal. In our design, the threshold is sampled on Ccmp during the amplifying phase of prior converting cycle in advance, which is used for subtraction with the input signal in the current cycle. Therefore, the difference is acquired and pre-amplified synchronously as input signal is being tracked, while in the mentioned conventional architectures the preamplifying is done with specially allocated time. Then digital result can be latched at the falling edge of CK1b (in Fig.2), the edge that ends the MDAC’s tracking. Figure 1. Conventional SHA-less architectures and timing sequences
III.
threshold will be obtained and then latched after preamplifying. However, the settling of MDAC still has to be delayed.
MODEL AND IMPLEMENTATION
It is easy to notice that the aperture error is caused by mistiming between signals that were sampled and latched, which is also considered as the RC delay mismatch of MDAC sampling path and comparator’s pre-amplifier input path in a high signal frequency situation.
In sum, the comparator’s pre-amplifying process begins after the sampling edge in both of the preceding architectures, thus no matter how fast the pre-amplifier and latch is, it is still necessary to introduce a pulse that allocates time for switching and pre-amplifying. However the pulse takes either part of tracking or settling time of MDAC as a price. Consequently, as input frequency and sampling rate increase, the decrease of available tracking or settling time results in the increasing requirement of input driver capacity or op-amp’s bandwidth, respectively. In addition, the involved narrow pulse is difficult to be precisely generated under high sampling rate conditions.
Assuming a sinusoidal signal with ±Vref input range, which can be written as Vin=Vref·sin(2πfint), where fin is the input frequency, the worst case for ADC happens at the maximum input slop as
dVin dt
max
= 2π ⋅ f in ⋅ Vref
(1)
In order to adjust the aperture error by digital redundancy correction, the maximum error has to be less than 0.125Vref according to the 2.5-bit MDAC transfer curve shown in Fig.3, which is expressed as
B. Proposed Design In this design, a 2.5-bit MDAC structure with a novel approach to avoid the involved pulse in conventional strategies is applied as the first stage. The architecture of this front-end MDAC with the employed dynamic comparator is shown in Fig.2. Assuming that the pre-amplifier is capable of tracking the comparison difference so well that the aperture error caused by sampling path mismatch can be tolerated, it is feasible to use the sampling edge to control the latch thus to
1 Ve max = 2π ⋅ f in ⋅ Vref ⋅ (Δt ) < Vref 8
Figure 2. Proposed first stage architecture for SHA-eliminating and comparator 799
(2)
Figure 4. Architecture of the 12-bit SHA-eliminating pipelined ADC
In order to reject common mode distortion and improve linearity, all the modules in the ADC core are designed using differential configuration. Two-stage symmetrical op-amps with gain-boosting are designed carefully to reach the desired gain and bandwidth under 1.2V power supply. All the sampling switches use traditional boot-strapped switch architecture [5] to prevent linearity deterioration.
Figure 3. Sketch of aperture error and 2.5-bit MDAC transfer curve
ΔRad max = 2π ⋅
1 ⋅ f in = 0.125rad Δt max
(3)
where ΔRadmax and Δtmax are the phase and time mismatch tolerance limit, respectively.
The value of sampling capacitors and op-amps’ specification are scaled down in subsequent stages to reduce power dissipation. The non-overlap clock is generated separately for each stage to minimize the global wiring. Onchip reference buffer is also introduced to avoid the fluctuation brought by related switched capacitor circuits. No additional calibration technique is used in this design to avoid the disadvantage of added calibration cycle.
During the tracking phase, considering the small-signal operation, the path through input port to pre-amplifier output can be modeled as a single pole common-source amplifier system while assuming that the input RC delay of both comparator and MDAC can be neglected comparing to the pre-amplifier’s bandwidth, by which the aperture error is determined, thus the pre-amplifier’s bandwidth requirement can be extracted as
tan −1 (
f in f BW max
) = ΔRad max
V.
(4)
According to the calculation, the bandwidth of the preamplifier should be designed greater than approximately 6.4 GHz to limit the aperture error within the correction range when fin reaches 800MHz. Meanwhile, pre-amplifier’s slew rate has to guarantee such bandwidth when considering the large-signal operation. Thus a large bandwidth dynamic comparator with high slew rate (in Fig.2) is designed to obtain high tracking speed. AC analyzing shows that the designed pre-amplifier achieves 8GHz bandwidth during its operational phase at all-corner conditions while the slew rate is more than 42V/ns, which is enough to support such large bandwidth. The post-layout simulation indicates that the 1st stage is still able to proper function when receiving an 800MHz sinusoidal signal. Though dynamic comparators in the 1st stage totally cost 5mA average current while MDAC costs 70mA, it is still much less than the increasing power consumed by MDAC (if 30% settling time shorter [3]) that meets the same specification. More important, the conversion speed limit, which is mainly decided by op-amp’s bandwidth and settling time, can be extended by the proposed method. IV.
MEASUREMENT RESULTS
The pipelined ADC is fabricated in 130nm 1P8M CMOS technology. The chip micrograph is shown in Fig.5. The total area including bonding pads is 4mm2 with ADC core area of 1.7mm2. The ADC operates under core supply of 1.2V and I/O supply of 1.8V. The total power consumption is 250mW (including on-chip reference, excluding I/O LVDS drivers) at 270MS/s, and it can be lower to 200mW with virtually the same performance at a sampling rate of 200MS/s. The measured output FFT spectrum with 45.1MHz input signal at 200MS/s is shown in Fig.6, which exhibits SNDR of 65.6dB and SFDR of 81.0dBc. Fig.7 shows the DNL/INL plot. The result of 0.38LSB peak DNL and 0.84LSB peak INL is obtained at 200MS/s with 30.1MHz input. Fig.8 reveals the SNDR, SNR, THD and SFDR of the ADC for an input frequency sweep at 200MS/s and 270MS/s respectively (THD contains 2nd-10th harmonic).
PROTOTYPE ADC DESIGN
A prototype of 12-bit 270MS/s pipelined ADC with SHAeliminating front-end is developed, of which architecture is shown in Fig.4. The circuit consists of five 2.5-bit stages and a 2-bit backend flash. On-chip bandgap, reference, clock generator, SPI interface and LVDS output drivers are included. 800
Figure 5. Chip micrograph
VI.
ADC Output Spectrum 0
This paper presents a 12-bit 270MS/s pipelined ADC with 1.2V supply. A novel method to eliminate front-end SHA is established, and is verified by the experimental chip’s measurement results, showing SNR of 63.7dB and SFDR of 76.1dBc at 120.1MHz input frequency. The performance comparison with the prior arts is shown in Table I, which indicates that the proposed strategy will simplify the design while its FOM, defined as Power/(2ENOB×Fs), is competitive compared with other SHA-eliminating methods even at the highest conversion speed. The summary of the prototype’s specifications is shown in Table II.
-20
Fin = 45.1MHz @ 200MS/s SFDR = 81.0 dBc THD = 77.6 dBc SNR = 65.9 dB SNDR = 65.6 dB ENOB = 10.6 bit
Power (dB)
-40
-60
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
REFERENCES
Fi/Fs
Figure 6. ADC output spectrum
[1]
ADC Static Performances 1
[2]
DNL (LSB)
0.5
0
-0.5
[3] -1
0
500
1000
1500
2000
2500
Code
1
3000
3500
4000
[4]
INL (LSB)
0.5
0
-0.5
-1
[5] 0
500
1000
1500
2000
2500
Code
3000
3500
4000
[6]
Figure 7. Static performances (Fs=200MS/s, Fin=30.1MHz) SNDR, SNR, THD, SFDR vs. Fin (Fs=200MS/s & 270MS/s) Fs=200MS/s
85 80
SFDR THD SNR SNDR
Byun-Moo Min, P. Kim, F. W. Bowman, D. M. Boisvert, and A. J. Aude “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 38, pp 2031-2039, December 2003. Kush Gulati, M. Shang Peng, A. Pulincherry, C. E. Munoz, M. Lugin, et al, “A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs,” IEEE J. Solid-State Circuits, vol. 41, pp 1856-1866, August 2006. Byung-Geun Lee, B. Min, G. Manganaro and J. W. Valvano, “A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC,” IEEE J. Solid-State Circuits, vol. 43, pp 2613-2619, December 2008. Siddharth Devarajan, L. Singer, D. Kelly, S. Decker, A. Kamath and P Wilkins, “A 16-bit, 125MS/s, 385mW, 78.7dB SNR CMOS Pipeline ADC,” IEEE J. Solid-State Circuits, vol. 44, pp 3305-3313, December 2009. Mikko Waltari and L. Sumanen , “A Self-Calirated Pipeline ADC with 200 MHz IF-Sampling Frontend”, AICSP, vol. 37, pp 201-213, 2003. Dong-Hyun Hwang, J. E. Song, S. P. Nam, H. J. Kim, T. J. An, K. S. Kim, and S. H. Lee, “A Range-Scaled 13b 100MS/s 0.13um CMOS SHA-Free ADC Based on a Single Reference”, ISOCC, pp 62-65, 2011.
TABLE II.
75
dB
CONCLUSION
SUMMARY OF SPECIFICATIONS
70
Technology
130nm 1P8M CMOS
65
Resolution
12 bits
60 55
50
100
150
200
Supply voltage
250
Input Frequency (MHz)
Fs=270MS/s
85 80
SFDR THD SNR SNDR
Power consumption
dB
75
Core: 1.2V I/O: 1.8V Core: 250mW@270MS/s Including on-chip reference I/O drivers: 90mW
70
Input range
1.2Vpp (differential)
65
Total area (with pad)
2mm×2mm
Sampling rate ENOB (Fin=30.1MHz) (Fin=70.1MHz) (Fin=120.1MHz) SNR (Fin=30.1MHz) (Fin=70.1MHz) (Fin=120.1MHz) SFDR (Fin=30.1MHz) (Fin=70.1MHz) (Fin=120.1MHz) THD (Fin=30.1MHz) (Fin=70.1MHz) (Fin=120.1MHz) Peak DNL (Fin=30.1MHz)
200MS/s 270MS/s 10.3 bits 10.6 bits 10.2 bits 10.6 bits 10.2 bits 10.4 bits 64.4 dB 65.9 dB 64.0 dB 65.7 dB 63.7 dB 64.7 dB 77.2 dBc 82.4 dBc 73.6 dBc 77.8 dBc 76.1 dBc 77.4 dBc 74.7 dBc 78.2 dBc 70.8 dBc 76.4 dBc 72.2 dBc 74.4 dBc 0.38 LSB
Peak INL (Fin=30.1MHz)
0.84 LSB
60 55
50
100
150
200
250
Input Frequency (MHz)
Figure 8. Dynamic performances versus input frequency
TABLE I. Resolution Supply Sampling Power (core) ENOB @Fin(Hz) FOM (pJ/Conv)
PERFORMANCE COMPARISON WITH THE PRIOR ARTS [2] 13 bits 3.3V 180MS/s 756mW 10.6 bits @15M
[3] 14 bits 3.0V 100MS/s 230mW 11.7 bits @39M
[6] 13 bits 1.3V 100MS/s 146mW 10.4 bits @4M
2.71
0.70
1.08
This work 12 bits 1.2V 200MS/s 270MS/s 200mW 250mW 10.6 bits 10.3 bits @30M @30M 0.65
0.74
801
Bin Wu
Institute of Microelectronics Tsinghua University Beijing, P.R.China [email protected]
Institute of Microelectronics Chinese Academy of Sciences Beijing, P.R.China
Abstract—This paper presents a 12-bit 270MS/s pipelined analog-to-digital converter (ADC) without employing a frontend sample-and-hold amplifier. A novel strategy is established to diminish the aperture error while maintaining both the original tracking time and amplifying time of multiplying digital-toanalog converter (MDAC). It matches the signal paths between comparators and MDAC in the first stage by using proper timing sequence and high-speed dynamic comparators. The measurement results show 63.7dB SNR and 76.1dBc SFDR at 120.1MHz input frequency while the chip’s total power dissipation is 250mW (excluding LVDS drivers) at 1.2V supply. The ADC core occupies 1.7mm2 and is implemented in a 130nm CMOS process.
frequency increases; therefore the sampling paths of both comparator and MDAC still have to be designed carefully.
I.
Several SHA-eliminating methods with aperture error minimizing have been established in [2][3][4] as is discussed in Section II. But all of the mentioned methods need partially occupy tracking time or amplifying time during the converting cycle, which increases the bandwidth requirements on the ADC driver or the first MDAC’s op-amp respectively, and more power consumption is caused in turn on system level, especially in a high-speed application. Moreover, the modified timing control will greatly complicate the design process. In this paper, a novel SHA-eliminating method which is more suitable for operating at high sampling rate and low power condition is introduced, of which principle is discussed in Section II. Section III provides analysis on its circuit implementation. Section IV & V reveal the design and the measurement results of a 12-bit pipelined ADC prototype. The conclusion is drawn in Section VI.
INTRODUCTION
With the development of wireless communication technology, the demand for high-speed and high-resolution analog-to-digital converters (ADCs) is increasing over the last decades. Besides, to confirm the trend of Software Radio, IFsampling is another issue deserves to be focused on. In order to convert high-frequency signals with low effective resolution deterioration, sample-and–hold amplifier (SHA) is widely introduced in high-speed designs. However, SHA brings in extra noise and causes more than one third of the circuit’s total power consumption [1], which is a huge disadvantage when power specification is concerned equally important in portable products.
II.
A. Conventional Designs One most directly and commonly used SHA-eliminating architecture [2] is shown in Fig.1 (a). This method guarantees that the signal paths of comparators and MDAC match each other during the tracking phase, which is implemented by using identical RC delay and timing. Besides, the dummy elements are also employed in front of pre-amplifier to copy the op-amp’s input parasitics. A separate comparison phase CK1c is introduced letting decisions to be done before the beginning of the amplifying phase.
Thus, for the purpose of lowing power consumption, noise contribution and reducing die area as well, the most transparent way is to remove the front-end SHA. This, unfortunately, introduces destructive effects to the first stage, because the sampled and held input signal is no longer provided. In this case, mismatch between sampling paths of comparator and MDAC leads to aperture error, which equivalently increases the comparators’ offset at the input. Thanks to the digital correction technique, the tolerance to the aperture error enlarges to a great extend, such as ±0.125Vref in a 2.5-bit stage. However, the situation gets worse when input
Another strategy [4] is exhibited in Fig.1 (b). Separated capacitors are used in comparators allowing that they sample the input and threshold voltage at the same time while the input signal is also being tracked by MDAC. During the amplifying phase, those separated capacitors switch on to virtual ground, thus the difference between sampled signal and
This work was supported by the Major National Science & Technology Program of China under Grant No. 2009ZX03007 002. / 2010ZX03001-00402.
978-1-4673-0219-7/12/$31.00 ©2012 IEEE
SHA-ELIMINATING STRATEGIES
798
remove the pulse and simplify the timing sequence compared with the traditional designs. In order to realize the assumption, the following requirements need to be met: firstly, the continuing subtraction between signal and threshold should be done during the tracking phase; secondly, the pre-amplifier with its input path should be rapidly responded to catch up with the highly fluctuated signal. In our design, the threshold is sampled on Ccmp during the amplifying phase of prior converting cycle in advance, which is used for subtraction with the input signal in the current cycle. Therefore, the difference is acquired and pre-amplified synchronously as input signal is being tracked, while in the mentioned conventional architectures the preamplifying is done with specially allocated time. Then digital result can be latched at the falling edge of CK1b (in Fig.2), the edge that ends the MDAC’s tracking. Figure 1. Conventional SHA-less architectures and timing sequences
III.
threshold will be obtained and then latched after preamplifying. However, the settling of MDAC still has to be delayed.
MODEL AND IMPLEMENTATION
It is easy to notice that the aperture error is caused by mistiming between signals that were sampled and latched, which is also considered as the RC delay mismatch of MDAC sampling path and comparator’s pre-amplifier input path in a high signal frequency situation.
In sum, the comparator’s pre-amplifying process begins after the sampling edge in both of the preceding architectures, thus no matter how fast the pre-amplifier and latch is, it is still necessary to introduce a pulse that allocates time for switching and pre-amplifying. However the pulse takes either part of tracking or settling time of MDAC as a price. Consequently, as input frequency and sampling rate increase, the decrease of available tracking or settling time results in the increasing requirement of input driver capacity or op-amp’s bandwidth, respectively. In addition, the involved narrow pulse is difficult to be precisely generated under high sampling rate conditions.
Assuming a sinusoidal signal with ±Vref input range, which can be written as Vin=Vref·sin(2πfint), where fin is the input frequency, the worst case for ADC happens at the maximum input slop as
dVin dt
max
= 2π ⋅ f in ⋅ Vref
(1)
In order to adjust the aperture error by digital redundancy correction, the maximum error has to be less than 0.125Vref according to the 2.5-bit MDAC transfer curve shown in Fig.3, which is expressed as
B. Proposed Design In this design, a 2.5-bit MDAC structure with a novel approach to avoid the involved pulse in conventional strategies is applied as the first stage. The architecture of this front-end MDAC with the employed dynamic comparator is shown in Fig.2. Assuming that the pre-amplifier is capable of tracking the comparison difference so well that the aperture error caused by sampling path mismatch can be tolerated, it is feasible to use the sampling edge to control the latch thus to
1 Ve max = 2π ⋅ f in ⋅ Vref ⋅ (Δt ) < Vref 8
Figure 2. Proposed first stage architecture for SHA-eliminating and comparator 799
(2)
Figure 4. Architecture of the 12-bit SHA-eliminating pipelined ADC
In order to reject common mode distortion and improve linearity, all the modules in the ADC core are designed using differential configuration. Two-stage symmetrical op-amps with gain-boosting are designed carefully to reach the desired gain and bandwidth under 1.2V power supply. All the sampling switches use traditional boot-strapped switch architecture [5] to prevent linearity deterioration.
Figure 3. Sketch of aperture error and 2.5-bit MDAC transfer curve
ΔRad max = 2π ⋅
1 ⋅ f in = 0.125rad Δt max
(3)
where ΔRadmax and Δtmax are the phase and time mismatch tolerance limit, respectively.
The value of sampling capacitors and op-amps’ specification are scaled down in subsequent stages to reduce power dissipation. The non-overlap clock is generated separately for each stage to minimize the global wiring. Onchip reference buffer is also introduced to avoid the fluctuation brought by related switched capacitor circuits. No additional calibration technique is used in this design to avoid the disadvantage of added calibration cycle.
During the tracking phase, considering the small-signal operation, the path through input port to pre-amplifier output can be modeled as a single pole common-source amplifier system while assuming that the input RC delay of both comparator and MDAC can be neglected comparing to the pre-amplifier’s bandwidth, by which the aperture error is determined, thus the pre-amplifier’s bandwidth requirement can be extracted as
tan −1 (
f in f BW max
) = ΔRad max
V.
(4)
According to the calculation, the bandwidth of the preamplifier should be designed greater than approximately 6.4 GHz to limit the aperture error within the correction range when fin reaches 800MHz. Meanwhile, pre-amplifier’s slew rate has to guarantee such bandwidth when considering the large-signal operation. Thus a large bandwidth dynamic comparator with high slew rate (in Fig.2) is designed to obtain high tracking speed. AC analyzing shows that the designed pre-amplifier achieves 8GHz bandwidth during its operational phase at all-corner conditions while the slew rate is more than 42V/ns, which is enough to support such large bandwidth. The post-layout simulation indicates that the 1st stage is still able to proper function when receiving an 800MHz sinusoidal signal. Though dynamic comparators in the 1st stage totally cost 5mA average current while MDAC costs 70mA, it is still much less than the increasing power consumed by MDAC (if 30% settling time shorter [3]) that meets the same specification. More important, the conversion speed limit, which is mainly decided by op-amp’s bandwidth and settling time, can be extended by the proposed method. IV.
MEASUREMENT RESULTS
The pipelined ADC is fabricated in 130nm 1P8M CMOS technology. The chip micrograph is shown in Fig.5. The total area including bonding pads is 4mm2 with ADC core area of 1.7mm2. The ADC operates under core supply of 1.2V and I/O supply of 1.8V. The total power consumption is 250mW (including on-chip reference, excluding I/O LVDS drivers) at 270MS/s, and it can be lower to 200mW with virtually the same performance at a sampling rate of 200MS/s. The measured output FFT spectrum with 45.1MHz input signal at 200MS/s is shown in Fig.6, which exhibits SNDR of 65.6dB and SFDR of 81.0dBc. Fig.7 shows the DNL/INL plot. The result of 0.38LSB peak DNL and 0.84LSB peak INL is obtained at 200MS/s with 30.1MHz input. Fig.8 reveals the SNDR, SNR, THD and SFDR of the ADC for an input frequency sweep at 200MS/s and 270MS/s respectively (THD contains 2nd-10th harmonic).
PROTOTYPE ADC DESIGN
A prototype of 12-bit 270MS/s pipelined ADC with SHAeliminating front-end is developed, of which architecture is shown in Fig.4. The circuit consists of five 2.5-bit stages and a 2-bit backend flash. On-chip bandgap, reference, clock generator, SPI interface and LVDS output drivers are included. 800
Figure 5. Chip micrograph
VI.
ADC Output Spectrum 0
This paper presents a 12-bit 270MS/s pipelined ADC with 1.2V supply. A novel method to eliminate front-end SHA is established, and is verified by the experimental chip’s measurement results, showing SNR of 63.7dB and SFDR of 76.1dBc at 120.1MHz input frequency. The performance comparison with the prior arts is shown in Table I, which indicates that the proposed strategy will simplify the design while its FOM, defined as Power/(2ENOB×Fs), is competitive compared with other SHA-eliminating methods even at the highest conversion speed. The summary of the prototype’s specifications is shown in Table II.
-20
Fin = 45.1MHz @ 200MS/s SFDR = 81.0 dBc THD = 77.6 dBc SNR = 65.9 dB SNDR = 65.6 dB ENOB = 10.6 bit
Power (dB)
-40
-60
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
REFERENCES
Fi/Fs
Figure 6. ADC output spectrum
[1]
ADC Static Performances 1
[2]
DNL (LSB)
0.5
0
-0.5
[3] -1
0
500
1000
1500
2000
2500
Code
1
3000
3500
4000
[4]
INL (LSB)
0.5
0
-0.5
-1
[5] 0
500
1000
1500
2000
2500
Code
3000
3500
4000
[6]
Figure 7. Static performances (Fs=200MS/s, Fin=30.1MHz) SNDR, SNR, THD, SFDR vs. Fin (Fs=200MS/s & 270MS/s) Fs=200MS/s
85 80
SFDR THD SNR SNDR
Byun-Moo Min, P. Kim, F. W. Bowman, D. M. Boisvert, and A. J. Aude “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 38, pp 2031-2039, December 2003. Kush Gulati, M. Shang Peng, A. Pulincherry, C. E. Munoz, M. Lugin, et al, “A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs,” IEEE J. Solid-State Circuits, vol. 41, pp 1856-1866, August 2006. Byung-Geun Lee, B. Min, G. Manganaro and J. W. Valvano, “A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC,” IEEE J. Solid-State Circuits, vol. 43, pp 2613-2619, December 2008. Siddharth Devarajan, L. Singer, D. Kelly, S. Decker, A. Kamath and P Wilkins, “A 16-bit, 125MS/s, 385mW, 78.7dB SNR CMOS Pipeline ADC,” IEEE J. Solid-State Circuits, vol. 44, pp 3305-3313, December 2009. Mikko Waltari and L. Sumanen , “A Self-Calirated Pipeline ADC with 200 MHz IF-Sampling Frontend”, AICSP, vol. 37, pp 201-213, 2003. Dong-Hyun Hwang, J. E. Song, S. P. Nam, H. J. Kim, T. J. An, K. S. Kim, and S. H. Lee, “A Range-Scaled 13b 100MS/s 0.13um CMOS SHA-Free ADC Based on a Single Reference”, ISOCC, pp 62-65, 2011.
TABLE II.
75
dB
CONCLUSION
SUMMARY OF SPECIFICATIONS
70
Technology
130nm 1P8M CMOS
65
Resolution
12 bits
60 55
50
100
150
200
Supply voltage
250
Input Frequency (MHz)
Fs=270MS/s
85 80
SFDR THD SNR SNDR
Power consumption
dB
75
Core: 1.2V I/O: 1.8V Core: 250mW@270MS/s Including on-chip reference I/O drivers: 90mW
70
Input range
1.2Vpp (differential)
65
Total area (with pad)
2mm×2mm
Sampling rate ENOB (Fin=30.1MHz) (Fin=70.1MHz) (Fin=120.1MHz) SNR (Fin=30.1MHz) (Fin=70.1MHz) (Fin=120.1MHz) SFDR (Fin=30.1MHz) (Fin=70.1MHz) (Fin=120.1MHz) THD (Fin=30.1MHz) (Fin=70.1MHz) (Fin=120.1MHz) Peak DNL (Fin=30.1MHz)
200MS/s 270MS/s 10.3 bits 10.6 bits 10.2 bits 10.6 bits 10.2 bits 10.4 bits 64.4 dB 65.9 dB 64.0 dB 65.7 dB 63.7 dB 64.7 dB 77.2 dBc 82.4 dBc 73.6 dBc 77.8 dBc 76.1 dBc 77.4 dBc 74.7 dBc 78.2 dBc 70.8 dBc 76.4 dBc 72.2 dBc 74.4 dBc 0.38 LSB
Peak INL (Fin=30.1MHz)
0.84 LSB
60 55
50
100
150
200
250
Input Frequency (MHz)
Figure 8. Dynamic performances versus input frequency
TABLE I. Resolution Supply Sampling Power (core) ENOB @Fin(Hz) FOM (pJ/Conv)
PERFORMANCE COMPARISON WITH THE PRIOR ARTS [2] 13 bits 3.3V 180MS/s 756mW 10.6 bits @15M
[3] 14 bits 3.0V 100MS/s 230mW 11.7 bits @39M
[6] 13 bits 1.3V 100MS/s 146mW 10.4 bits @4M
2.71
0.70
1.08
This work 12 bits 1.2V 200MS/s 270MS/s 200mW 250mW 10.6 bits 10.3 bits @30M @30M 0.65
0.74
801
