A 12b 50 MS/s 21.6 mW 0.18 m CMOS ADC ... - Semantic Scholar
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011
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A 12b 50 MS/s 21.6 mW 0.18 m CMOS ADC Maximally Sharing Capacitors and Op-Amps Kyung-Hoon Lee, Student Member, IEEE, Kwang-Soo Kim, and Seung-Hoon Lee, Member, IEEE
Abstract—A 12b 50 MS/s 0.18 m CMOS pipeline ADC is described. The proposed capacitor and operational amplifier (op-amp) sharing techniques merge the front-end sample-and-hold amplifier (SHA) and the first multiplying digital-to-analog converter (MDAC1) to achieve low power without an additional reset timing and a memory effect. The second and third MDACs share a single op-amp to reduce power consumption further. A shared op-amp of the merged SHA and MDAC1 controls properly the input trans-conductance for stability at each clock phase of holding and amplifying. The prototype ADC in a 0.18 m CMOS process demonstrates the measured differential and integral nonlinearities within 0.53 LSB and 2.09 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 60.6 dB and a maximum spurious-free dynamic range of 69.4 dB at 50 MS/s. The ADC with an active die area of 0.93 mm2 consumes 21.6 mW at 50 MS/s and 1.8 V. Index Terms—Analog-to-digital converter (ADC), capacitor sharing, CMOS, low power, op-amp sharing, memory effect, pipeline.
I. INTRODUCTION ITH the recent development of communication systems and the increased multimedia information, high-quality display systems have been widely expanded to a variety of application areas such as education, entertainment, medical, military, and aerospace industries. Moreover, the trend of system-on-a-chip (SoC) based on advanced VLSI technologies has rapidly increased the demand for high performance analog-to-digital converters (ADCs) essential to the system interface. Particularly, the ADCs for the analog front-end of high-definition displays such as ultrasound vision systems, charge coupled devices, computed tomography scanners, and portable communication terminals require a resolution of 12b and a conversion rate of 50 MS/s level with low power and small chip area, simultaneously. Of various ADC architectures, the pipeline ADC has been commonly employed as one of the best candidates to meet the required specifications mentioned above [1]–[13]. Meanwhile, many circuit techniques such as switched operational amplifier (op-amp), op-amp sharing, sample-and-hold amplifier (SHA)-free front-end, and capacitor
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Manuscript received June 25, 2010; revised October 26, 2010, January 04, 2011; accepted January 18, 2011. Date of publication March 17, 2011; date of current version September 14, 2011. This work was supported by the IDEC of KAIST, the Basic Science Research Program through the National Research Foundation (NRF) funded by the Ministry of Education, Science and Technology under Project 2010-0007618, and the Ministry of Knowledge, Economy, Korea, under the University ITRC support program supervised by the National IT Industry Promotion Agency under Project NIPA-2010-C1090-1001-0003. This paper was recommended by Associate Editor R. Lofti. The authors are with the Department of Electronic Engineering, Sogang University, Seoul 121-742, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSI.2011.2112591
sharing have been invented to reduce the power consumption of power-hungry interstage amplifiers [14]–[25]. The switched op-amp technique saves power consumption by disconnecting a current path from a power supply during the nonamplifying phase of amplifiers [14]–[16]. However, this technique has no benefit in area saving since the required number of op-amps remains the same. The on and off switching of the dc bias current also causes a transient overshoot or a phase margin variation which degrades signal settling behavior. On the other hand, the op-amp sharing scheme shares a single op-amp between two adjacent pipeline stages operating at complementary clock phases to reduce power and area [17]–[19]. But, the extra signal-steering switches in analog signal paths introduce a finite series on-resistance, which degrades signal settling time. Moreover, the present sampled input can be affected by a residual charge from the previously sampled input in case the input summing nodes of op-amp are never reset. Power dissipation and die area can be reduced further by removing a front-end SHA employed for a wide input bandwidth [20]–[23]. However, the input bandwidth of the SHA-less circuit is somewhat limited due to the aperture error caused by a different input sampling time between the first-stage multiplying digital-to-analog converter (MDAC1) and the first-stage flash ADC (FLASH1). The limited input bandwidth can be relaxed by careful design and layout skills considering a matched RC delay between two different critical signal paths [21], [22]. In a 16 b-resolution high-speed SHA-less pipeline ADC, the nonlinear kickback glitch energy due to a voltage difference between a new analog input connected to the MDAC1 and the previous reference voltage from the FLASH1 can degrade the whole ADC linearity significantly. The problem can be partly solved by an extra charge-clearing clock between the amplifying and sampling clock phases [23]. On the other hand, the capacitor sharing scheme shares the capacitors between two adjacent pipeline stages, which reduces a capacitive load of the residue op-amp of the previous stage and allows a high sampling rate without extra power consumption [24], [25]. However, the memory effect due to a previous charge remaining in the capacitors limits a maximum achievable resolution since the shared capacitors during amplification are directly reused for signal sampling without reset. An additional clock phase to reset the shared capacitors and the input node of op-amp reduces the memory effect, but the additional clock degrades the overall ADC sampling speed [24]. This work describes a 12b 50 MS/s pipeline ADC sharing capacitors and op-amps as maximum as possible without additional clock phases and memory effect. The front-end SHA and MDAC1 are merged to reduce power consumption by sharing capacitors and a single op-amp, simultaneously, while the
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Fig. 2. SHA and MDAC1 configurations without capacitor sharing scheme.
Fig. 1. Proposed 12b 50 MS/s 0.18 m CMOS ADC.
second and third MDACs (MDAC2 and MDAC3) share a single op-amp to reduce power consumption further. The proposed capacitor sharing scheme based on two capacitor banks resets an unused capacitor bank without a separate reset timing. The shared op-amp with two NMOS input differential pairs resets the inactive input pair to overcome a conventional memory , of effect [26], [27], whereas the input trans-conductance, the shared op-amp is properly adjusted at each clock phase for stable operation. This paper is organized as follows. The proposed ADC architecture is discussed in Section II while Section III specifically describes the detailed circuit implementation. The measured results of the prototype ADC are summarized in Section IV. Finally, conclusion is given in Section V. II. PROPOSED ADC ARCHITECTURE The proposed 12b 50 MS/s ADC employs a 4-step pipeline architecture as shown in Fig. 1. The ADC consists of an input SHA, one 3 b and two 4 b MDACs, one 3 b and three 4 b flash ADCs, a digital correction logic (DCL) block with decimator, a clock generator, and on-chip current and voltage references. The input SHA and MDAC1 are merged as the SHADAC by sharing capacitors and a single op-amp, while the MDAC2 and MDAC3 share a single op-amp to reduce power consumption. The SHADAC employs a gate-bootstrapping technique in the input sampling network to reduce a sampling distortion at input frequencies exceeding the Nyquist rate [28]. III. CIRCUIT IMPLEMENTATION A. Proposed Capacitor Sharing Technique Recently many capacitor sharing techniques in ADCs have been developed to minimize power consumption and chip area [24], [25]. The configurations of the SHA and MDAC1 without any capacitor sharing scheme at each clock phase are shown in Fig. 2. In Fig. 2, the AS and AM are defined as the op-amps , and repfor the SHA and MDAC1 while the resents a digital code from the FLASH ADC1 and the output voltages of the MDAC1 and SHA, respectively. During the Q2 phase, the sampling capacitors of the MDAC1 become the load of the SHA. The circuits with two previously reported capacitor sharing schemes remove the sampling capacitors of the following stage as shown in Fig. 3, where the indicates the amplified residue voltage of the MDAC2. As a result, capacitive loads are
Fig. 3. SHA and MDAC1 based on two previously reported capacitor sharing schemes: (a) with an extra reset phase [24]; (b) with two capacitor banks [25].
considerably reduced, which allows low-power consumption for a target speed compared to the conventional switched-capacitor topology. The capacitor sharing scheme in Fig. 3(a) requires , to remove a memory effect due to the an extra clock, previous charge remaining in the shared capacitors [24]. Thus, this scheme reduces the overall ADC conversion speed. On the other hand, the capacitor sharing scheme based on two capacitor banks in Fig. 3(b) resets an unused capacitor bank to remove a residual charge without an extra clock phase [25]. However, the shared op-amp is always active for a full clock cycle and the nonreset input node of op-amp can produce the undesired memory effect as observed in the circled area of Fig. 3(b) [29]. The proposed capacitor sharing scheme in this work uses two capacitor banks and a single op-amp with two separate NMOS input differential pairs simultaneously to remove an extra clock phase and a memory effect, as shown in Fig. 4. When one capacitor bank is used for holding or amplifying operation, the other unused capacitor bank is reset to remove the previous residual charge. The shared op-amp with two separate NMOS input pairs resets the inactive input pair alternately to overcome a memory effect [26], [27]. The memory effect related to the proposed capacitor sharing scheme is analyzed in detail in Appendix. Table I compares the proposed capacitor sharing scheme with the previously reported capacitor sharing schemes based on 1.5 b MDACs and a single-ended op-amp topology. Although
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Fig. 4. SHA and MDAC1 with the proposed capacitor sharing technique. Fig. 5. Merged SHA and MDAC1 to be represented as SHADAC. TABLE I COMPARISON OF TWO PREVIOUSLY REPORTED CAPACITOR SHARING SCHEMES AND THE PROPOSED CAPACITOR SHARING SCHEME
the actual load capacitance should include the parasitic capacitance and the series capacitance of the sampling capacitor and the gate capacitance of the preamp in the flash subranging ADC, these capacitances are much smaller than the feedback capacitor in the 1.5 b MDAC and therefore can be neglected for quick comparison in Table I. The proposed technique halves the required number of op-amps and the load capacitance compared to the conventional switched-capacitor based configuration without using any capacitor sharing technique. Moreover, the proposed scheme does not need an extra clock phase for resetting the shared capacitors and the input nodes of op-amp. The input referred kT/C noise of the proposed technique is the same except for the CCS [25]. Although the input referred kT/C noise of the CCS [25] is 60% of the others, input signals are sampled in two capacitor banks, alternately, as shown in Fig. 3(b), which can introduce a harmonic distortion observed in the double sampling technique [30]. The only demerit of the proposed capacitor sharing technique is extra capacitors for two capacitor banks. However, the active die area for the extra capacitors is 0.009 mm , which occupies only 1% of the overall ADC size in this work. The proposed capacitor sharing technique based on two capacitor banks is somewhat similar to the double sampling technique [30] achieving a doubled sampling speed, while one of the main performance-limiting factors in the double sampling scheme is a timing mismatch between two different input signal paths. In the double sampling technique, analog input signals are independently sampled in two capacitor banks with separate sampling switches at each clock phase and the sampling instants are also different corresponding to each separate sampling clock phase, which can introduce severe harmonic distortion.
Fig. 6. Timing diagram and operation of each circuit block in the SHADAC.
On the other hand, the proposed capacitor sharing technique shares capacitors and op-amps between adjacent pipeline stages to reduce power consumption and chip area rather than to increase sampling speed. Furthermore, input signals are sampled , at the sampling phase and on a single sampling capacitor, transferred to two capacitor banks alternately. Therefore the proposed capacitor sharing technique does not have a timing mismatch problem as observed in the conventional double sampling technique. B. Proposed SHADAC Based on Two Capacitor Banks The proposed SHADAC, which merges the SHA and MDAC1, consists of two capacitor banks (C-bank X and C-bank Y), a single two-stage op-amp with two separate NMOS input differential pairs, and an input sampling network as shown in Fig. 5, where all the circuits are drawn in a single-ended version. A gate-bootstrapping circuit is employed in input sampling switches to obtain high accuracy and low distortion at input frequencies exceeding the Nyquist frequency by keeping the gate-source voltage of the sampling switches constant independently of the input signal level [28]. The clock signals for the proposed capacitor sharing scheme and the operations of the SHA, MDAC1, and two capacitor
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Fig. 7. SHADAC configurations at each clock phase. (a) Phase
. (b) Phase . (c) Phase . (d) Phase .
banks are detailed in Fig. 6. In this work, all of the timing clock signals are internally generated from a single master clock with simple digital logic gates. The configurations of the SHADAC corresponding to each clock phase are illustrated in Fig. 7, sequentially, from Phase to Phase . During the clock phase , an input signal, , , and the C-bank X is is sampled on the sampling capacitor, used for the residue amplification of the MDAC1 with an analog , corresponding to a digital code from the FLASH voltage, ADC1, while the unused C-bank Y is reset. During the clock phase , the sampled input signal in the sampling capacitor is transferred to the C-bank Y for the holding of the SHA and the sampling operation of the MDAC1, simultaneously, while the C-bank X used for amplification in the previous phase is reset for the next operation. During the clock phase , the next input signal is sampled in the sampling capacitor while the C-bank Y is used for the residue amplification of the MDAC1 and the unused C-bank X stays at the reset mode. During the clock phase , the C-bank Y used for amplification is reset and the sampled input signal is transferred to the C-bank X for the holding and sampling operations of the SHA and MDAC1, respectively. These operations are synchronized to the two nonoverlapped clock phases, Q1 and Q2, and therefore the proposed capacitor sharing technique does not need an extra clock phase to reset the shared capacitors. The proposed capacitor sharing technique based on two capacitor banks can suffer from device mismatch similar to channel mismatch commonly observed in the conventional time-interleaved multichannel ADCs [31], [32]. The device mismatch between two capacitor banks can be minimized with
Fig. 8. Two capacitor banks of the interdigitated layout style to minimize device mismatch.
the interdigitated layout alternately placing the unit capacitors of two banks with dummy capacitors at both ends, as shown in Fig. 8. The merged capacitor switching (MCS) scheme is also employed for a better capacitor matching accuracy [33]. The MCS technique halves the required number of unit capacitors by merging two unit capacitors to one while the unit capacitor size can be doubled, which improves the capacitor matching. In addition, all the unit capacitors are enclosed with the stacked metal lines to make the neighboring condition of each unit capacitor identical for high matching [34]. C. Trans-Conductance Controlled Op-Amp Sharing Technique The shared op-amp employed in the SHADAC is detailed in Fig. 9 with a corresponding timing diagram. The first-stage op-amp, AMP1, is based on a telescopic topology with three NMOS input differential pairs and three separate current paths while the second op-amp, AMP2, consists of a common-source topology with a stacked PMOS transistor to achieve a high dc
LEE et al.: A 12B 50 MS/S 21.6 MW 0.18 M CMOS ADC MAXIMALLY SHARING CAPACITORS AND OP-AMPS
Fig. 9. g -controlled op-amp in the SHADAC: (a) during the holding mode of the SHA, (b) during the amplifying mode of the MDAC1, and (c) timing diagram.
gain and a 1.5 output swing range at 1.8 V. Since the shared op-amp of the SHADAC is used continuously during both of the SHA and MDAC1 operations, the different loop gain and loading conditions of the shared op-amp need be considered at each clock phase. During Q1 when the op-amp is in the holding mode of the SHA, a feedback factor becomes 1/2 and a load capacitance is reduced since the feedback capacitor is used for the sampling capacitor of the MDAC1. On the other hand, during Q2, the MDAC1 drives the sampling capacitor of the MDAC2 as a load capacitance and amplifies a residue voltage with a feedback factor of 1/4. As a result, the shared op-amp needs to be optimized for proper bandwidth and stability at each clock phase. The proposed op-amp of the SHADAC employs an extra , current path to adjust the trans-conductance of AMP1, considering the required bandwidth, feedback factor, and phase margin. During the holding mode of the SHA, the extra current path reduces the bias current flowing into the input stage to 60% of I, as shown in Fig. 9(a), and thereby the is decreased to improve a phase margin for the SHA stability. On the other
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Fig. 10. Bandwidth and phase margin of the shared op-amp in the SHADAC : (a) without g -control and (b) with g -control technique.
hand, during the amplifying mode of the MDAC1, the extra current path is inactive and all the bias current of I flows into and bandwidth for a proper the input stage to increase the MDAC1 operation as illustrated in Fig. 9(b). The proposed op-amp topology is analyzed as follows. The two-stage op-amp with a conventional Miller compensation has , defined as (1), where , an open-loop gain, and are the trans-conductance and output resistance of the first and second op-amp, respectively. The dominant and nonand , are approximated like (2) and dominant poles, (3), respectively, where and are the load capacitance at the output and the compensation capacitance. When the op-amp has a feedback factor, , the corresponding loop bandwidth, dB, and phase margin, PM, are approximated in (4) and (5), respectively (1) (2) (3)
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(4) (5) The bandwidth and phase margin of the shared two-stage op-amp in the SHADAC are illustrated in Fig. 10. When the control as op-amp is optimized for the MDAC1 without the shown in Fig. 10(a), the phase margin at the holding mode of the SHA is not sufficient due to the large feedback factor like (5). This can degrade the overall ADC performance. With the control of Fig. 10(b), the bandwidth and phase margin of the MDAC1 are not changed, while those of the SHA are improved . The reduced increases the phase due to the reduced margin but decreases the open-loop gain and loop bandwidth as summarized in (1), (4), and (5). Although the open-loop gain and loop bandwidth of op-amp are somewhat decreased due to , the op-amp of this work satisfies the target the reduced specification at the holding mode of the SHA. The smaller feedback factor of the SHA than that of the MDAC1 extends a loop bandwidth and the proposed capacitor sharing scheme reduces the load capacitance of the SHA considerably. The loop band. width and phase margin are traded off by controlling The target specifications of the op-amp at the holding mode of the SHA are an open-loop gain of 72 dB and a loop-bandwidth of 141 MHz while those of the op-amp at the amplifying mode of the MDAC1 are an open-loop gain of 72 dB and a loop-bandwidth of 118 MHz, respectively. In this work, the simulated SHA shows an open-loop gain of 82 dB and a loop bandwidth of 281 MHz with a phase margin of 67 , while the simulated MDAC1 shows an open-loop gain of 86 dB and a loop bandwidth of 212 MHz with a phase margin of 70 , respectively, considering the design margin and settling behavior during transient simulations. On the other hand, the unit capacitance of two and , in the SHADAC is 500 fF concapacitor banks, sidering the thermal noise and matching accuracy. The simuat the holding mode of lated thermal noise with the reduced the SHA is 61 uVrms. Considering only the kT/C and op-amp thermal noise, the maximum achievable SNR is about 76 dB, satisfies the target specification. thereby the reduced The shared op-amp in the MDAC2 and MDAC3 is shown in Fig. 11 with a timing diagram. Since the MDAC2 and MDAC3 have the same feedback factor and similar characteristic, an is not necessary. In this work, extra current path to optimize the of AMP1 is properly controlled by changing the W/L size of input transistors based on the different loading and parasitic conditions at each amplifying mode. The unit capacitances of the MDAC2 and MDAC3 are 125 fF and 60 fF considering the thermal noise requirement, respectively. Two switches steering the input bias currents of AMP1 are turned on and off alternately with slightly overlapped clock and , and Q1B and Q2B, as phases, shown in Figs. 9 and 11, respectively. With the overlapped clock phases, the input bias currents of AMP1 flow continuously through a tail current mirror, whose gate is connected to a dynamic common-mode feedback voltage, CMFB1. The input signals of the next stage are sampled in the clock phases, Q1P and Q2P, just before Q1 and Q2 turn off, while the switching of Q1B and Q2B occurs in the nonoverlapped period of Q1 and
Fig. 11. (a) Shared op-amp in MDAC2 and MDAC3 and (b) timing diagram.
Fig. 12. Bias circuit for the telescopic op-amp insensitive to input commonmode voltage variations.
Q2 in the switched-capacitor circuits. As a result, the switching of Q1B and Q2B does not affect the signal settling behavior in the amplifying phases, Q1 and Q2, while the glitch energy of the shared op-amp is reduced and the op-amp shows a relatively fast settling behavior compared with the nonoverlapped clock phases [27]. D. Bias Circuit for the Telescopic Op-Amp Insensitive to Input Common-Mode Voltage Variations The shared op-amp of Figs. 9 and 11 employs a telescopic amplifier topology in the first stage. A bias circuit for the telescopic amplifier is proposed to minimize the effect of input common-mode voltage variations, as shown in Fig. 12. Defining the input and output common-mode voltage of the , the node voltages at T1, T2, and VB3 are amplifier as , and , respectively, while the saturation condition of transistors MN1 and MN2 is . On the other hand, the , voltage of T3 from the gate voltage of a transistor M3b, is and the drain voltage of a diode-connected . By controlling a current transistor M2 becomes properly, the proposed bias circuit enables all transistors of
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Fig. 13. Latched comparator.
Fig. 15. Measured DNL and INL.
Fig. 14. Die photograph of the prototype ADC.
the op-amp to operate in a saturation region regardless of input common-mode voltage variations. E. Comparator The comparator in the FLASH ADCs is shown in Fig. 13, which consists of an input stage, a preamp, and a latch. The sampling capacitor, , of 30 fF samples a reference voltage during the Q2 phase. During the next Q1 phase, the sampled reference voltage is compared to the input signal and the difference is amplified. Just before the low transition of Q1 phase, the latch turns on and performs a regeneration operation. The preamp prevents the latch offset and kickback effect from the latch to the input. IV. ADC IMPLEMETATION AND MEASUREMENTS The proposed 12b 50 MS/s prototype ADC is implemented in a 0.18 m CMOS technology as shown in Fig. 14. The ADC occupies an active die area of 0.93 mm including on-chip MOS decoupling capacitances of about 200 pF and dissipates 21.6 mW with on-chip voltage references consuming 4 mW at 50 MS/s and 1.8 V. In the proposed capacitor sharing technique, the sampled analog inputs are transferred to two capacitor banks, C-bank X and C-bank Y, and converted to the corresponding digital codes, alternately at each clock phase. If one clock phase is used for C-bank X, the other clock phase is always used only for C-bank Y. Therefore, the offset and capacitor mismatch between two capacitor banks can be easily analyzed and investigated by measuring the static and dynamic performance based on all of
Fig. 16. Measured FFT spectrum (fs = 50 MHz, fin = 4 MHz).
the sequentially captured digital outputs from two capacitor banks. The measured maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of the prototype ADC using two capacitor banks are 0.53 LSB and 2.09 LSB, which are similar to the results using only C-bank X. On the other hand, the DNL and INL using only C-bank Y are 0.54 LSB and 2.34 LSB, as shown in Fig. 15. This means that there is little device mismatch between capacitors of the C-bank X and C-bank Y at a 12b level, although a maximum achievable accuracy of the unit capacitor with this 0.18 m CMOS process is one of the major INL performance-limiting factors. The typical FFT spectrum of the ADC measured with a 1.5 input sinusoidal signal of 4 MHz at 50 MS/s is plotted in Fig. 16. The ADC shows a similar FFT spectrum regardless of which capacitor bank is employed. The measured dynamic performance of the prototype ADC input sinusoidal signal is summarized in Fig. 17. with a 1.5 The signal-to-noise-and-distortion ratio (SNDR) and spuriousfree dynamic range (SFDR) in Fig. 17(a) are measured with different sampling frequencies up to 60 MHz at a 4 MHz input. The SNDR and SFDR are maintained over 60.6 dB and 69.4 dB up to 50 MS/s, respectively. The SNDR and the SFDR in
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TABLE II PERFORMANCE SUMMARY OF THE PROTOTYPE ADC
V. CONCLUSION
Fig. 17. Measured SFDR and SNDR of the prototype ADC versus: (a) fs and (b) fin.
This work proposes a 12b 50 MS/s pipeline ADC based on capacitor and op-amp sharing techniques for high-definition display applications. The front-end SHA and MDAC1 are merged into the SHADAC by sharing capacitors and a single op-amp without extra reset clock and memory effect, while the MDAC2 and MDAC3 share a single op-amp to reduce power consumption and chip area furthermore. The shared op-amp of properly with an additional the SHADAC controls the input current path for robust operation at each clock phase. The interdigitated layout scheme placing each unit capacitor in two capacitor banks alternately with a dummy capacitor at both ends minimizes device mismatch while all unit capacitors are surrounded by all the available interconnection metal lines for highly matched capacitor environment. The prototype ADC implemented in a 0.18 m CMOS demonstrates a measured DNL and INL within 0.53 LSB and 2.09 LSB, respectively. The ADC with an active die area of 0.93 mm shows a maximum SNDR and SFDR of 60.6 dB and 69.4 dB, respectively, and a power dissipation of 21.6 mW at 1.8 V and 50 MS/s. APPENDIX
Fig. 18. FoM comparison of recently reported 12b CMOS ADCs operating above 30 MS/s.
Fig. 17(b) are measured with input frequencies increased up to 90 MHz at a sampling rate of 50 MS/s. The SNDR and SFDR are measured to be 58.0 dB and 67.4 dB, respectively, at the Nyquist rate input. With the input frequency up to 60 MHz, the SNDR and SFDR are maintained above 56.2 dB and 66.5 dB, respectively, while the SNDR and SFDR at input frequencies exceeding 90 MHz are degraded rapidly. The figure of merits (FoM), defined as (6), of the prototype ADC is 0.49 pJ/conv-step including the power consumption of on-chip voltage references. The recently reported CMOS ADCs with a resolution of 12b and a sampling clock rate exceeding 30 MS/s are compared with the proposed ADC in Fig. 18 and the overall ADC performance is summarized in Table II (6)
Memory effects occur due to the parasitic capacitance of the virtual ground node when op-amps are shared between adjacent stages in a pipeline ADC [29]. When the input summing node is always used without reset, the stored charge on the parasitic capacitance of the virtual ground node can change the output signal. However, in the proposed SHADAC, there is no memory effect during the holding operation of the SHA because the input summing node is reset at the sampling mode of the SHA. On the other hand, the error voltage caused by a memory effect affects the output voltage during the amplifying operation of the MDAC1, since the input summing node during the holding mode of the SHA is directly used during the amplifying operation of the MDAC1 without reset. In this Appendix, the output error voltage due to a memory effect during the amplifying operation of the MDAC1 in the proposed SHADAC is analyzed and compared with the inherent error voltage of the conventional 3 b MDAC1 with the same level of parasitic capacitance and finite open loop gain. The sampling and amplifying operations of the conventional 3 b MDAC1 are illustrated in Fig. 19, while the charge of an N-th input signal at the Q1 phase is expressed in (7) (7)
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Fig. 19. Conventional 3 b MDAC1 configurations at each clock phase.
It is assumed that the reference voltage applied to the capacitors at the Q2 amplifying mode of the MDAC1 is zero and there is no capacitor mismatch, since only the errors due to a memory effect are considered for simplicity of calculation. Then, the charge equation during Q2 is derived as (8)
Fig. 20. Proposed SHADAC configurations at each clock phase.
Using the charge conservation law, (10) and (11) are calculated as (12)
(8) Since the total charge should be conserved, (7) and (8) are summarized as (9)
(9) As a result, the error factor of the conventional 3 b MDAC1 at the Q2 amplifying phase. On the other hand, the operations based on the proposed SHADAC are illustrated in Fig. 20, where the N-th input signal sampled in the MDAC1 are stored in the feedback capacitors during the holding operation of the SHA. The charge of the N-th input signal during Q1 is expressed in (10)
is
(10) Assuming the reference voltage applied to the capacitors is zero for simplicity of calculation as mentioned above, the charge equation at the Q2 amplifying phase can be expressed as (11)
(11)
(12) As a result, the error factor of the SHADAC is at the amplifying phase. As illustrated in the analysis result of (9) and (12), the error factor due to a memory effect during the amplifying operation of the MDAC1 in the proposed SHADAC is smaller by approximately 20% than the error factor of the conventional MDAC1 based on the same parasitic capacitance and finite open loop gain. REFERENCES [1] J. Yuan, N. H. Farhat, and J. Van der Spiegel, “Background calibration with piecewise linearized error model for CMOS pipeline A/D converter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 1, pp. 311–321, Feb. 2008. [2] K. Chandrashekar, M. Corsi, J. Fattaruso, and B. Bakkaloglu, “A 20-MS/s to 40-MS/s reconfigurable pipeline ADC implemented with parallel OTA scaling,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 8, pp. 602–606, Aug. 2010. [3] L. Brooks and H. S. Lee, “A 12b, 50 MS/s, fully differential zerocrossing pipelined ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3329–3343, Dec. 2009. [4] Y. J. Kim, H. C. Choi, G. C. Ahn, and S. H. Lee, “A 12b 50 MS/s CMOS Nyquist A/D converter with a fully differential class-AB switched op-amp,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 620–628, Dec. 2010. [5] H. Yu, S. W. Chin, and B. C. Wong, “A 12b 50 Msps 34 mW pipelined ADC,” in Proc. CICC, Sep. 2008, pp. 297–300. [6] J. Yuan, N. Farhat, and J. Van der Spiegel, “A 50 MS/s 12-bit CMOS pipeline A/D converter with nonlinear background calibration,” in Proc. CICC, Sep. 2005, pp. 399–402. [7] A. Shabra and H. S. Lee, “A 12-bit mismatch-shaped pipeline A/D converter,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2001, pp. 211–212. [8] H. Ploeg, G. Hoogzaad, H. Termeer, M. Vertregt, and R. Roovers, “A 2.5 V 12b 54-Msample/s 0.25-um CMOS ADC in 1 mm with mixedsignal chopping and calibration,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1859–1867, Dec. 2001. [9] L. Singer, S. Ho, M. Timko, and D. Kelly, “A 12b 65 Msample/s CMOS ADC with 82 dB SFDR at 120 MHz,” in ISSCC Dig. Tech Papers, Feb. 2000, pp. 38–39.
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[10] E. Iroaga and B. Murmann, “A 12-bit 75-MS/s pipelined ADC using incomplete settling,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 748–756, Apr. 2007. [11] B. Murmann and B. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040–2050, Dec. 2003. [12] A. Loloee, A. Zanchi, H. Jin, S. Shehata, and E. Bartolome, “A 12b 80 Msps pipelined ADC core with 190 mW consumption from 3 V in 0.18 m digital CMOS,” in Proc. ESSCIRC, Sep. 2002, pp. 467–470. [13] C. R. Grace, P. J. Hurst, and S. H. Lewis, “A 12b 80 Msample/s pipelined ADC with bootstrapped digital calibration,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1038–1046, May 2005. [14] M. Waltari and K. A. I. Halonen, “1-V 9-bit pipelined switched-opamp ADC,” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 129–134, Jan. 2001. [15] H. C. Kim, D. K. Jeong, and W. C. Kim, “A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 4, pp. 795–801, Apr. 2006. [16] H. C. Choi, Y. J. Kim, K. H. Lee, Y. L. Kim, and S. H. Lee, “A 10 b 25 MS/s 4.8 mW 0.13 m CMOS ADC for switched-bias power-reduction techniques,” Int. J. Circuit Theory Appl., vol. 37, pp. 955–967, Nov. 2009. [17] K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, “A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers,” IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 312–320, Mar. 1997. [18] J. Li, X. Zeng, L. Xie, J. Chen, J. Zhang, and Y. Guo, “A 1.8-V 22-mW 10-bit 30-MS/s pipelined ADC for low-power subsampling applications,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 321–329, Feb. 2008. [19] B. M. Min, P. Kim, D. M. Boisvert, and A. J. Aude, “A 69-mW 10-bit 80-Msample/s pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2031–2039, Dec. 2003. [20] I. Mehr and L. Singer, “A 55-mW 10-bit 40-Msample/s Nyquist-rate CMOS ADC,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 318–325, Mar. 2000. [21] Y. D. Jeon, S. C. Lee, K. D. Kim, J. K. Kwon, and J. Kim, “A 4.7 mW 0.32 mm 10 b 30 MS/s pipelined ADC without a front-end S/H in 90 nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 456–457. [22] D. Y. Chang, “Design technique for a pipelined ADC without using a front-end sample-and-hold amplifier,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 11, pp. 2123–2132, Nov. 2004. [23] S. Devarajan, L. Singer, D. Kelly, S. Decker, A. Kamath, and P. Wilkins, “A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3305–3313, Dec. 2009. [24] B. G. Lee, B. M. Min, G. Manganaro, and J. W. Valvano, “A 14-b 100-MS/s pipelined ADC with a merged SHA and first MDAC,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2613–2619, Dec. 2008. [25] N. Sasidhar et al., “A low power pipelined ADC using capacitor and opamp sharing technique with a scheme to cancel the effect of signal dependent kickback,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2392–2401, Sep. 2009. [26] S. T. Ryu, B. S. Song, and K. Bacrania, “A 10-bit 50-MS/s pipelined ADC with opamp current reuse,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 475–485, Mar. 2007. [27] K. H. Lee, S. W. Lee, Y. J. Kim, K. S. Kim, and S. H. Lee, “Ten-bit 100 MS/s 24.2 mW 0.8 mm 0.18 m CMOS pipeline ADC based on maximal circuit sharing schemes,” Electron Lett., vol. 45, no. 25, pp. 1296–1297, Dec. 2009. [28] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599–606, May 1999. [29] J. P. Keane, P. J. Hurst, and S. H. Lewis, “Digital background calibration for memory effects in pipelined analog-to-digital converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 3, pp. 511–525, Mar. 2006. [30] M. Waltari and K. Halonen, “A 220-MSample/s CMOS sample-andhold circuit using double-sampling,” Analog Integr. Circuits Signal Process., vol. 18, no. 18, pp. 21–31, Jan. 1999.
[31] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp. 261–271, Mar. 2001. [32] H. C. Choi, Y. J. Kim, G. C. Ahn, and S. H. Lee, “A 1.2-V 12-b 120-MS/s SHA-free dual-channel Nyquist ADC based on midcode calibration,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 5, pp. 894–901, May 2009. [33] S. M. Yoo, T. H. Oh, J. W. Moon, S. H. Lee, and U. K. Moon, “A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR,” in Proc. CICC, Sep. 2002, pp. 441–444. [34] Y. J. Cho, K. H. Lee, H. C. Choi, S. H. Lee, K. H. Moon, and J. W. Kim, “A calibration-free 14 b 70 MS/s 3.3 mm 235 mW 0.13 m CMOS pipeline ADC with high-matching 3-D symmetric capacitors,” in Proc. CICC, Sep. 2006, pp. 485–488.
Kyung-Hoon Lee received the B.S., M.S., and Ph.D. degrees in electronics engineering from Sogang University, Seoul, Korea, in 2004, 2006, and 2011, respectively. He is currently a Senior Engineer at Samsung Electronics, Korea. His current interests are in the design of high-resolution low-power CMOS data converters and very high-speed mixed-mode integrated systems.
Kwang-Soo Kim received the B.S., M.S., and Ph.D. degrees in electronic engineering from Sogang University, Seoul, Korea, in 1981, 1983, and 1992, respectively. From 1982 to 1998 he was with the Electronics and Telecommunications Research Institute, working on silicon devices (CMOS, bipolar, and BiCMOS). From 1988 to 1992, he carried out his Ph.D. dissertation at Sogang on the high speed and high density BiCMOS device. From 1999 to 2005 he was Principal Research Engineer with IITA where he planned new component technology about information and communication technology of Korea. From 2005 to 2008 he was a Principal Research Engineer with DGIST, where he conducted research on IT convergence technology for intelligent vehicles. He joined Sogang University in 2008. Now, he is a Professor of Electrical Engineering in the Department of Sogang Institute of Advanced Technology at Sogang University. His current research interests focus on the technology, modeling, and reliability of sensors (pressure, acceleration and thermal sensors). He is also active in studying the technology of sensor interface circuits.
Seung-Hoon Lee received the B.S. and M.S. degrees with honors in electronic engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, in 1991. From 1990 to 1993, he was with Analog Devices Semiconductor, Wilmington, MA, as a Senior Design Engineer. Since 1993, he has been with the Department of Electronic Engineering, Sogang University, Seoul, Korea, where he is now a Professor. He has served as the chief editor of the IEEK Journal of Semiconductor Devices, Circuits, and Systems and a TPC member of many international and domestic conferences including the IEEE Symposium on VLSI Circuits. His current interest is in the design and testing of high-resolution high-speed CMOS data converters, CMOS communication circuits, integrated sensors, and mixed-mode integrated systems.
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A 12b 50 MS/s 21.6 mW 0.18 m CMOS ADC Maximally Sharing Capacitors and Op-Amps Kyung-Hoon Lee, Student Member, IEEE, Kwang-Soo Kim, and Seung-Hoon Lee, Member, IEEE
Abstract—A 12b 50 MS/s 0.18 m CMOS pipeline ADC is described. The proposed capacitor and operational amplifier (op-amp) sharing techniques merge the front-end sample-and-hold amplifier (SHA) and the first multiplying digital-to-analog converter (MDAC1) to achieve low power without an additional reset timing and a memory effect. The second and third MDACs share a single op-amp to reduce power consumption further. A shared op-amp of the merged SHA and MDAC1 controls properly the input trans-conductance for stability at each clock phase of holding and amplifying. The prototype ADC in a 0.18 m CMOS process demonstrates the measured differential and integral nonlinearities within 0.53 LSB and 2.09 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 60.6 dB and a maximum spurious-free dynamic range of 69.4 dB at 50 MS/s. The ADC with an active die area of 0.93 mm2 consumes 21.6 mW at 50 MS/s and 1.8 V. Index Terms—Analog-to-digital converter (ADC), capacitor sharing, CMOS, low power, op-amp sharing, memory effect, pipeline.
I. INTRODUCTION ITH the recent development of communication systems and the increased multimedia information, high-quality display systems have been widely expanded to a variety of application areas such as education, entertainment, medical, military, and aerospace industries. Moreover, the trend of system-on-a-chip (SoC) based on advanced VLSI technologies has rapidly increased the demand for high performance analog-to-digital converters (ADCs) essential to the system interface. Particularly, the ADCs for the analog front-end of high-definition displays such as ultrasound vision systems, charge coupled devices, computed tomography scanners, and portable communication terminals require a resolution of 12b and a conversion rate of 50 MS/s level with low power and small chip area, simultaneously. Of various ADC architectures, the pipeline ADC has been commonly employed as one of the best candidates to meet the required specifications mentioned above [1]–[13]. Meanwhile, many circuit techniques such as switched operational amplifier (op-amp), op-amp sharing, sample-and-hold amplifier (SHA)-free front-end, and capacitor
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Manuscript received June 25, 2010; revised October 26, 2010, January 04, 2011; accepted January 18, 2011. Date of publication March 17, 2011; date of current version September 14, 2011. This work was supported by the IDEC of KAIST, the Basic Science Research Program through the National Research Foundation (NRF) funded by the Ministry of Education, Science and Technology under Project 2010-0007618, and the Ministry of Knowledge, Economy, Korea, under the University ITRC support program supervised by the National IT Industry Promotion Agency under Project NIPA-2010-C1090-1001-0003. This paper was recommended by Associate Editor R. Lofti. The authors are with the Department of Electronic Engineering, Sogang University, Seoul 121-742, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSI.2011.2112591
sharing have been invented to reduce the power consumption of power-hungry interstage amplifiers [14]–[25]. The switched op-amp technique saves power consumption by disconnecting a current path from a power supply during the nonamplifying phase of amplifiers [14]–[16]. However, this technique has no benefit in area saving since the required number of op-amps remains the same. The on and off switching of the dc bias current also causes a transient overshoot or a phase margin variation which degrades signal settling behavior. On the other hand, the op-amp sharing scheme shares a single op-amp between two adjacent pipeline stages operating at complementary clock phases to reduce power and area [17]–[19]. But, the extra signal-steering switches in analog signal paths introduce a finite series on-resistance, which degrades signal settling time. Moreover, the present sampled input can be affected by a residual charge from the previously sampled input in case the input summing nodes of op-amp are never reset. Power dissipation and die area can be reduced further by removing a front-end SHA employed for a wide input bandwidth [20]–[23]. However, the input bandwidth of the SHA-less circuit is somewhat limited due to the aperture error caused by a different input sampling time between the first-stage multiplying digital-to-analog converter (MDAC1) and the first-stage flash ADC (FLASH1). The limited input bandwidth can be relaxed by careful design and layout skills considering a matched RC delay between two different critical signal paths [21], [22]. In a 16 b-resolution high-speed SHA-less pipeline ADC, the nonlinear kickback glitch energy due to a voltage difference between a new analog input connected to the MDAC1 and the previous reference voltage from the FLASH1 can degrade the whole ADC linearity significantly. The problem can be partly solved by an extra charge-clearing clock between the amplifying and sampling clock phases [23]. On the other hand, the capacitor sharing scheme shares the capacitors between two adjacent pipeline stages, which reduces a capacitive load of the residue op-amp of the previous stage and allows a high sampling rate without extra power consumption [24], [25]. However, the memory effect due to a previous charge remaining in the capacitors limits a maximum achievable resolution since the shared capacitors during amplification are directly reused for signal sampling without reset. An additional clock phase to reset the shared capacitors and the input node of op-amp reduces the memory effect, but the additional clock degrades the overall ADC sampling speed [24]. This work describes a 12b 50 MS/s pipeline ADC sharing capacitors and op-amps as maximum as possible without additional clock phases and memory effect. The front-end SHA and MDAC1 are merged to reduce power consumption by sharing capacitors and a single op-amp, simultaneously, while the
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Fig. 2. SHA and MDAC1 configurations without capacitor sharing scheme.
Fig. 1. Proposed 12b 50 MS/s 0.18 m CMOS ADC.
second and third MDACs (MDAC2 and MDAC3) share a single op-amp to reduce power consumption further. The proposed capacitor sharing scheme based on two capacitor banks resets an unused capacitor bank without a separate reset timing. The shared op-amp with two NMOS input differential pairs resets the inactive input pair to overcome a conventional memory , of effect [26], [27], whereas the input trans-conductance, the shared op-amp is properly adjusted at each clock phase for stable operation. This paper is organized as follows. The proposed ADC architecture is discussed in Section II while Section III specifically describes the detailed circuit implementation. The measured results of the prototype ADC are summarized in Section IV. Finally, conclusion is given in Section V. II. PROPOSED ADC ARCHITECTURE The proposed 12b 50 MS/s ADC employs a 4-step pipeline architecture as shown in Fig. 1. The ADC consists of an input SHA, one 3 b and two 4 b MDACs, one 3 b and three 4 b flash ADCs, a digital correction logic (DCL) block with decimator, a clock generator, and on-chip current and voltage references. The input SHA and MDAC1 are merged as the SHADAC by sharing capacitors and a single op-amp, while the MDAC2 and MDAC3 share a single op-amp to reduce power consumption. The SHADAC employs a gate-bootstrapping technique in the input sampling network to reduce a sampling distortion at input frequencies exceeding the Nyquist rate [28]. III. CIRCUIT IMPLEMENTATION A. Proposed Capacitor Sharing Technique Recently many capacitor sharing techniques in ADCs have been developed to minimize power consumption and chip area [24], [25]. The configurations of the SHA and MDAC1 without any capacitor sharing scheme at each clock phase are shown in Fig. 2. In Fig. 2, the AS and AM are defined as the op-amps , and repfor the SHA and MDAC1 while the resents a digital code from the FLASH ADC1 and the output voltages of the MDAC1 and SHA, respectively. During the Q2 phase, the sampling capacitors of the MDAC1 become the load of the SHA. The circuits with two previously reported capacitor sharing schemes remove the sampling capacitors of the following stage as shown in Fig. 3, where the indicates the amplified residue voltage of the MDAC2. As a result, capacitive loads are
Fig. 3. SHA and MDAC1 based on two previously reported capacitor sharing schemes: (a) with an extra reset phase [24]; (b) with two capacitor banks [25].
considerably reduced, which allows low-power consumption for a target speed compared to the conventional switched-capacitor topology. The capacitor sharing scheme in Fig. 3(a) requires , to remove a memory effect due to the an extra clock, previous charge remaining in the shared capacitors [24]. Thus, this scheme reduces the overall ADC conversion speed. On the other hand, the capacitor sharing scheme based on two capacitor banks in Fig. 3(b) resets an unused capacitor bank to remove a residual charge without an extra clock phase [25]. However, the shared op-amp is always active for a full clock cycle and the nonreset input node of op-amp can produce the undesired memory effect as observed in the circled area of Fig. 3(b) [29]. The proposed capacitor sharing scheme in this work uses two capacitor banks and a single op-amp with two separate NMOS input differential pairs simultaneously to remove an extra clock phase and a memory effect, as shown in Fig. 4. When one capacitor bank is used for holding or amplifying operation, the other unused capacitor bank is reset to remove the previous residual charge. The shared op-amp with two separate NMOS input pairs resets the inactive input pair alternately to overcome a memory effect [26], [27]. The memory effect related to the proposed capacitor sharing scheme is analyzed in detail in Appendix. Table I compares the proposed capacitor sharing scheme with the previously reported capacitor sharing schemes based on 1.5 b MDACs and a single-ended op-amp topology. Although
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Fig. 4. SHA and MDAC1 with the proposed capacitor sharing technique. Fig. 5. Merged SHA and MDAC1 to be represented as SHADAC. TABLE I COMPARISON OF TWO PREVIOUSLY REPORTED CAPACITOR SHARING SCHEMES AND THE PROPOSED CAPACITOR SHARING SCHEME
the actual load capacitance should include the parasitic capacitance and the series capacitance of the sampling capacitor and the gate capacitance of the preamp in the flash subranging ADC, these capacitances are much smaller than the feedback capacitor in the 1.5 b MDAC and therefore can be neglected for quick comparison in Table I. The proposed technique halves the required number of op-amps and the load capacitance compared to the conventional switched-capacitor based configuration without using any capacitor sharing technique. Moreover, the proposed scheme does not need an extra clock phase for resetting the shared capacitors and the input nodes of op-amp. The input referred kT/C noise of the proposed technique is the same except for the CCS [25]. Although the input referred kT/C noise of the CCS [25] is 60% of the others, input signals are sampled in two capacitor banks, alternately, as shown in Fig. 3(b), which can introduce a harmonic distortion observed in the double sampling technique [30]. The only demerit of the proposed capacitor sharing technique is extra capacitors for two capacitor banks. However, the active die area for the extra capacitors is 0.009 mm , which occupies only 1% of the overall ADC size in this work. The proposed capacitor sharing technique based on two capacitor banks is somewhat similar to the double sampling technique [30] achieving a doubled sampling speed, while one of the main performance-limiting factors in the double sampling scheme is a timing mismatch between two different input signal paths. In the double sampling technique, analog input signals are independently sampled in two capacitor banks with separate sampling switches at each clock phase and the sampling instants are also different corresponding to each separate sampling clock phase, which can introduce severe harmonic distortion.
Fig. 6. Timing diagram and operation of each circuit block in the SHADAC.
On the other hand, the proposed capacitor sharing technique shares capacitors and op-amps between adjacent pipeline stages to reduce power consumption and chip area rather than to increase sampling speed. Furthermore, input signals are sampled , at the sampling phase and on a single sampling capacitor, transferred to two capacitor banks alternately. Therefore the proposed capacitor sharing technique does not have a timing mismatch problem as observed in the conventional double sampling technique. B. Proposed SHADAC Based on Two Capacitor Banks The proposed SHADAC, which merges the SHA and MDAC1, consists of two capacitor banks (C-bank X and C-bank Y), a single two-stage op-amp with two separate NMOS input differential pairs, and an input sampling network as shown in Fig. 5, where all the circuits are drawn in a single-ended version. A gate-bootstrapping circuit is employed in input sampling switches to obtain high accuracy and low distortion at input frequencies exceeding the Nyquist frequency by keeping the gate-source voltage of the sampling switches constant independently of the input signal level [28]. The clock signals for the proposed capacitor sharing scheme and the operations of the SHA, MDAC1, and two capacitor
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Fig. 7. SHADAC configurations at each clock phase. (a) Phase
. (b) Phase . (c) Phase . (d) Phase .
banks are detailed in Fig. 6. In this work, all of the timing clock signals are internally generated from a single master clock with simple digital logic gates. The configurations of the SHADAC corresponding to each clock phase are illustrated in Fig. 7, sequentially, from Phase to Phase . During the clock phase , an input signal, , , and the C-bank X is is sampled on the sampling capacitor, used for the residue amplification of the MDAC1 with an analog , corresponding to a digital code from the FLASH voltage, ADC1, while the unused C-bank Y is reset. During the clock phase , the sampled input signal in the sampling capacitor is transferred to the C-bank Y for the holding of the SHA and the sampling operation of the MDAC1, simultaneously, while the C-bank X used for amplification in the previous phase is reset for the next operation. During the clock phase , the next input signal is sampled in the sampling capacitor while the C-bank Y is used for the residue amplification of the MDAC1 and the unused C-bank X stays at the reset mode. During the clock phase , the C-bank Y used for amplification is reset and the sampled input signal is transferred to the C-bank X for the holding and sampling operations of the SHA and MDAC1, respectively. These operations are synchronized to the two nonoverlapped clock phases, Q1 and Q2, and therefore the proposed capacitor sharing technique does not need an extra clock phase to reset the shared capacitors. The proposed capacitor sharing technique based on two capacitor banks can suffer from device mismatch similar to channel mismatch commonly observed in the conventional time-interleaved multichannel ADCs [31], [32]. The device mismatch between two capacitor banks can be minimized with
Fig. 8. Two capacitor banks of the interdigitated layout style to minimize device mismatch.
the interdigitated layout alternately placing the unit capacitors of two banks with dummy capacitors at both ends, as shown in Fig. 8. The merged capacitor switching (MCS) scheme is also employed for a better capacitor matching accuracy [33]. The MCS technique halves the required number of unit capacitors by merging two unit capacitors to one while the unit capacitor size can be doubled, which improves the capacitor matching. In addition, all the unit capacitors are enclosed with the stacked metal lines to make the neighboring condition of each unit capacitor identical for high matching [34]. C. Trans-Conductance Controlled Op-Amp Sharing Technique The shared op-amp employed in the SHADAC is detailed in Fig. 9 with a corresponding timing diagram. The first-stage op-amp, AMP1, is based on a telescopic topology with three NMOS input differential pairs and three separate current paths while the second op-amp, AMP2, consists of a common-source topology with a stacked PMOS transistor to achieve a high dc
LEE et al.: A 12B 50 MS/S 21.6 MW 0.18 M CMOS ADC MAXIMALLY SHARING CAPACITORS AND OP-AMPS
Fig. 9. g -controlled op-amp in the SHADAC: (a) during the holding mode of the SHA, (b) during the amplifying mode of the MDAC1, and (c) timing diagram.
gain and a 1.5 output swing range at 1.8 V. Since the shared op-amp of the SHADAC is used continuously during both of the SHA and MDAC1 operations, the different loop gain and loading conditions of the shared op-amp need be considered at each clock phase. During Q1 when the op-amp is in the holding mode of the SHA, a feedback factor becomes 1/2 and a load capacitance is reduced since the feedback capacitor is used for the sampling capacitor of the MDAC1. On the other hand, during Q2, the MDAC1 drives the sampling capacitor of the MDAC2 as a load capacitance and amplifies a residue voltage with a feedback factor of 1/4. As a result, the shared op-amp needs to be optimized for proper bandwidth and stability at each clock phase. The proposed op-amp of the SHADAC employs an extra , current path to adjust the trans-conductance of AMP1, considering the required bandwidth, feedback factor, and phase margin. During the holding mode of the SHA, the extra current path reduces the bias current flowing into the input stage to 60% of I, as shown in Fig. 9(a), and thereby the is decreased to improve a phase margin for the SHA stability. On the other
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Fig. 10. Bandwidth and phase margin of the shared op-amp in the SHADAC : (a) without g -control and (b) with g -control technique.
hand, during the amplifying mode of the MDAC1, the extra current path is inactive and all the bias current of I flows into and bandwidth for a proper the input stage to increase the MDAC1 operation as illustrated in Fig. 9(b). The proposed op-amp topology is analyzed as follows. The two-stage op-amp with a conventional Miller compensation has , defined as (1), where , an open-loop gain, and are the trans-conductance and output resistance of the first and second op-amp, respectively. The dominant and nonand , are approximated like (2) and dominant poles, (3), respectively, where and are the load capacitance at the output and the compensation capacitance. When the op-amp has a feedback factor, , the corresponding loop bandwidth, dB, and phase margin, PM, are approximated in (4) and (5), respectively (1) (2) (3)
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(4) (5) The bandwidth and phase margin of the shared two-stage op-amp in the SHADAC are illustrated in Fig. 10. When the control as op-amp is optimized for the MDAC1 without the shown in Fig. 10(a), the phase margin at the holding mode of the SHA is not sufficient due to the large feedback factor like (5). This can degrade the overall ADC performance. With the control of Fig. 10(b), the bandwidth and phase margin of the MDAC1 are not changed, while those of the SHA are improved . The reduced increases the phase due to the reduced margin but decreases the open-loop gain and loop bandwidth as summarized in (1), (4), and (5). Although the open-loop gain and loop bandwidth of op-amp are somewhat decreased due to , the op-amp of this work satisfies the target the reduced specification at the holding mode of the SHA. The smaller feedback factor of the SHA than that of the MDAC1 extends a loop bandwidth and the proposed capacitor sharing scheme reduces the load capacitance of the SHA considerably. The loop band. width and phase margin are traded off by controlling The target specifications of the op-amp at the holding mode of the SHA are an open-loop gain of 72 dB and a loop-bandwidth of 141 MHz while those of the op-amp at the amplifying mode of the MDAC1 are an open-loop gain of 72 dB and a loop-bandwidth of 118 MHz, respectively. In this work, the simulated SHA shows an open-loop gain of 82 dB and a loop bandwidth of 281 MHz with a phase margin of 67 , while the simulated MDAC1 shows an open-loop gain of 86 dB and a loop bandwidth of 212 MHz with a phase margin of 70 , respectively, considering the design margin and settling behavior during transient simulations. On the other hand, the unit capacitance of two and , in the SHADAC is 500 fF concapacitor banks, sidering the thermal noise and matching accuracy. The simuat the holding mode of lated thermal noise with the reduced the SHA is 61 uVrms. Considering only the kT/C and op-amp thermal noise, the maximum achievable SNR is about 76 dB, satisfies the target specification. thereby the reduced The shared op-amp in the MDAC2 and MDAC3 is shown in Fig. 11 with a timing diagram. Since the MDAC2 and MDAC3 have the same feedback factor and similar characteristic, an is not necessary. In this work, extra current path to optimize the of AMP1 is properly controlled by changing the W/L size of input transistors based on the different loading and parasitic conditions at each amplifying mode. The unit capacitances of the MDAC2 and MDAC3 are 125 fF and 60 fF considering the thermal noise requirement, respectively. Two switches steering the input bias currents of AMP1 are turned on and off alternately with slightly overlapped clock and , and Q1B and Q2B, as phases, shown in Figs. 9 and 11, respectively. With the overlapped clock phases, the input bias currents of AMP1 flow continuously through a tail current mirror, whose gate is connected to a dynamic common-mode feedback voltage, CMFB1. The input signals of the next stage are sampled in the clock phases, Q1P and Q2P, just before Q1 and Q2 turn off, while the switching of Q1B and Q2B occurs in the nonoverlapped period of Q1 and
Fig. 11. (a) Shared op-amp in MDAC2 and MDAC3 and (b) timing diagram.
Fig. 12. Bias circuit for the telescopic op-amp insensitive to input commonmode voltage variations.
Q2 in the switched-capacitor circuits. As a result, the switching of Q1B and Q2B does not affect the signal settling behavior in the amplifying phases, Q1 and Q2, while the glitch energy of the shared op-amp is reduced and the op-amp shows a relatively fast settling behavior compared with the nonoverlapped clock phases [27]. D. Bias Circuit for the Telescopic Op-Amp Insensitive to Input Common-Mode Voltage Variations The shared op-amp of Figs. 9 and 11 employs a telescopic amplifier topology in the first stage. A bias circuit for the telescopic amplifier is proposed to minimize the effect of input common-mode voltage variations, as shown in Fig. 12. Defining the input and output common-mode voltage of the , the node voltages at T1, T2, and VB3 are amplifier as , and , respectively, while the saturation condition of transistors MN1 and MN2 is . On the other hand, the , voltage of T3 from the gate voltage of a transistor M3b, is and the drain voltage of a diode-connected . By controlling a current transistor M2 becomes properly, the proposed bias circuit enables all transistors of
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Fig. 13. Latched comparator.
Fig. 15. Measured DNL and INL.
Fig. 14. Die photograph of the prototype ADC.
the op-amp to operate in a saturation region regardless of input common-mode voltage variations. E. Comparator The comparator in the FLASH ADCs is shown in Fig. 13, which consists of an input stage, a preamp, and a latch. The sampling capacitor, , of 30 fF samples a reference voltage during the Q2 phase. During the next Q1 phase, the sampled reference voltage is compared to the input signal and the difference is amplified. Just before the low transition of Q1 phase, the latch turns on and performs a regeneration operation. The preamp prevents the latch offset and kickback effect from the latch to the input. IV. ADC IMPLEMETATION AND MEASUREMENTS The proposed 12b 50 MS/s prototype ADC is implemented in a 0.18 m CMOS technology as shown in Fig. 14. The ADC occupies an active die area of 0.93 mm including on-chip MOS decoupling capacitances of about 200 pF and dissipates 21.6 mW with on-chip voltage references consuming 4 mW at 50 MS/s and 1.8 V. In the proposed capacitor sharing technique, the sampled analog inputs are transferred to two capacitor banks, C-bank X and C-bank Y, and converted to the corresponding digital codes, alternately at each clock phase. If one clock phase is used for C-bank X, the other clock phase is always used only for C-bank Y. Therefore, the offset and capacitor mismatch between two capacitor banks can be easily analyzed and investigated by measuring the static and dynamic performance based on all of
Fig. 16. Measured FFT spectrum (fs = 50 MHz, fin = 4 MHz).
the sequentially captured digital outputs from two capacitor banks. The measured maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of the prototype ADC using two capacitor banks are 0.53 LSB and 2.09 LSB, which are similar to the results using only C-bank X. On the other hand, the DNL and INL using only C-bank Y are 0.54 LSB and 2.34 LSB, as shown in Fig. 15. This means that there is little device mismatch between capacitors of the C-bank X and C-bank Y at a 12b level, although a maximum achievable accuracy of the unit capacitor with this 0.18 m CMOS process is one of the major INL performance-limiting factors. The typical FFT spectrum of the ADC measured with a 1.5 input sinusoidal signal of 4 MHz at 50 MS/s is plotted in Fig. 16. The ADC shows a similar FFT spectrum regardless of which capacitor bank is employed. The measured dynamic performance of the prototype ADC input sinusoidal signal is summarized in Fig. 17. with a 1.5 The signal-to-noise-and-distortion ratio (SNDR) and spuriousfree dynamic range (SFDR) in Fig. 17(a) are measured with different sampling frequencies up to 60 MHz at a 4 MHz input. The SNDR and SFDR are maintained over 60.6 dB and 69.4 dB up to 50 MS/s, respectively. The SNDR and the SFDR in
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TABLE II PERFORMANCE SUMMARY OF THE PROTOTYPE ADC
V. CONCLUSION
Fig. 17. Measured SFDR and SNDR of the prototype ADC versus: (a) fs and (b) fin.
This work proposes a 12b 50 MS/s pipeline ADC based on capacitor and op-amp sharing techniques for high-definition display applications. The front-end SHA and MDAC1 are merged into the SHADAC by sharing capacitors and a single op-amp without extra reset clock and memory effect, while the MDAC2 and MDAC3 share a single op-amp to reduce power consumption and chip area furthermore. The shared op-amp of properly with an additional the SHADAC controls the input current path for robust operation at each clock phase. The interdigitated layout scheme placing each unit capacitor in two capacitor banks alternately with a dummy capacitor at both ends minimizes device mismatch while all unit capacitors are surrounded by all the available interconnection metal lines for highly matched capacitor environment. The prototype ADC implemented in a 0.18 m CMOS demonstrates a measured DNL and INL within 0.53 LSB and 2.09 LSB, respectively. The ADC with an active die area of 0.93 mm shows a maximum SNDR and SFDR of 60.6 dB and 69.4 dB, respectively, and a power dissipation of 21.6 mW at 1.8 V and 50 MS/s. APPENDIX
Fig. 18. FoM comparison of recently reported 12b CMOS ADCs operating above 30 MS/s.
Fig. 17(b) are measured with input frequencies increased up to 90 MHz at a sampling rate of 50 MS/s. The SNDR and SFDR are measured to be 58.0 dB and 67.4 dB, respectively, at the Nyquist rate input. With the input frequency up to 60 MHz, the SNDR and SFDR are maintained above 56.2 dB and 66.5 dB, respectively, while the SNDR and SFDR at input frequencies exceeding 90 MHz are degraded rapidly. The figure of merits (FoM), defined as (6), of the prototype ADC is 0.49 pJ/conv-step including the power consumption of on-chip voltage references. The recently reported CMOS ADCs with a resolution of 12b and a sampling clock rate exceeding 30 MS/s are compared with the proposed ADC in Fig. 18 and the overall ADC performance is summarized in Table II (6)
Memory effects occur due to the parasitic capacitance of the virtual ground node when op-amps are shared between adjacent stages in a pipeline ADC [29]. When the input summing node is always used without reset, the stored charge on the parasitic capacitance of the virtual ground node can change the output signal. However, in the proposed SHADAC, there is no memory effect during the holding operation of the SHA because the input summing node is reset at the sampling mode of the SHA. On the other hand, the error voltage caused by a memory effect affects the output voltage during the amplifying operation of the MDAC1, since the input summing node during the holding mode of the SHA is directly used during the amplifying operation of the MDAC1 without reset. In this Appendix, the output error voltage due to a memory effect during the amplifying operation of the MDAC1 in the proposed SHADAC is analyzed and compared with the inherent error voltage of the conventional 3 b MDAC1 with the same level of parasitic capacitance and finite open loop gain. The sampling and amplifying operations of the conventional 3 b MDAC1 are illustrated in Fig. 19, while the charge of an N-th input signal at the Q1 phase is expressed in (7) (7)
LEE et al.: A 12B 50 MS/S 21.6 MW 0.18 M CMOS ADC MAXIMALLY SHARING CAPACITORS AND OP-AMPS
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Fig. 19. Conventional 3 b MDAC1 configurations at each clock phase.
It is assumed that the reference voltage applied to the capacitors at the Q2 amplifying mode of the MDAC1 is zero and there is no capacitor mismatch, since only the errors due to a memory effect are considered for simplicity of calculation. Then, the charge equation during Q2 is derived as (8)
Fig. 20. Proposed SHADAC configurations at each clock phase.
Using the charge conservation law, (10) and (11) are calculated as (12)
(8) Since the total charge should be conserved, (7) and (8) are summarized as (9)
(9) As a result, the error factor of the conventional 3 b MDAC1 at the Q2 amplifying phase. On the other hand, the operations based on the proposed SHADAC are illustrated in Fig. 20, where the N-th input signal sampled in the MDAC1 are stored in the feedback capacitors during the holding operation of the SHA. The charge of the N-th input signal during Q1 is expressed in (10)
is
(10) Assuming the reference voltage applied to the capacitors is zero for simplicity of calculation as mentioned above, the charge equation at the Q2 amplifying phase can be expressed as (11)
(11)
(12) As a result, the error factor of the SHADAC is at the amplifying phase. As illustrated in the analysis result of (9) and (12), the error factor due to a memory effect during the amplifying operation of the MDAC1 in the proposed SHADAC is smaller by approximately 20% than the error factor of the conventional MDAC1 based on the same parasitic capacitance and finite open loop gain. REFERENCES [1] J. Yuan, N. H. Farhat, and J. Van der Spiegel, “Background calibration with piecewise linearized error model for CMOS pipeline A/D converter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 1, pp. 311–321, Feb. 2008. [2] K. Chandrashekar, M. Corsi, J. Fattaruso, and B. Bakkaloglu, “A 20-MS/s to 40-MS/s reconfigurable pipeline ADC implemented with parallel OTA scaling,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 8, pp. 602–606, Aug. 2010. [3] L. Brooks and H. S. Lee, “A 12b, 50 MS/s, fully differential zerocrossing pipelined ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3329–3343, Dec. 2009. [4] Y. J. Kim, H. C. Choi, G. C. Ahn, and S. H. Lee, “A 12b 50 MS/s CMOS Nyquist A/D converter with a fully differential class-AB switched op-amp,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 620–628, Dec. 2010. [5] H. Yu, S. W. Chin, and B. C. Wong, “A 12b 50 Msps 34 mW pipelined ADC,” in Proc. CICC, Sep. 2008, pp. 297–300. [6] J. Yuan, N. Farhat, and J. Van der Spiegel, “A 50 MS/s 12-bit CMOS pipeline A/D converter with nonlinear background calibration,” in Proc. CICC, Sep. 2005, pp. 399–402. [7] A. Shabra and H. S. Lee, “A 12-bit mismatch-shaped pipeline A/D converter,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2001, pp. 211–212. [8] H. Ploeg, G. Hoogzaad, H. Termeer, M. Vertregt, and R. Roovers, “A 2.5 V 12b 54-Msample/s 0.25-um CMOS ADC in 1 mm with mixedsignal chopping and calibration,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1859–1867, Dec. 2001. [9] L. Singer, S. Ho, M. Timko, and D. Kelly, “A 12b 65 Msample/s CMOS ADC with 82 dB SFDR at 120 MHz,” in ISSCC Dig. Tech Papers, Feb. 2000, pp. 38–39.
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Kyung-Hoon Lee received the B.S., M.S., and Ph.D. degrees in electronics engineering from Sogang University, Seoul, Korea, in 2004, 2006, and 2011, respectively. He is currently a Senior Engineer at Samsung Electronics, Korea. His current interests are in the design of high-resolution low-power CMOS data converters and very high-speed mixed-mode integrated systems.
Kwang-Soo Kim received the B.S., M.S., and Ph.D. degrees in electronic engineering from Sogang University, Seoul, Korea, in 1981, 1983, and 1992, respectively. From 1982 to 1998 he was with the Electronics and Telecommunications Research Institute, working on silicon devices (CMOS, bipolar, and BiCMOS). From 1988 to 1992, he carried out his Ph.D. dissertation at Sogang on the high speed and high density BiCMOS device. From 1999 to 2005 he was Principal Research Engineer with IITA where he planned new component technology about information and communication technology of Korea. From 2005 to 2008 he was a Principal Research Engineer with DGIST, where he conducted research on IT convergence technology for intelligent vehicles. He joined Sogang University in 2008. Now, he is a Professor of Electrical Engineering in the Department of Sogang Institute of Advanced Technology at Sogang University. His current research interests focus on the technology, modeling, and reliability of sensors (pressure, acceleration and thermal sensors). He is also active in studying the technology of sensor interface circuits.
Seung-Hoon Lee received the B.S. and M.S. degrees with honors in electronic engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, in 1991. From 1990 to 1993, he was with Analog Devices Semiconductor, Wilmington, MA, as a Senior Design Engineer. Since 1993, he has been with the Department of Electronic Engineering, Sogang University, Seoul, Korea, where he is now a Professor. He has served as the chief editor of the IEEK Journal of Semiconductor Devices, Circuits, and Systems and a TPC member of many international and domestic conferences including the IEEE Symposium on VLSI Circuits. His current interest is in the design and testing of high-resolution high-speed CMOS data converters, CMOS communication circuits, integrated sensors, and mixed-mode integrated systems.
