a 1.5 v high-linearity cmos mixer for 2.4 ghz ... - Semantic Scholar
➠
➡ A 1.5 V HIGH-LINEARITY CMOS MIXER FOR 2.4 GHZ APPLICATIONS Hung-Che Wei, Ro-Min Weng and Kun-Yi Lin Dept. of Electrical Engineering, National Dong Hwa University 1, Sec. 2, Da Hsueh Rd., Shou-Feng Hualien, Taiwan, Republic of China Fax:+886-3-8634060 E-mail:[email protected] Antenna
ABSTRACT
Mixer
A folded-cascode mixer with a modified Class-AB transconductor for 2.4 GHz ISM band applications is presented in this paper. The mixer is composed of a modified Class-AB transconductor and a low-voltage design technique. The proposed architecture improves the performance of linearity in the RF front-end. Simulation results for the proposed mixer using tsmc 0.18 µm Mixed Signal CMOS process are: input 1-dB compression point (P-1dB) –1.15 dBm, input third-order intercept point (IIP3) 11 dBm, power conversion gain 1 dB, and single side-band noise figure 17.3 dB. The mixer consumes 5.86 mA of current from a 1.5 V power supply.
BPF
Amplifier
LNA
Demod
Oscillator
Fig. 1. Bluetooth high IF receiver architecture.
1. INTRODUCTION In recent years, demands for wireless service and capacity increase as well. For this reason, 2.4 GHz is the frequency band attracted more and more researchers. This frequency band is also called ISM band that is free to be used in the Industrial, Scientific and Medical applications. Up to now, there have been many protocols proposed for different purposes at the ISM band, such as Bluetooth and IEEE 802.11b. Bluetooth is the one that improves the wireless local area network (WLAN) realizing more conveniently. The specification was developed by the Bluetooth Special Interest Group (SIG) which composed of several international companies famous in the communication sphere. One typical receiver architecture applied in the bluetooth system is shown in Fig. 1[1]. Although many Bluetooth integrated circuits (ICs) have been accomplished, they were usually realized by various processes. In the radio frequency circuit design, Bipolar and GaAs are usually the main consideration to realize circuit integration due to their better performance in the radio frequency (RF) applications. For many digital blocks in the communication ICs were realized by CMOS process, an idea was proposed making all blocks in a chip, whether analog or digital one. The chip realized in entirely CMOS process can make cost and area scaledown efficiently. Thus to accomplish RF circuits by entire CMOS technology is much attracted. Mixer is an important component in an RF receiver that provides frequency translation from RF to the intermediate frequency (IF) called “down-convert”, or from IF to RF called “up-convert”. There are several RF parameters of a mixer, such as input thirdorder intercept point (IIP3), conversion gain, input 1-dB compression point (P-1dB), noise figure, port return loss and port-to-port isolation. Among these parameters, what determine the linearity
0-7803-8251-X/04/$17.00 ©2004 IEEE
of a mixer are IIP3 and P-1dB. IIP3 exhibits the effects of intermodulation terms in the nonlinear circuit. P-1dB represents the ceiling of the input power. In the front-end architecture, the cascade components influence overall linearity. The overall IIP3 performance in the front-end is calculated by
IIP 3total = [
1 A21 A2 A2 + + 1 2 + · · · ]−1 . IIP 31 IIP 32 IIP 33
(1)
The IIP3 magnitude of the n-th stage is given by IIP3n, and the nth loaded voltage gain represented by An. It shows the linearity of a front-end is dominated by the ones located following the first stage of the front-end[2]. The more IIP3n increases, the more IIP3total can be improved. Gilbert cell is a typical type used in mixers or multipliers, and has merits in noise performance, linearity, port-to-port isolation, high bandwidth, and current reuse. The conventional Gilbert cell mixer usually cascades three stages (transconductor stage, commutating stage and load stage). If the commutating stage is assumed ideal switches, overall Gilbert mixer linearity is dominated by the transconductor stage. The nonlinear phenomenon of the mixer is due to the square law of the MOS transistors or the exponential law of the Bipolar transistors in the transconductor stage. Due to the nonlinearity of the transconductor, the input signal linear range and harmonic suppression are limited. Although some characteristics of a Gilbert cell mixer are much better than other passive mixers, such as gain, isolation,· · · etc., its performance in IIP3 is not as good as passive ones.
I - 561
ISCAS 2004
➡
➡ Vdd
2. DESIGN METHODOLOGY OF MIXER The transconductor stage of the Gilbert cell mixer usually realized in a differential pair converts small voltage signals to small current signals. Nevertheless, it appears that the linearity of the Gilbert cell mixer is limited by the class-A transconductor composed of the differential pair[3]. Lots of methods have been proposed to improve for the linearity of the mixer due to the nonlinear phenomenon of the transconductor stage. Using source degeneration connected to the sources of the transconductor stage in a Gilbert cell mixer is commonly published[4, 5]. Trade-offs between the conversion gain and the linearity are considered by designers while using the method described previously. Another way to enhance the linearity of a mixer, is based on CMOS gm Cell composed of the tanh functions[6, 7]. As charge-injection method employs current injecting into the drain of the transistors in the transconductor stage, it increases the current in the transconductor stage and is proportional to the value of IIP3 and the conversion gain[8, 9]. But the improvement in the aspect of IIP3 is not much. Hence, A method to improve the linearity using a modified ClassAB high-linear transconductor is proposed[10], as shown in Fig. 2. While biased at saturation region, M1 and M4 convert the input RF voltage signal into small output current signal. M1 and M3 induce small current signals with the same phase, and M2 and M4 induce small current signals with the opposite phase. one of the merits is to realize matching network easily in the opposition to the common-source transconductors. The modified Class-AB high-linearity transconductor provides less linearity degeneration than the generally differential pair one. Let the aspects of M1–M8 to be the same values, relationships of the drain currents in the transistors M1–M8 are represented below: iD2 iD3 io
= = = = = =
|νRF |
≤
where kn
=
iD5 = iD6 iD7 = iD8 io + − io − (iD1 + iD8 ) − (iD4 + iD5 ) 4 kn · Iref · νRF 2gm · νRF Iref 2 kn
(2) (3)
(4) (5)
1 Wn ). µn Cox ( 2 Ln
√ The transconductor provides 2 times the input signal range of a differential pair one by verifying Eqn. 5, and the twice gm value of Class-AB transconductor stage by Eqn. 4. Experiment results of the architecture has showed excellent capability in Total Harmonic Distortion (THD) suppressing, and it is obviously that it has more linear region of the input signal, too. This transconductor can be used in the application of a mixer due to the wider input range and the better harmonic suppression. While CMOS linearity is dominated by the drain bias voltage and the current density[11], a low voltage design technique[12] is more appropriate than the cascade architecture. It is formed by LC tanks, bypass capacitors and current sources. The LC tank provides infinite impedance ideally while it resonates at the RF frequency. The function of bypass capacitors is to supply for ac
Load
Load
Iref io +
VH M9
M5
VG
M10
ioM6
M7
C1
M8
C2 RF-
RF M1
M2
M3
M4
Fig. 2. Modified Class-AB high-linear transconductor.
coupling branches. This design technique is easy to implement in all the circuits in a chip with on-chip passive devices. Due to the limitation of Q-factor in the on-chip inductor, a solution takes the place of LC tanks below the local oscillator (LO) stage with current sources. These current sources also provide high impedance below the LO stage [13]. There are trade-offs between the IIP3, conversion gain and noise figure in the design consideration of a mixer. While the gain of a front-end receiver can be compensated with other building blocks such as LNA, AGC,· · · etc., specification of a mixer can be optimized the performance of the linearity with the moderate conversion gain. Fig. 3 illustrates the proposed high-linearity folded-cascode mixer with a modified Class-AB transconductor stage. Input differential signal νRF injects into the drain of M1 and M4 and induces output currents via current mirrors M1–M2 and M3–M4. C1–L1 and C2–L2 both resonate at the frequency of 2.4 GHz. C3, C4, C5 and C6 are applied to be the DC-blocking capacitors. M5– M8 provide the promotion of the isolation in the mixer. M11–M14 are the commutating stages act as the switches ideally which biased by the bias tee architecture in the impedance matching network. To make M11–14 as ideal switches, the transistors are biased in the saturation region that is close to the triode region. Then the IF current signal is down-converted by the commutating stage and the RF signal injected from the source of M11–M14. It is translated into the voltage signal by the load stage consisted of M15, M16, R1 and R2. For testing and matching purposes, source followers are used as output buffers that not illustrated in Fig. 3. 3. SIMULATION RESULTS The simulation of the proposed mixer is based on tsmc 0.18 µm Mixed Signal CMOS RF models. Frequencies of three ports in the mixer are specified at RF Frequency of 2.4 GHz, LO frequency of 2.3 GHz and IF frequency of 100 MHz, respectively. The active current of mixer is about 5.86 mA from a 1.5 V supply voltage. While sweeping the LO power, Fig. 4 shows that the relationship between IIP3 and the conversion gain. We can choose an
I - 562
➡
➡ Vdd
Vdd
M15 L1
C1
L2
R1
C2
M16
R2
IF
B
IF-
A
Iref
LO
M11 M12
M13 M14
LO
LOM5
M10
M6
M7
M8
D
C5 C
C3
C4
RF
C6 RF-
M1
M9
M2
M3
Is
Is
M4
Fig. 3. Proposed mixer with the modified Class-AB transcoductor.
20 10
P IF (Simulated) Ideal
0
Output power (dBm)
appropriate LO power to achieve desired IIP3 and the conversion gain. The simulation results of input 1-dB compression point (P1dB) is shown in Fig. 5, which achieves –1.15 dBm alongside the various RF input power while applying –10 dBm LO power. As two-tone testing, two tones are located at 2.405 GHz and 2.395 GHz, respectively. Fig. 6 illustrates IIP3 measured to be 11 dBm. We contrast the simulation results of other mixers by the same design consideration in optimizing the linearity. The Layout of the proposed mixer is shown in Fig. 7. It uses a compact area of 1.24 × 1.17 mm2 . For the purpose of improving the isolation of the mixer, the strategy is to make the layout symmetrically as far as possible. We adopt the parallel connection of the capacitors realizing the large capacitance. Table 1 summarizes the simulation results of the proposed mixer. The proposed mixer represents excellent properties of the conversion gain and the linearity.
−10 −20 −30 −40 −50 −60 −70 −80 −60
−50
−40
−30
−20
−10
0
10
Input RF power (dBm) 25 20
Fig. 5. P-1dB of the proposed mixer.
GAIN IIP3
Gain (dB) and IIP3 (dBm)
15 10 5 0 −5 −10 −15 −20 −25 −30
−25
−20
−15
−10
−5
0
LO power (dBm)
Fig. 4. The simulation results of conversion gain and IIP3 versus LO power.
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Table 1. Performance summary of mixers. Ref. [14] This work Process (um) 0.35 0.18 Supply Voltage (V) 2 1.5 fRF (GHz) 0.9 2.4 0.8 2.3 fLO (GHz) Power consumption (mW) 7.2 8.8 LO Power (dBm) –7 –10 IIP3 (dBm) –3.3 11 P-1dB (dBm) –15.4 –1.15 Conversion Gain (dB) 1.1 1 SSB Noise Figure (dB) N.A. 17.3
20
➡
➠ 5. REFERENCES
20 0
P IF (Simulated) P IM3 (Simulated)
[1] J. P. K. Gilb, “Bluetooth radio architectures,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 3–6, June 2000.
Ideal
Output power (dBm)
−20 −40
[2] W. H. Hayward, Introduction to Radio Frequency Design, Englewood Cliffs, NJ: Prentice-Hall, 1982.
−60
[3] B. Gilbert, “The MICROMIXER: a highly linear variant of the Gilbert mixer using a bisymmetric Class-AB input stage,” IEEE Journal of Solid-State Circuits, vol. 32, no. 9, pp. 1412–1423, Sept. 1997.
−80 −100 −120
[4] C. H. Feng, F. Jonsson, M. Ismail and H. Olsson, “Analysis of nonlinearities in RF CMOS amplifiers ,” The 6th IEEE International Conference on Electronics, Circuits and Systems, vol. 1, pp. 137–140, 1999.
−140 −160 −60
−50
−40
−30
−20
−10
0
10
20
Input RF power (dBm)
[5] Q. Li, J. Zhang, W. Li and J. S. Yuan, “CMOS RF mixer no-linearity design,” Proceedings of the 44th IEEE Midwest Symposium on Circuits and Systems, vol. 2, pp. 808–811, Aug. 2001.
Fig. 6. IIP3 of the proposed mixer.
[6] B. Gilbert, “The multi-tanh principle: a tutorial overview,” IEEE Journal of Solid State Circuits, vol. 33, no. 1, pp. 2– 17, Jan. 1998. [7] C. C. Chang, R. M. Weng, J. C. Huang, K. Hsu and K. Y. Lin, “A 1.5 V high gain CMOS mixer for 2.4-GHz applications,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 782–785, May 2001. [8] L. A. NacEachern and T. Manku, “A charge-injection method for Gilbert cell biasing ,” IEEE Canadian Conference on Electrical and Computer Engineering, vol. 1, pp. 365–368, May 1998. [9] S. G. Lee and J. K. Choi, “Current-reuse bleeding mixer,” IEE Electronics Letters, vol. 36, no. 8, pp. 696–697, Apr. 2000. [10] G. Giustolisi, G. Palmisano and S. Pennisi, “High-linear class AB transconductor for high-frequency applications,” IEEE International Symposium on Circuits and Systems, vol. 5, pp. 169–172, May 2000.
Fig. 7. Layout of the proposed mixer.
[11] S. Kang, B. Choi and B. Kim, “Linearity analysis of CMOS for RF application,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 3, pp. 169–172, Mar. 2003. 4. CONCLUSION
[12] T. Manku, G. Beck and E. J. Shin, “A low-voltage design technique for RF integrated circuits,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 10, pp. 1408–1413, Oct. 1998.
A folded-cascode mixer with the modified Class-AB transconductor stage that improves the performances of IIP3 and the conversion gain is presented. The proposed mixer operates at 2.4 GHz and is suitable for radio frequency applications. It converts to the IF frequency of 100 MHz by mixing with the LO frequency of 2.3 GHz. Due to the linear effects of the following stages in the frontend receiver, we hope that highly linear performance of the mixer can improve the linearity of the overall front-end system. The simulation results show that this mixer achieves IIP3 of 11 dBm, P-1dB of –1.15 dBm and conversion gain of 1-dB in the power consumption of 8.8 mW. The behavior of the mixer exhibits relatively high linearity and conversion gain. The proposed mixer is fit for WLAN applications.
[13] C. C. Tang, W. S. Lu, L. D. Van and W. S. Feng, “A 2.4GHz CMOS down-conversion doubly balanced mixer with low supply voltage,” IEEE International Symposium on Circuits and Systems, vol. 4, pp. 794–797, May 2001. [14] C. F. Au-Yeung and K. K. M. Cheng, “CMOS mixer linearization by the low-frequency signal injection method,” IEEE MTT-S International Microwave Symposium Digest, vol. 1, pp. 95–98, June 2003.
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➡ A 1.5 V HIGH-LINEARITY CMOS MIXER FOR 2.4 GHZ APPLICATIONS Hung-Che Wei, Ro-Min Weng and Kun-Yi Lin Dept. of Electrical Engineering, National Dong Hwa University 1, Sec. 2, Da Hsueh Rd., Shou-Feng Hualien, Taiwan, Republic of China Fax:+886-3-8634060 E-mail:[email protected] Antenna
ABSTRACT
Mixer
A folded-cascode mixer with a modified Class-AB transconductor for 2.4 GHz ISM band applications is presented in this paper. The mixer is composed of a modified Class-AB transconductor and a low-voltage design technique. The proposed architecture improves the performance of linearity in the RF front-end. Simulation results for the proposed mixer using tsmc 0.18 µm Mixed Signal CMOS process are: input 1-dB compression point (P-1dB) –1.15 dBm, input third-order intercept point (IIP3) 11 dBm, power conversion gain 1 dB, and single side-band noise figure 17.3 dB. The mixer consumes 5.86 mA of current from a 1.5 V power supply.
BPF
Amplifier
LNA
Demod
Oscillator
Fig. 1. Bluetooth high IF receiver architecture.
1. INTRODUCTION In recent years, demands for wireless service and capacity increase as well. For this reason, 2.4 GHz is the frequency band attracted more and more researchers. This frequency band is also called ISM band that is free to be used in the Industrial, Scientific and Medical applications. Up to now, there have been many protocols proposed for different purposes at the ISM band, such as Bluetooth and IEEE 802.11b. Bluetooth is the one that improves the wireless local area network (WLAN) realizing more conveniently. The specification was developed by the Bluetooth Special Interest Group (SIG) which composed of several international companies famous in the communication sphere. One typical receiver architecture applied in the bluetooth system is shown in Fig. 1[1]. Although many Bluetooth integrated circuits (ICs) have been accomplished, they were usually realized by various processes. In the radio frequency circuit design, Bipolar and GaAs are usually the main consideration to realize circuit integration due to their better performance in the radio frequency (RF) applications. For many digital blocks in the communication ICs were realized by CMOS process, an idea was proposed making all blocks in a chip, whether analog or digital one. The chip realized in entirely CMOS process can make cost and area scaledown efficiently. Thus to accomplish RF circuits by entire CMOS technology is much attracted. Mixer is an important component in an RF receiver that provides frequency translation from RF to the intermediate frequency (IF) called “down-convert”, or from IF to RF called “up-convert”. There are several RF parameters of a mixer, such as input thirdorder intercept point (IIP3), conversion gain, input 1-dB compression point (P-1dB), noise figure, port return loss and port-to-port isolation. Among these parameters, what determine the linearity
0-7803-8251-X/04/$17.00 ©2004 IEEE
of a mixer are IIP3 and P-1dB. IIP3 exhibits the effects of intermodulation terms in the nonlinear circuit. P-1dB represents the ceiling of the input power. In the front-end architecture, the cascade components influence overall linearity. The overall IIP3 performance in the front-end is calculated by
IIP 3total = [
1 A21 A2 A2 + + 1 2 + · · · ]−1 . IIP 31 IIP 32 IIP 33
(1)
The IIP3 magnitude of the n-th stage is given by IIP3n, and the nth loaded voltage gain represented by An. It shows the linearity of a front-end is dominated by the ones located following the first stage of the front-end[2]. The more IIP3n increases, the more IIP3total can be improved. Gilbert cell is a typical type used in mixers or multipliers, and has merits in noise performance, linearity, port-to-port isolation, high bandwidth, and current reuse. The conventional Gilbert cell mixer usually cascades three stages (transconductor stage, commutating stage and load stage). If the commutating stage is assumed ideal switches, overall Gilbert mixer linearity is dominated by the transconductor stage. The nonlinear phenomenon of the mixer is due to the square law of the MOS transistors or the exponential law of the Bipolar transistors in the transconductor stage. Due to the nonlinearity of the transconductor, the input signal linear range and harmonic suppression are limited. Although some characteristics of a Gilbert cell mixer are much better than other passive mixers, such as gain, isolation,· · · etc., its performance in IIP3 is not as good as passive ones.
I - 561
ISCAS 2004
➡
➡ Vdd
2. DESIGN METHODOLOGY OF MIXER The transconductor stage of the Gilbert cell mixer usually realized in a differential pair converts small voltage signals to small current signals. Nevertheless, it appears that the linearity of the Gilbert cell mixer is limited by the class-A transconductor composed of the differential pair[3]. Lots of methods have been proposed to improve for the linearity of the mixer due to the nonlinear phenomenon of the transconductor stage. Using source degeneration connected to the sources of the transconductor stage in a Gilbert cell mixer is commonly published[4, 5]. Trade-offs between the conversion gain and the linearity are considered by designers while using the method described previously. Another way to enhance the linearity of a mixer, is based on CMOS gm Cell composed of the tanh functions[6, 7]. As charge-injection method employs current injecting into the drain of the transistors in the transconductor stage, it increases the current in the transconductor stage and is proportional to the value of IIP3 and the conversion gain[8, 9]. But the improvement in the aspect of IIP3 is not much. Hence, A method to improve the linearity using a modified ClassAB high-linear transconductor is proposed[10], as shown in Fig. 2. While biased at saturation region, M1 and M4 convert the input RF voltage signal into small output current signal. M1 and M3 induce small current signals with the same phase, and M2 and M4 induce small current signals with the opposite phase. one of the merits is to realize matching network easily in the opposition to the common-source transconductors. The modified Class-AB high-linearity transconductor provides less linearity degeneration than the generally differential pair one. Let the aspects of M1–M8 to be the same values, relationships of the drain currents in the transistors M1–M8 are represented below: iD2 iD3 io
= = = = = =
|νRF |
≤
where kn
=
iD5 = iD6 iD7 = iD8 io + − io − (iD1 + iD8 ) − (iD4 + iD5 ) 4 kn · Iref · νRF 2gm · νRF Iref 2 kn
(2) (3)
(4) (5)
1 Wn ). µn Cox ( 2 Ln
√ The transconductor provides 2 times the input signal range of a differential pair one by verifying Eqn. 5, and the twice gm value of Class-AB transconductor stage by Eqn. 4. Experiment results of the architecture has showed excellent capability in Total Harmonic Distortion (THD) suppressing, and it is obviously that it has more linear region of the input signal, too. This transconductor can be used in the application of a mixer due to the wider input range and the better harmonic suppression. While CMOS linearity is dominated by the drain bias voltage and the current density[11], a low voltage design technique[12] is more appropriate than the cascade architecture. It is formed by LC tanks, bypass capacitors and current sources. The LC tank provides infinite impedance ideally while it resonates at the RF frequency. The function of bypass capacitors is to supply for ac
Load
Load
Iref io +
VH M9
M5
VG
M10
ioM6
M7
C1
M8
C2 RF-
RF M1
M2
M3
M4
Fig. 2. Modified Class-AB high-linear transconductor.
coupling branches. This design technique is easy to implement in all the circuits in a chip with on-chip passive devices. Due to the limitation of Q-factor in the on-chip inductor, a solution takes the place of LC tanks below the local oscillator (LO) stage with current sources. These current sources also provide high impedance below the LO stage [13]. There are trade-offs between the IIP3, conversion gain and noise figure in the design consideration of a mixer. While the gain of a front-end receiver can be compensated with other building blocks such as LNA, AGC,· · · etc., specification of a mixer can be optimized the performance of the linearity with the moderate conversion gain. Fig. 3 illustrates the proposed high-linearity folded-cascode mixer with a modified Class-AB transconductor stage. Input differential signal νRF injects into the drain of M1 and M4 and induces output currents via current mirrors M1–M2 and M3–M4. C1–L1 and C2–L2 both resonate at the frequency of 2.4 GHz. C3, C4, C5 and C6 are applied to be the DC-blocking capacitors. M5– M8 provide the promotion of the isolation in the mixer. M11–M14 are the commutating stages act as the switches ideally which biased by the bias tee architecture in the impedance matching network. To make M11–14 as ideal switches, the transistors are biased in the saturation region that is close to the triode region. Then the IF current signal is down-converted by the commutating stage and the RF signal injected from the source of M11–M14. It is translated into the voltage signal by the load stage consisted of M15, M16, R1 and R2. For testing and matching purposes, source followers are used as output buffers that not illustrated in Fig. 3. 3. SIMULATION RESULTS The simulation of the proposed mixer is based on tsmc 0.18 µm Mixed Signal CMOS RF models. Frequencies of three ports in the mixer are specified at RF Frequency of 2.4 GHz, LO frequency of 2.3 GHz and IF frequency of 100 MHz, respectively. The active current of mixer is about 5.86 mA from a 1.5 V supply voltage. While sweeping the LO power, Fig. 4 shows that the relationship between IIP3 and the conversion gain. We can choose an
I - 562
➡
➡ Vdd
Vdd
M15 L1
C1
L2
R1
C2
M16
R2
IF
B
IF-
A
Iref
LO
M11 M12
M13 M14
LO
LOM5
M10
M6
M7
M8
D
C5 C
C3
C4
RF
C6 RF-
M1
M9
M2
M3
Is
Is
M4
Fig. 3. Proposed mixer with the modified Class-AB transcoductor.
20 10
P IF (Simulated) Ideal
0
Output power (dBm)
appropriate LO power to achieve desired IIP3 and the conversion gain. The simulation results of input 1-dB compression point (P1dB) is shown in Fig. 5, which achieves –1.15 dBm alongside the various RF input power while applying –10 dBm LO power. As two-tone testing, two tones are located at 2.405 GHz and 2.395 GHz, respectively. Fig. 6 illustrates IIP3 measured to be 11 dBm. We contrast the simulation results of other mixers by the same design consideration in optimizing the linearity. The Layout of the proposed mixer is shown in Fig. 7. It uses a compact area of 1.24 × 1.17 mm2 . For the purpose of improving the isolation of the mixer, the strategy is to make the layout symmetrically as far as possible. We adopt the parallel connection of the capacitors realizing the large capacitance. Table 1 summarizes the simulation results of the proposed mixer. The proposed mixer represents excellent properties of the conversion gain and the linearity.
−10 −20 −30 −40 −50 −60 −70 −80 −60
−50
−40
−30
−20
−10
0
10
Input RF power (dBm) 25 20
Fig. 5. P-1dB of the proposed mixer.
GAIN IIP3
Gain (dB) and IIP3 (dBm)
15 10 5 0 −5 −10 −15 −20 −25 −30
−25
−20
−15
−10
−5
0
LO power (dBm)
Fig. 4. The simulation results of conversion gain and IIP3 versus LO power.
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Table 1. Performance summary of mixers. Ref. [14] This work Process (um) 0.35 0.18 Supply Voltage (V) 2 1.5 fRF (GHz) 0.9 2.4 0.8 2.3 fLO (GHz) Power consumption (mW) 7.2 8.8 LO Power (dBm) –7 –10 IIP3 (dBm) –3.3 11 P-1dB (dBm) –15.4 –1.15 Conversion Gain (dB) 1.1 1 SSB Noise Figure (dB) N.A. 17.3
20
➡
➠ 5. REFERENCES
20 0
P IF (Simulated) P IM3 (Simulated)
[1] J. P. K. Gilb, “Bluetooth radio architectures,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 3–6, June 2000.
Ideal
Output power (dBm)
−20 −40
[2] W. H. Hayward, Introduction to Radio Frequency Design, Englewood Cliffs, NJ: Prentice-Hall, 1982.
−60
[3] B. Gilbert, “The MICROMIXER: a highly linear variant of the Gilbert mixer using a bisymmetric Class-AB input stage,” IEEE Journal of Solid-State Circuits, vol. 32, no. 9, pp. 1412–1423, Sept. 1997.
−80 −100 −120
[4] C. H. Feng, F. Jonsson, M. Ismail and H. Olsson, “Analysis of nonlinearities in RF CMOS amplifiers ,” The 6th IEEE International Conference on Electronics, Circuits and Systems, vol. 1, pp. 137–140, 1999.
−140 −160 −60
−50
−40
−30
−20
−10
0
10
20
Input RF power (dBm)
[5] Q. Li, J. Zhang, W. Li and J. S. Yuan, “CMOS RF mixer no-linearity design,” Proceedings of the 44th IEEE Midwest Symposium on Circuits and Systems, vol. 2, pp. 808–811, Aug. 2001.
Fig. 6. IIP3 of the proposed mixer.
[6] B. Gilbert, “The multi-tanh principle: a tutorial overview,” IEEE Journal of Solid State Circuits, vol. 33, no. 1, pp. 2– 17, Jan. 1998. [7] C. C. Chang, R. M. Weng, J. C. Huang, K. Hsu and K. Y. Lin, “A 1.5 V high gain CMOS mixer for 2.4-GHz applications,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 782–785, May 2001. [8] L. A. NacEachern and T. Manku, “A charge-injection method for Gilbert cell biasing ,” IEEE Canadian Conference on Electrical and Computer Engineering, vol. 1, pp. 365–368, May 1998. [9] S. G. Lee and J. K. Choi, “Current-reuse bleeding mixer,” IEE Electronics Letters, vol. 36, no. 8, pp. 696–697, Apr. 2000. [10] G. Giustolisi, G. Palmisano and S. Pennisi, “High-linear class AB transconductor for high-frequency applications,” IEEE International Symposium on Circuits and Systems, vol. 5, pp. 169–172, May 2000.
Fig. 7. Layout of the proposed mixer.
[11] S. Kang, B. Choi and B. Kim, “Linearity analysis of CMOS for RF application,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 3, pp. 169–172, Mar. 2003. 4. CONCLUSION
[12] T. Manku, G. Beck and E. J. Shin, “A low-voltage design technique for RF integrated circuits,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 10, pp. 1408–1413, Oct. 1998.
A folded-cascode mixer with the modified Class-AB transconductor stage that improves the performances of IIP3 and the conversion gain is presented. The proposed mixer operates at 2.4 GHz and is suitable for radio frequency applications. It converts to the IF frequency of 100 MHz by mixing with the LO frequency of 2.3 GHz. Due to the linear effects of the following stages in the frontend receiver, we hope that highly linear performance of the mixer can improve the linearity of the overall front-end system. The simulation results show that this mixer achieves IIP3 of 11 dBm, P-1dB of –1.15 dBm and conversion gain of 1-dB in the power consumption of 8.8 mW. The behavior of the mixer exhibits relatively high linearity and conversion gain. The proposed mixer is fit for WLAN applications.
[13] C. C. Tang, W. S. Lu, L. D. Van and W. S. Feng, “A 2.4GHz CMOS down-conversion doubly balanced mixer with low supply voltage,” IEEE International Symposium on Circuits and Systems, vol. 4, pp. 794–797, May 2001. [14] C. F. Au-Yeung and K. K. M. Cheng, “CMOS mixer linearization by the low-frequency signal injection method,” IEEE MTT-S International Microwave Symposium Digest, vol. 1, pp. 95–98, June 2003.
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