A 1.8V -0.18µm CMOS Lock-In Amplifier for Portable ... - IEEE Xplore
A 1.8V -0.18µm CMOS Lock-In Amplifier for Portable Applications P.M. Maya-Hern´andez, M.T. Sanz-Pascual
B. Calvo
Electronic Department ´ Instituto Nacional de Astrof´ısica, Optica y Electr´onica Tonantzintla, Puebla, M´exico Email: {paulina maya, materesa}@inaoep.mx
Group of Electronic Design, I3A University of Zaragoza Zaragoza, Spain Email: [email protected]
Abstract— This paper presents a new analog lock-in amplifier designed in a 0.18µm CMOS process with a single supply voltage of 1.8V . The proposed architecture, which recovers the signal of interest from noisy environments with errors below 4% for noise signals of the same amplitude as the signal of interest, is suitable for portable applications thanks to its reduced power consumption and single-supply voltage operation. Post-layout simulation results show a variable DC gain ranging from 20 to 40dB, input-referred noise of 28.3µmVrms , power consumption of 351.4µW and area of (253x52)µm2 .
I. I NTRODUCTION Smart sensors are systems where sensors and their associated electronics are integrated together. One of the problems encountered with some sensors is the low output signal level compared to the noise level, which can largely exceed the signal amplitude of interest, especially in noisy environments. This implies the need for special amplification techniques to increase the signal to noise ratio [1]. One possibility is the use of lock-in amplifiers (LIAs), which are based on a technique known as phase sensitive detection. This technique makes it possible to detect and measure the amplitude and phase of very small signals at a reference frequency f0 , even if there are sources of noise several orders of magnitude higher than the signal to be measured itself. Although LIAs are widely used in instrumentation, they are not currently marketed in an integrated manner. In fact, only a few integrated versions can be encountered in the literature [2-4] and most of them operate in dual supply mode, thus not being suitable for battery operated systems. This work explores an alternative implementation of an analogue LIA. It is based on an input voltage-to-current converter, followed by a current rectifier which acts as the mixer, plus a final transresistance amplifier. The circuit is designed to be used in portable applications, in particular for wireless sensor network systems. For this reason, it is powered by a single supply-compatible with battery operated systemsand minimum power consumption and size are looked for. As a result, both power dissipation and area are reduced with This work was supported by CONACYT 235415 master grant, CONACYT CB-SEP-2008-01-99901 Research Project and MICINN-FEDER (RYC-200803185).
978-1-4673-0219-7/12/$31.00 ©2012 IEEE
respect to previously reported LIAs. Section II presents the proposed lock-in amplifier in a general manner. Section III describes the basic building blocks of the proposed solution, integrated in a 1.8V − 0.18µm CMOS standard technology. In Section IV, a summary of post-layout simulation results is reported. Finally, some conclusions are drawn in Section V. II. P ROPOSED L OCK -I N A MPLIFIER A lock-in amplifier is a system which reduces the noise bandwidth through synchronous detection. In particular, its output signal is a DC voltage proportional to the amplitude of the input signal, which is modulated at the same frequency as a reference signal f0 [1]. The block diagram of a typical lock-in amplifier is shown in Fig. 1. Amplificador Input de Entrada Amplifier
-
Vin f0
V o1
Mixer
BPF V o2
LPF Vout
Vout_dc
+ f0
Fig. 1.
Block diagram of a typical lock-in amplifier
A sensor is excited by a signal with a known frequency f0 and its output is injected into the lock-in system. The first active block is a low noise amplifier which provides high gain. It may be followed by a band-pass filter to remove or attenuate the noise contribution at all the frequencies except for f0 . The next block is a mixer or Phase-Sensitive Detector (PSD), which multiplies the modulated input signal by the reference signal. By properly synchronizing the input and control signals to have the same frequency and phase values, the data signal is full-wave rectified at the output. In this way, the DC component may be easily extracted by means of a low-pass filter with a suitable low cut-off frequency. In most integrated LIAs found in literature, the input amplifier is a classic 3-opamp instrumentation amplifier whose gain is typically controlled through an external resistor Rgain . As for the mixer, it is usually based on a voltage amplifier stage with a switch-controlled ±1 gain. This is shown in Fig. 2(a). The LIA proposed in this paper totally differs from this approach. In order to reduce power consumption, it consists of a voltage-to-current converter followed by a resistorless mixer,
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a MOS current divider and a transimpedance amplifier (see Fig. 2(b)). Thus, not only the number of amplifiers is reduced but also the number of resistors, which consume otherwise most of the area and add noise to the circuit. The rectification of the signal is carried out in the current domain and gain adjustment is achieved through a 3-bit digitally programmable current divider. Amplifier In1
Mixer
+ _
R5 R1
R3
_ +
Vout
R4
R2
_ +
R7
2Vin Rdeg
(1)
Vref
R6
In2
Io1 =
Note that the dominant poles are located at nodes 1 and 2, so that an external capacitor Cext can be added as shown in fig. 3(b) to adjust the input stage bandwidth and thus reduce the noise contribution.
R8
_ +
Rgain
LPF
+ − The differential input voltage Vin = Vin − Vin is therefore driven to the terminals of the equivalent degeneration resistor 2Rdeg , generating a current signal Iac which is copied to the output branch. The single-output current is then given by:
Vdd M9
M9
Mixer
Transconductor Vin (f0 )
Rdeg
+ _
Io1
,
Iout Iout2
f0
M1
+TIA
M2
Vout_dc Vout
Ib
Ib
a0 a1 a2
(b)
M10 Vc
_
(a)
Rdeg/2
M9 Vc
LPF
Rf
M7
M7
M6
R-2R
Io1
M6
Ib
(a)
Vc
M9
Vc
M10
Io1 Vin+
M1 Vc M4 1
M5
M4 Vc M1
Iac
M2
Vin-
2
M2
M5
Cext
M8
(b)
Ib
Rdeg/2
Cext M3
M3
Gnd
Vdd/2
Fig. 3. (a) Composite p-channel device (b) P-type degenerated transconductor Fig. 2. Lock-in amplifiers: (a) previous implementations vs. (b) proposed topology
Finally, the low-pass filter (LPF) is passive and intended to be connected externally to the circuit (both in our implementation and in those encountered in literature). Future implementations will include an integrated filter.
B. Current Divider The implemented 3-bit current divider is an R−2R ladder as shown in Fig. 4 [6], where each PMOS transistor is equivalent to a resistance R.
III. M AIN B UILDING B LOCKS D ESIGN
Vb I´in
M3
In this section, each building block of the proposed LIA is presented and design hints are given. a2
M2' R
A. Transconductor The differential pair with source degeneration is one of the most popular transconductors. The requirement that the input pair transconductance gm be much higher than the inverse of the degeneration resistance Rdeg to attain high linearity is usually satisfied by employing large transistors and/or bias currents. However, this may not be desirable in terms of area and power consumption. An alternative is to boost the gm of the input pair by using a compound device as shown in Fig. 3 (a). The implementation of the transconductor stage is shown in Fig. 3(b). The input transistors (M1) serve as voltage followers buffering the input voltage to the degeneration resistor while the constant current sources M3 force any change in the resistor current to be directly reflected in the drain currents of M2. This topology was presented in [5], but in our case active cascodes are used in order to maximize the output impedance and enhance the gm -boosting action, thus increasing the accuracy of the total transconductance Gm =1/2Rdeg of the system. Two linear poly-silicon resistors Rdeg = 1kΩ were used to give more symmetry to the layout implementation of the circuit.
M2
a2
R 2 M3
a1
R
R M3 2 M3
M1' R
M1 R
a1
a0
M3 R
M 0' R
M0 R
a0 I out
Iout 2
Fig. 4.
Current ladder divider
0 The input current Iin is divided into two output currents, 0 0 Iout = ∆Iin and Iout2 = (1 − ∆)Iin . The division factor ∆ is controlled by a digital word A(3) = a2 , a1 , a0 and is given by:
" # n−1 X 1 ∆= n 1+ (2j − aj 2j ) with n=3 2 j=0
(2)
The output current is connected to the virtual ground (VDD /2) input of the next block, the transimpedance amplifier. Iout2 , in turn, is driven to VDD /2 for proper current division. The advantage of using parallel transistors to generate R/2 and one transistor to generate R is that the voltage drop between the input node and the current output nodes is smaller than it would be with 2 transistors in series to generate 2R and one transistor to generate R [7].
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C. Transimpedance Amplifier Fig. 5 shows the topology of the transimpedance amplifier (TIA). It consists of a single-stage differential amplifier and a linear poly-silicon feedback resistor Rf with 100kΩ value and a compensation capacitor of 500f F . If Iin is the current delivered by the current ladder, the output voltage is given by: Vout = −Iin Rf
(3)
Vdd M2
M2 Vout
Ib
The topology employed here was presented in [8] and is depicted in Fig. 6. The circuit operates as a current follower when the control signal ctrl is low and as a current inverter when ctrl is high. As the ctrl signal is in phase with the input signal, this results in a full rectification of the input current. IV. P ERFORMANCE S UMMARY The proposed LIA was designed in a 0.18µm CMOS process with 1.8V supply voltage. The layout of the circuit is shown in Figure 7. The low-pass filter (LPF) is not included in the layout because it will be implemented externally as a second order passive LPF with a cut-off frequency of 5Hz.
Cc Rf
Vin+= Vdd 2
M1
VinIin
M1
2Ib M4
M3
Gnd
Fig. 5.
Transimpedance amplifier
Fig. 7.
Considering the cascade connection of the three blocks presented so far, the total gain of the system as a function of the digital word is given by the following expression: Vout Rf =− Vin Rdeg
! n−1 i X 1h j j (2 − aj 2 ) with n=3 1+ 2n j=0
(4)
A summary of the LIA post-layout main parameters is reported in Table I. Fig. 8(a) shows the transfer function gain for each digital word: the gain ranges from 20.9 to 39.5dB, with a constant bandwidth of 1M Hz, which corresponds to a capacitor Cext = 3pF . The circuit consumes 352µW , from which 27.9% is due to the mixer. Thus, an optimization of the mixer design would fairly reduce power.
That is, it is equivalent to a programmable gain amplifier whose gain depends on the Rf to Rdeg ratio and on the current ladder digital word. Note that both Rf and Rdeg are implemented with the same material, so both will suffer the same variations with process and temperature, thus ensuring good accuracy and robustness. Furthermore, current division is highly linear [6], and so is the whole system.
TABLE I LIA E LECTRIC C HARACTERIZATION
D. Mixer As was shown in fig. 2(b), an additional block is inserted between the voltage-to-current converter and the current divider, namely, a mixer. Its function is to carry out the phase sensitive detection over the signal and thus provide a fully rectified output current with a DC component proportional to the signal of interest and (almost) independent of noise. Vdd Ib
M7
Vc
M1
M5
M9 M9
Vc
ctrl
M8
Vc
M7 M7
M10 Vc
Io1
Iin
ctrl
M10
Io1 Io1'
ctrl ctrl
M4
M3
Ib
M7 M2
Vdd 2
M6
M8 M7 M7
M7
M7
Vc
M9
Vc
ctrl
M9
M9
M9 Gnd
Fig. 6.
Vc
Mixer
M9 M9 M9 M9
Vc
ctrl
M9 M9
Layout of the proposed lock-in amplifier
Parameter
Value
Gain (dB)
20.9 − 39.5
BW (MHz)
1
Input-referred noise ( µVrms )
28.3
CMRR (dB)
78.3
PSRR+ (dB)
57.3
PSRR- (dB)
50.6
Output Offset mV
2.7
Power Consumption (µW )
351.4
Area (µm2 )
253x52
As previously mentioned, in order to limit the noise, the bandwidth of the system can be adjusted by means of Cext . Fig. 8(b) shows the transfer function at maximum gain for different Cext values (3.1pF, 41pF, 415pF and 4.1nF to set a BW of 1M Hz, 100kHz, 10kHz and 1kHz, respectively). Thus, programmability can be used not only to adjust gain according to the input amplitude, but also to adjust bandwidth according to the input frequency. To test the performance of the circuit, three cases were studied. The amplifier was set to its maximum gain. For the first case the signal vs applied to the transconductor inputs was a sinusoidal voltage of 10mV at 1kHz frequency. For the second case, the signal vs was a sinusoidal voltage of 1mV
670
1.6
1.20
40 1.15
20
10
1.2
1.0
0-0-0 0-0-1 0-1-0 0-1-1 1-0-0 1-0-1 1-1-0 1-1-1
0
Vout_dc (V)
Vout (V)
Ganancia (dB)
1.4
1.05 1.00
0.8
0.95 0.6
0.0
100
1k
10k
100k
1M
1.0
2.0
3.0
4.0
0.90 0.0
5.0
100.0
Tiempo (ms)
10M
200.0
300.0
400.0
500.0
Tiempo (ms)
(a)
Frecuencia (Hz)
(a)
1.6
1.20 1.15
Vout (V)
20
Vout_dc (V)
1.4
40
Ganancia (dB)
1.10
1.2
1.0
1.10 1.05 1.00
0.8
0
0.95
4.1nF 414pF 41pF 3.1pF 0
-20 10
100
0.6
0.0
1.0
2.0
3.0
4.0
5.0
0.90 0.0
100.0
Tiempo (ms)
1k
10k
100k
1M
10M
200.0
300.0
400.0
500.0
Tiempo (ms)
(b)
Frecuencia (Hz)
(b)
Fig. 8.
Fig. 9. Rectified TIA output signal and LPF filter dc output for: (a) sinusoidal voltage of 10mV at 1KHz; (b) sinusoidal voltage of 1mV at 1KHz with an interfering sinusoidal signal of 10mV at 10KHz
(a) Gain Programability (b) BW variation with Cext
TABLE III C OMPARISON WITH PREVIOUSLY REPORTED LIA S
at 1kHz frequency. Finally, for the third case the signal vs was a sinusoidal voltage of 1mV at 1kHz frequency with an interfering sinusoidal vn of 10mV at 10kHz frequency. The theorical output Vout dc ideal and the post-layout simulation output Vout dc sim of the amplifier are reported in Table II for each case. TABLE II LIA E LECTRIC C HARACTERIZATION Cases
Vout
dc ideal
(V) Case 1 vs = 10mV @1kHz Case 2 vs = 1mV @1kHz Case 3 vs = 10mV @1kHz vn = 10mV @10kHz
1.218
Vout dc sim (V) 1.204
Relative Error 1.1%
0.932
0.940
0.8%
1.218
1.267
4%
Parameter
Proposed LIA
[2]
[3]
Gain (dB)
20.9 − 39.5
109
10 − 110
BW (kHz)
1000
50
−
Input-referred noise √ (nV / Hz)
5.9@1kHz
17@20kHz
34@77Hz
CMRR (dB)
117
> 60
−
PSRR+ (dB)
57.3
−
−
PSRR- (dB)
50.6
−
−
Output Offset (mV)
2.71
−
−
Consumption (mW )
0.35
25
3
Integrated Area (mm2 )
0.013
6.5
5
R EFERENCES
It can be noticed that the output of the three cases are well resolved by the amplifier with a small margin of error. Fig. 9 shows the rectified TIA output signal and LPF filter dc output for the first and the third case afore proposed to test the circuit. Finally, Table III compares the electric performance of the proposed LIA with other implementations found in the literature. V. C ONCLUSION A novel integrated lock-in amplifier has been presented which achieves very promising results with a reduction in power consumption and area compared to other existing solutions. The proposed architecture is able of recovering a signal of interest from noisy environments with a relative error lower than 4%. Future work contemplates the integration of the lowpass filter in the same chip to have a fully integrated solution.
[1] Lock-in amplifiers, appl. notes, Stanford Res. Sys., data sheets, 1999. [2] A. Gnudi, L Colalongo and G. Baccarani, Integrated Lock-In Amplifier for Sensor Aplications, Proc. IEEE Solid-State Circuits Conf: ESSCIRC, pp. 58-61, 1999. [3] A. DAmico, A. De Marcellis, C. DiCarlo, C. Di Natale, G. Ferri, E. Martinelli, R. Paolesse and V. Stornelli,Low-voltage low-power integrated analog lock-in amplifier for gas sensor applications, Sensors and Actuators, vol. 44, no. 2, pp. 400-406, 2008. [4] Jiawei Xu, Guy Meynants and Patrick Merken, Low-Power Lock-In Amplifier for Complex Impedance Measurement, IEEE Workshop on Advances in sensors and Interfaces: IWASI, pp. 110-114, 2009. [5] T. Kwan and K. Martin, An Adaptative Analog Continuos-Time CMOS Biquadratic Filter, IEEE Journal of Solid-State Circuits, vol. 26, pp.859867,1991. [6] K. Bult and G. Geelen, An inherently linear and compact MOST-only current division technique, IEEE J. Solid-State Circuits, vol. 27, n. 12, pp. 1730-1735, 1992. [7] M. Pastre and M. Kayal, Methodology for the Digital Calibration of Analog Circuits and Systems with Case Studies, Springer, 2006. [8] G. Zatorre, N. Medrano, M. T. Sanz, C. Aldea, B. Calvo and S. Celma, Digitally Programmable Analogue Circuits for Sensor Conditioning Systems, Sensors-Basel, vol. 9, no. 5, pp. 3652-3665, Neural Networks and Sensors, 2009.
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B. Calvo
Electronic Department ´ Instituto Nacional de Astrof´ısica, Optica y Electr´onica Tonantzintla, Puebla, M´exico Email: {paulina maya, materesa}@inaoep.mx
Group of Electronic Design, I3A University of Zaragoza Zaragoza, Spain Email: [email protected]
Abstract— This paper presents a new analog lock-in amplifier designed in a 0.18µm CMOS process with a single supply voltage of 1.8V . The proposed architecture, which recovers the signal of interest from noisy environments with errors below 4% for noise signals of the same amplitude as the signal of interest, is suitable for portable applications thanks to its reduced power consumption and single-supply voltage operation. Post-layout simulation results show a variable DC gain ranging from 20 to 40dB, input-referred noise of 28.3µmVrms , power consumption of 351.4µW and area of (253x52)µm2 .
I. I NTRODUCTION Smart sensors are systems where sensors and their associated electronics are integrated together. One of the problems encountered with some sensors is the low output signal level compared to the noise level, which can largely exceed the signal amplitude of interest, especially in noisy environments. This implies the need for special amplification techniques to increase the signal to noise ratio [1]. One possibility is the use of lock-in amplifiers (LIAs), which are based on a technique known as phase sensitive detection. This technique makes it possible to detect and measure the amplitude and phase of very small signals at a reference frequency f0 , even if there are sources of noise several orders of magnitude higher than the signal to be measured itself. Although LIAs are widely used in instrumentation, they are not currently marketed in an integrated manner. In fact, only a few integrated versions can be encountered in the literature [2-4] and most of them operate in dual supply mode, thus not being suitable for battery operated systems. This work explores an alternative implementation of an analogue LIA. It is based on an input voltage-to-current converter, followed by a current rectifier which acts as the mixer, plus a final transresistance amplifier. The circuit is designed to be used in portable applications, in particular for wireless sensor network systems. For this reason, it is powered by a single supply-compatible with battery operated systemsand minimum power consumption and size are looked for. As a result, both power dissipation and area are reduced with This work was supported by CONACYT 235415 master grant, CONACYT CB-SEP-2008-01-99901 Research Project and MICINN-FEDER (RYC-200803185).
978-1-4673-0219-7/12/$31.00 ©2012 IEEE
respect to previously reported LIAs. Section II presents the proposed lock-in amplifier in a general manner. Section III describes the basic building blocks of the proposed solution, integrated in a 1.8V − 0.18µm CMOS standard technology. In Section IV, a summary of post-layout simulation results is reported. Finally, some conclusions are drawn in Section V. II. P ROPOSED L OCK -I N A MPLIFIER A lock-in amplifier is a system which reduces the noise bandwidth through synchronous detection. In particular, its output signal is a DC voltage proportional to the amplitude of the input signal, which is modulated at the same frequency as a reference signal f0 [1]. The block diagram of a typical lock-in amplifier is shown in Fig. 1. Amplificador Input de Entrada Amplifier
-
Vin f0
V o1
Mixer
BPF V o2
LPF Vout
Vout_dc
+ f0
Fig. 1.
Block diagram of a typical lock-in amplifier
A sensor is excited by a signal with a known frequency f0 and its output is injected into the lock-in system. The first active block is a low noise amplifier which provides high gain. It may be followed by a band-pass filter to remove or attenuate the noise contribution at all the frequencies except for f0 . The next block is a mixer or Phase-Sensitive Detector (PSD), which multiplies the modulated input signal by the reference signal. By properly synchronizing the input and control signals to have the same frequency and phase values, the data signal is full-wave rectified at the output. In this way, the DC component may be easily extracted by means of a low-pass filter with a suitable low cut-off frequency. In most integrated LIAs found in literature, the input amplifier is a classic 3-opamp instrumentation amplifier whose gain is typically controlled through an external resistor Rgain . As for the mixer, it is usually based on a voltage amplifier stage with a switch-controlled ±1 gain. This is shown in Fig. 2(a). The LIA proposed in this paper totally differs from this approach. In order to reduce power consumption, it consists of a voltage-to-current converter followed by a resistorless mixer,
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a MOS current divider and a transimpedance amplifier (see Fig. 2(b)). Thus, not only the number of amplifiers is reduced but also the number of resistors, which consume otherwise most of the area and add noise to the circuit. The rectification of the signal is carried out in the current domain and gain adjustment is achieved through a 3-bit digitally programmable current divider. Amplifier In1
Mixer
+ _
R5 R1
R3
_ +
Vout
R4
R2
_ +
R7
2Vin Rdeg
(1)
Vref
R6
In2
Io1 =
Note that the dominant poles are located at nodes 1 and 2, so that an external capacitor Cext can be added as shown in fig. 3(b) to adjust the input stage bandwidth and thus reduce the noise contribution.
R8
_ +
Rgain
LPF
+ − The differential input voltage Vin = Vin − Vin is therefore driven to the terminals of the equivalent degeneration resistor 2Rdeg , generating a current signal Iac which is copied to the output branch. The single-output current is then given by:
Vdd M9
M9
Mixer
Transconductor Vin (f0 )
Rdeg
+ _
Io1
,
Iout Iout2
f0
M1
+TIA
M2
Vout_dc Vout
Ib
Ib
a0 a1 a2
(b)
M10 Vc
_
(a)
Rdeg/2
M9 Vc
LPF
Rf
M7
M7
M6
R-2R
Io1
M6
Ib
(a)
Vc
M9
Vc
M10
Io1 Vin+
M1 Vc M4 1
M5
M4 Vc M1
Iac
M2
Vin-
2
M2
M5
Cext
M8
(b)
Ib
Rdeg/2
Cext M3
M3
Gnd
Vdd/2
Fig. 3. (a) Composite p-channel device (b) P-type degenerated transconductor Fig. 2. Lock-in amplifiers: (a) previous implementations vs. (b) proposed topology
Finally, the low-pass filter (LPF) is passive and intended to be connected externally to the circuit (both in our implementation and in those encountered in literature). Future implementations will include an integrated filter.
B. Current Divider The implemented 3-bit current divider is an R−2R ladder as shown in Fig. 4 [6], where each PMOS transistor is equivalent to a resistance R.
III. M AIN B UILDING B LOCKS D ESIGN
Vb I´in
M3
In this section, each building block of the proposed LIA is presented and design hints are given. a2
M2' R
A. Transconductor The differential pair with source degeneration is one of the most popular transconductors. The requirement that the input pair transconductance gm be much higher than the inverse of the degeneration resistance Rdeg to attain high linearity is usually satisfied by employing large transistors and/or bias currents. However, this may not be desirable in terms of area and power consumption. An alternative is to boost the gm of the input pair by using a compound device as shown in Fig. 3 (a). The implementation of the transconductor stage is shown in Fig. 3(b). The input transistors (M1) serve as voltage followers buffering the input voltage to the degeneration resistor while the constant current sources M3 force any change in the resistor current to be directly reflected in the drain currents of M2. This topology was presented in [5], but in our case active cascodes are used in order to maximize the output impedance and enhance the gm -boosting action, thus increasing the accuracy of the total transconductance Gm =1/2Rdeg of the system. Two linear poly-silicon resistors Rdeg = 1kΩ were used to give more symmetry to the layout implementation of the circuit.
M2
a2
R 2 M3
a1
R
R M3 2 M3
M1' R
M1 R
a1
a0
M3 R
M 0' R
M0 R
a0 I out
Iout 2
Fig. 4.
Current ladder divider
0 The input current Iin is divided into two output currents, 0 0 Iout = ∆Iin and Iout2 = (1 − ∆)Iin . The division factor ∆ is controlled by a digital word A(3) = a2 , a1 , a0 and is given by:
" # n−1 X 1 ∆= n 1+ (2j − aj 2j ) with n=3 2 j=0
(2)
The output current is connected to the virtual ground (VDD /2) input of the next block, the transimpedance amplifier. Iout2 , in turn, is driven to VDD /2 for proper current division. The advantage of using parallel transistors to generate R/2 and one transistor to generate R is that the voltage drop between the input node and the current output nodes is smaller than it would be with 2 transistors in series to generate 2R and one transistor to generate R [7].
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C. Transimpedance Amplifier Fig. 5 shows the topology of the transimpedance amplifier (TIA). It consists of a single-stage differential amplifier and a linear poly-silicon feedback resistor Rf with 100kΩ value and a compensation capacitor of 500f F . If Iin is the current delivered by the current ladder, the output voltage is given by: Vout = −Iin Rf
(3)
Vdd M2
M2 Vout
Ib
The topology employed here was presented in [8] and is depicted in Fig. 6. The circuit operates as a current follower when the control signal ctrl is low and as a current inverter when ctrl is high. As the ctrl signal is in phase with the input signal, this results in a full rectification of the input current. IV. P ERFORMANCE S UMMARY The proposed LIA was designed in a 0.18µm CMOS process with 1.8V supply voltage. The layout of the circuit is shown in Figure 7. The low-pass filter (LPF) is not included in the layout because it will be implemented externally as a second order passive LPF with a cut-off frequency of 5Hz.
Cc Rf
Vin+= Vdd 2
M1
VinIin
M1
2Ib M4
M3
Gnd
Fig. 5.
Transimpedance amplifier
Fig. 7.
Considering the cascade connection of the three blocks presented so far, the total gain of the system as a function of the digital word is given by the following expression: Vout Rf =− Vin Rdeg
! n−1 i X 1h j j (2 − aj 2 ) with n=3 1+ 2n j=0
(4)
A summary of the LIA post-layout main parameters is reported in Table I. Fig. 8(a) shows the transfer function gain for each digital word: the gain ranges from 20.9 to 39.5dB, with a constant bandwidth of 1M Hz, which corresponds to a capacitor Cext = 3pF . The circuit consumes 352µW , from which 27.9% is due to the mixer. Thus, an optimization of the mixer design would fairly reduce power.
That is, it is equivalent to a programmable gain amplifier whose gain depends on the Rf to Rdeg ratio and on the current ladder digital word. Note that both Rf and Rdeg are implemented with the same material, so both will suffer the same variations with process and temperature, thus ensuring good accuracy and robustness. Furthermore, current division is highly linear [6], and so is the whole system.
TABLE I LIA E LECTRIC C HARACTERIZATION
D. Mixer As was shown in fig. 2(b), an additional block is inserted between the voltage-to-current converter and the current divider, namely, a mixer. Its function is to carry out the phase sensitive detection over the signal and thus provide a fully rectified output current with a DC component proportional to the signal of interest and (almost) independent of noise. Vdd Ib
M7
Vc
M1
M5
M9 M9
Vc
ctrl
M8
Vc
M7 M7
M10 Vc
Io1
Iin
ctrl
M10
Io1 Io1'
ctrl ctrl
M4
M3
Ib
M7 M2
Vdd 2
M6
M8 M7 M7
M7
M7
Vc
M9
Vc
ctrl
M9
M9
M9 Gnd
Fig. 6.
Vc
Mixer
M9 M9 M9 M9
Vc
ctrl
M9 M9
Layout of the proposed lock-in amplifier
Parameter
Value
Gain (dB)
20.9 − 39.5
BW (MHz)
1
Input-referred noise ( µVrms )
28.3
CMRR (dB)
78.3
PSRR+ (dB)
57.3
PSRR- (dB)
50.6
Output Offset mV
2.7
Power Consumption (µW )
351.4
Area (µm2 )
253x52
As previously mentioned, in order to limit the noise, the bandwidth of the system can be adjusted by means of Cext . Fig. 8(b) shows the transfer function at maximum gain for different Cext values (3.1pF, 41pF, 415pF and 4.1nF to set a BW of 1M Hz, 100kHz, 10kHz and 1kHz, respectively). Thus, programmability can be used not only to adjust gain according to the input amplitude, but also to adjust bandwidth according to the input frequency. To test the performance of the circuit, three cases were studied. The amplifier was set to its maximum gain. For the first case the signal vs applied to the transconductor inputs was a sinusoidal voltage of 10mV at 1kHz frequency. For the second case, the signal vs was a sinusoidal voltage of 1mV
670
1.6
1.20
40 1.15
20
10
1.2
1.0
0-0-0 0-0-1 0-1-0 0-1-1 1-0-0 1-0-1 1-1-0 1-1-1
0
Vout_dc (V)
Vout (V)
Ganancia (dB)
1.4
1.05 1.00
0.8
0.95 0.6
0.0
100
1k
10k
100k
1M
1.0
2.0
3.0
4.0
0.90 0.0
5.0
100.0
Tiempo (ms)
10M
200.0
300.0
400.0
500.0
Tiempo (ms)
(a)
Frecuencia (Hz)
(a)
1.6
1.20 1.15
Vout (V)
20
Vout_dc (V)
1.4
40
Ganancia (dB)
1.10
1.2
1.0
1.10 1.05 1.00
0.8
0
0.95
4.1nF 414pF 41pF 3.1pF 0
-20 10
100
0.6
0.0
1.0
2.0
3.0
4.0
5.0
0.90 0.0
100.0
Tiempo (ms)
1k
10k
100k
1M
10M
200.0
300.0
400.0
500.0
Tiempo (ms)
(b)
Frecuencia (Hz)
(b)
Fig. 8.
Fig. 9. Rectified TIA output signal and LPF filter dc output for: (a) sinusoidal voltage of 10mV at 1KHz; (b) sinusoidal voltage of 1mV at 1KHz with an interfering sinusoidal signal of 10mV at 10KHz
(a) Gain Programability (b) BW variation with Cext
TABLE III C OMPARISON WITH PREVIOUSLY REPORTED LIA S
at 1kHz frequency. Finally, for the third case the signal vs was a sinusoidal voltage of 1mV at 1kHz frequency with an interfering sinusoidal vn of 10mV at 10kHz frequency. The theorical output Vout dc ideal and the post-layout simulation output Vout dc sim of the amplifier are reported in Table II for each case. TABLE II LIA E LECTRIC C HARACTERIZATION Cases
Vout
dc ideal
(V) Case 1 vs = 10mV @1kHz Case 2 vs = 1mV @1kHz Case 3 vs = 10mV @1kHz vn = 10mV @10kHz
1.218
Vout dc sim (V) 1.204
Relative Error 1.1%
0.932
0.940
0.8%
1.218
1.267
4%
Parameter
Proposed LIA
[2]
[3]
Gain (dB)
20.9 − 39.5
109
10 − 110
BW (kHz)
1000
50
−
Input-referred noise √ (nV / Hz)
5.9@1kHz
17@20kHz
34@77Hz
CMRR (dB)
117
> 60
−
PSRR+ (dB)
57.3
−
−
PSRR- (dB)
50.6
−
−
Output Offset (mV)
2.71
−
−
Consumption (mW )
0.35
25
3
Integrated Area (mm2 )
0.013
6.5
5
R EFERENCES
It can be noticed that the output of the three cases are well resolved by the amplifier with a small margin of error. Fig. 9 shows the rectified TIA output signal and LPF filter dc output for the first and the third case afore proposed to test the circuit. Finally, Table III compares the electric performance of the proposed LIA with other implementations found in the literature. V. C ONCLUSION A novel integrated lock-in amplifier has been presented which achieves very promising results with a reduction in power consumption and area compared to other existing solutions. The proposed architecture is able of recovering a signal of interest from noisy environments with a relative error lower than 4%. Future work contemplates the integration of the lowpass filter in the same chip to have a fully integrated solution.
[1] Lock-in amplifiers, appl. notes, Stanford Res. Sys., data sheets, 1999. [2] A. Gnudi, L Colalongo and G. Baccarani, Integrated Lock-In Amplifier for Sensor Aplications, Proc. IEEE Solid-State Circuits Conf: ESSCIRC, pp. 58-61, 1999. [3] A. DAmico, A. De Marcellis, C. DiCarlo, C. Di Natale, G. Ferri, E. Martinelli, R. Paolesse and V. Stornelli,Low-voltage low-power integrated analog lock-in amplifier for gas sensor applications, Sensors and Actuators, vol. 44, no. 2, pp. 400-406, 2008. [4] Jiawei Xu, Guy Meynants and Patrick Merken, Low-Power Lock-In Amplifier for Complex Impedance Measurement, IEEE Workshop on Advances in sensors and Interfaces: IWASI, pp. 110-114, 2009. [5] T. Kwan and K. Martin, An Adaptative Analog Continuos-Time CMOS Biquadratic Filter, IEEE Journal of Solid-State Circuits, vol. 26, pp.859867,1991. [6] K. Bult and G. Geelen, An inherently linear and compact MOST-only current division technique, IEEE J. Solid-State Circuits, vol. 27, n. 12, pp. 1730-1735, 1992. [7] M. Pastre and M. Kayal, Methodology for the Digital Calibration of Analog Circuits and Systems with Case Studies, Springer, 2006. [8] G. Zatorre, N. Medrano, M. T. Sanz, C. Aldea, B. Calvo and S. Celma, Digitally Programmable Analogue Circuits for Sensor Conditioning Systems, Sensors-Basel, vol. 9, no. 5, pp. 3652-3665, Neural Networks and Sensors, 2009.
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