A 60-W Multicarrier WCDMA Power Amplifier ... - Semantic Scholar
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 4, APRIL 2009
265
A 60-W Multicarrier WCDMA Power Amplifier Using an RF Predistorter Kyung-Hoon Lim, Gunhyun Ahn, Sungchan Jung, Hyun-Chul Park, Student Member, IEEE, Min-Su Kim, Ju-Ho Van, Hanjin Cho, Jong-Hyuk Jeong, Cheon-Seok Park, and Youngoo Yang, Member, IEEE
Abstract—In this brief, we present a 60-W power amplifier that is linearized using an RF predistorter for multicarrier wideband code-division multiple-access (WCDMA) applications. The proposed RF predistorter is fully composed of RF or analog circuits, and it has a moderate memory effect compensation capability using a delayed third-order intermodulation (IM3) component path. It also includes the IM5 generation circuits and a compact IM3 generator that is capable of autocanceling for the fundamental component. The proposed RF predistorter was implemented and applied to a 60-W high-power WCDMA amplifier. For a fourcarrier downlink WCDMA signal, the RF predistorter improved the adjacent channel leakage power ratio at a 5-MHz offset by 6.19 dB at an average output power of 48 dBm. The total efficiency of the system is as high as 13.6% at the same output power level. At an output power level of 60 W, the linearized power amplifier complies with the linearity specification of the WCDMA system. Index Terms—Intermodulation distortion (IMD), memory effect, multicarrier power amplifier, power amplifier, predistorter.
I. I NTRODUCTION
M
OST of the wireless communication systems require highly linear and efficient signal transmission. However, high-power amplifiers are inherently nonlinear and inefficient; thus, they should be linearized using proper linearization techniques [1]–[11]. There have been two main linearization methods: feedforward and predistortion. Feedforward has popularly been adopted, particularly for high-power multicarrier applications, due to its excellent ability to improve linearity. Because it uses a subsidiary error amplifier, an output delay line, and a coupler for error signal cancellation, it has relatively low efficiency and high complexity [1], [2]. There have also been various predistortion techniques that can be classified as classic RF/analog and digital predistortion methods. Recently, digital-based predistortion techniques have been highlighted as an alternative choice for the feedforward
Manuscript received July 30, 2008; revised December 8, 2008. First published March 6, 2009; current version published April 17, 2009. This work was supported by the Ministry of Science and Technology, Korean Government, under the Korea Science and Engineering Foundation Grant R01-2007-00020377-0. This paper was recommended by Associate Editor L. Larson. K.-H. Lim, S. Jung, H.-C. Park, M.-S. Kim, J.-H. Van, H. Cho, J.-H. Jeong, C.-S. Park, and Y. Yang are with the School of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746 Korea (e-mail: [email protected]). G. Ahn is with Korea Electrotechnology Research Institute (KERI), Ansan 426-170, Korea. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2009.2015385
technique. By virtue of fast evolving digital signal processing technologies and signal converting circuits such as analog-todigital and digital-to-analog converters, we can more accurately and adaptively compensate for the nonlinearity of the high-power amplifiers [3]–[6]. However, it is still considerably expensive and power consuming to adopt high-speed and high-resolution digital signal processing and data converting circuits that are suitable for systems in which linear power amplifiers amplify multicarrier wideband code-division multipleaccess (WCDMA) signals. Many RF or analog predistortion methods have been reported. Since they have generally been composed of incomparably simple circuits, most of the previously published RF/analog predistortion techniques have performed well only for wellbehaving nonlinear circuits that are likely to generate thirdorder dominant intermodulation (IM3) terms without having a considerable memory effect [7]–[11]. However, high-power amplifiers generally exhibit considerable higher order IM terms and a memory effect [11], [12]. This is why the RF/analog predistortion techniques are not considered adequate for linearizing high-power amplifiers for multicarrier applications. In this brief, we demonstrate an improved RF predistorter that is able to compensate for the memory effect. A delayed IM3 component is added to the main IM3 path to compensate for the memory effect of the high-power amplifier. The IM3 and IM5 components are generated and independently controlled with compact RF IM generators and analog vector modulation circuits. For experimental verification, the proposed RF predistorter is applied to a high-power multicarrier WCDMA amplifier. II. O PERATION AND C ONFIGURATION OF THE RF P REDISTORTER A. Circuit Configuration Fig. 1 shows a schematic of the proposed RF predistorter. The input signal is split into the fundamental and IM paths. The signal that is split into the IM path is again split into the IM3 and IM5 paths. The three signals from the fundamental, IM3, and IM5 paths are controlled, combined, amplified, and then applied to the power amplifier under test. The IM3 path includes an IM3 generator that has an automatic cancellation capability for the fundamental component and dominantly generates the IM3 component. The generated IM3 component is split into three paths. The signal in the first path is adjusted and combined with the signal generated in the IM5 generator to cancel out the unwanted IM3 component in
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the condition for a perfect cancellation is ΓS,3 = −ΓS,4 . The impedances of ZS,4 and ZS,3 can be written as ZS,4 = Z0
1 + ΓS,4 1 − ΓS,4
(1)
ZS,3 = Z0
1 + ΓS,3 . 1 − ΓS,3
(2)
ZS,3 from (2) can further be simplified using the perfect cancellation condition as ZS,3 = Z0
Fig. 1. Circuit diagram of the proposed RF predistorter.
Fig. 2. Schematic and operational diagram of the compact IM generator.
the IM5 path. The signal in the second path (main IM3 path) is just adjusted using a vector modulator that consists of a variable attenuator and a variable phase shifter. The signal in the third path (delayed IM3 path) has a vector modulator and an additional delay line to take the memory effect into account, which was first proposed for an envelope predistorter [11]. Since we extracted almost pure IM3 and IM5 components, we can independently control their magnitudes and phases using the vector modulators in each path. The delays of each path should exactly be matched except for the delayed IM3 path, which includes a delay that is intentionally added.
1 − ΓS,4 Z2 = 0 . 1 + ΓS,4 ZS,4
(3)
We must select the values of the shunt inductor and resistor that are connected to port 3 so that the condition from (3) is satisfied for the cancellation of the fundamental. In contrast with the fundamental component, the IM component generated from the antiparallel diode at port 3 can directly be reflected to port 2. The basic IM3 generator was designed using the circuit configuration shown in Fig. 2. We also used the same circuit configuration and chose a different input level for the IM5 generator that generates the IM5 component in the presence of a moderate IM3 component. The unwanted IM3 component in the IM5 path was suppressed to below the IM5 level using an additional cancellation path that was already shown in Fig. 1. Fig. 3(a) and (b) shows the measured output power spectral densities (PSDs) for the IM components in the IM3 and IM5 paths, respectively. C. Memory Effect Compensation To verify the memory effect compensation capability, the main and delayed IM3 paths are simplified, as presented in Fig. 4(a). For the narrow-band equal-amplitude two-tone input signal with ω1 and ω2 frequencies, while ω1 < ω2 , IM3 tones with 2ω1 − ω2 and 2ω2 − ω1 frequencies will be generated. The normalized input IM3 signal can be represented in the phasor form with each frequency index as
B. Compact IM Generator
IM3in [2ω1 − ω2 ] = 1∠0
(4)
Fig. 2 shows a schematic of the compact IM generation circuit. It consists of a 90◦ hybrid and an antiparallel Schottky diode pair, and a parallel-connected inductor–resistor pair. If we select port 1 as the input port, the output port should be an isolation port (port 2). The phases of S31 and S41 of the fourport hybrid coupler are 0◦ and −90◦ , respectively. The IM generator can be very compact because it has a cancellation capability for the fundamental component. The input signal is equally split into port 3 and port 4, with a 90◦ phase difference due to the characteristics of the hybrid coupler. Then, the reflected signals from port 3 and port 4 due to nonzero values of ΓS,3 and ΓS,4 are combined at port 2, again with a 90◦ phase difference. To achieve a perfect fundamental cancellation, we need to have the reflected signals from port 3 and port 4 with the same magnitudes and a phase difference of 180◦ . Therefore,
IM3in [2ω2 − ω1 ] = 1∠0.
(5)
Then, the delayed IM3 components using an optimized delay length of τd are given as IM3d [2ω1 − ω2 ] = 1∠ − (2ω1 − ω2 )τd = 1∠ − θ1
(6)
IM3d [2ω2 − ω1 ] = 1∠ − (2ω2 − ω1 )τd = 1∠ − θ2 .
(7)
The amplitudes and phases of the delayed IM3 components can equally be adjusted using a vector modulator as follows: IM3vm [2ω1 − ω2 ] = A∠(−θ1 − φ) = A∠ − θ1
(8)
IM3vm [2ω2 − ω1 ] = A∠(−θ2 − φ) = A∠ − θ2
(9)
where A and φ are attenuation and phase-shift coefficients of the vector modulator, respectively.
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Fig. 5. Experimental configuration, including the high-power main amplifier.
Finally, the delayed and main IM3 components are combined to make output IM3 components whose magnitudes and phases, respectively, are expressed as (10) |IM3out [2ω1 − ω2 ]| = 1 + A2 + 2A cos θ1 (11) |IM3out [2ω2 − ω1 ]| = 1 + A2 + 2A cos θ2
Fig. 3.
(a) Output PSD of the IM3 generator. (b) Output PSD in the IM5 path.
∠IM3out [2ω1 − ω2 ] = tan−1
−A sin θ1 1 + A cos θ1
(12)
∠IM3out [2ω2 − ω1 ] = tan−1
−A sin θ2 1 + A cos θ2
(13)
where θ1 and θ2 are different values and can be controlled as we adjust the values of τd , A, and φ. As shown in (10)–(13), we can control the magnitudes and phases of the lower and upper IM3 tones to have different magnitudes and phases by selecting a length of additional delay line τd , an attenuation A, and a phase shift φ for the vector modulator in the delayed IM3 path. This process is graphically represented in Fig. 4(b). III. E XPERIMENTAL V ERIFICATION
Fig. 4. (a) Simplified operational diagram for the main and delayed IM3 paths. (b) Vector representations of the memory effect compensation process for the lower (2ω1 − ω2 ) and upper (2ω2 − ω1 ) IM3 tones.
For the experimental validation, we implemented a highpower class-AB amplifier for the 2.16-GHz band. Four 190-W peak–envelope–power push–pull laterally diffused metal– oxide–semiconductor field-effect transistors (LDMOSFETs) were parallel combined for the final stage of the main amplifier. It is driven by a three-stage driver amplifier, which consists of a 190-W LDMOSFET, a 45-W LDMOSFET, and a 2-W GaAs metal–semiconductor field-effect transistor, as shown in Fig. 5. The proposed predistorter was designed and implemented in a 17.3 × 11.8 cm2 area, as shown in Fig. 6. Experiments were carried out with and without the additional delayed IM3 path to verify the memory effect compensation capability of the proposed predistorter. An additional delay was experimentally optimized to be 1.2 ns for the additional IM3 path. A 2.16-GHz two-tone signal with a tone spacing of 5 MHz was applied to measure the IM distortion (IMD) performance before and after linearization. The control voltages of the vector modulators in the IM paths were exhaustively optimized to have the best performance for each given condition. Fig. 7(a)
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Fig. 6. Photograph of the implemented RF predistorter.
Fig. 8. Linearization results using a four-carrier downlink WCDMA signal. (a) PSD at an output power level of 48 dBm. (b) ACLR performances at ±5-MHz offsets.
Fig. 7. Linearization results using a two-tone signal with a tone spacing of 5 MHz. (a) PSD at an output power level of 51 dBm. (b) IMD performances.
shows the PSDs at an output power of 51 dBm for the two-tone signal input. The IMD3 performance was improved by about 10 dB using the proposed predistorter with the delayed IM3 path, as compared with that using the same predistorter without the delayed IM3 path. This verifies that the delayed IM3 path is successfully compensating for the memory effect. Fig. 7(b) shows the IMD performance for various output power levels.
Fig. 8(a) shows the PSDs at an output power level of 48 dBm for the four-carrier downlink WCDMA signal whose peak-toaverage power ratio is 9.82 dB at a complementary cumulative distribution function of 0.01%. The initial control voltages of the vector modulators that were obtained from the two-tone test were further optimized for these three conditions: 1) using no predistorter; 2) using a predistorter without the delayed IM3 path; and 3) using a predistorter with the delayed IM3 path. The adjacent channel leakage power ratio (ACLR) level at a −5-MHz offset was improved to −47.53 dBc (a 3.77-dB improvement from −43.76 dBc) using the predistorter without the delayed IM3 path. It was improved even more to −49.95 dBc (a 2.42-dB improvement from −47.76 dBc) after including the delayed IM3 path. At an output power level of 60 W, the linearized amplifier with the delayed IM3 path exhibits an ACLR of −50 dBc, which complies with the WCDMA system specifications. This is about 2 dB more output power than that achieved without the delayed IM3 path at the same ACLR level. Table I presents a summary of the experimental results, including the power-added efficiency (PAE) performances. As shown in the table, the RF predistorter has a negligible effect on the overall efficiency. We achieved a high overall efficiency of 13.6% at an output power level of 48 dBm while obtaining an
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TABLE I PERFORMANCE SUMMARY FOR THE HIGH-POWER AMPLIFIER USING THE PROPOSED RF PREDISTORTER
ACLR of −49.95 dBc using the predistorter with the delayed IM3 path, which is a 3.88% improvement compared with the 9.72% efficiency that was achieved when the output power level was 46 dBm, and the ACLR was −49.9 dBc using a predistorter without the delayed IM3 path. IV. C ONCLUSION In this brief, an advanced RF predistorter, including a moderate compensation capability for the memory effect, has been demonstrated. We used compact IM3 generation circuits with an automatic cancellation capability for the fundamental component. In addition to the IM3 generation, the IM5 was also generated using a compact IM5 generator and an IM3 cancellation process. The generated IM3 and IM5 were independently controlled to cancel the IM components generated from the main amplifier. We proposed an additional IM3 path with an optimized delay line for the main IM3 signal. The magnitudes and phases of both IM3 signals were controlled to achieve the maximum compensation for the memory effect of the main amplifier. The proposed predistorter was implemented and applied to a 60-W high-power multicarrier amplifier for WCDMA applications. We achieved an additional ACLR improvement of 2.42 dB (−47.53 versus −49.95 dBc) at an output power of 48 dBm after applying the delayed IM3 path to the predistorter. This experimentally verifies the memory effect compensation process using the delayed IM3 path, which was also theoretically analyzed. The power amplifier, after being linearized using the proposed predistorter, delivered a 60-W average output power for a four-carrier downlink WCDMA signal while complying with the linearity specification for WCDMA systems.
R EFERENCES [1] J. S. Kenney and A. Leke, “Design considerations for multicarrier CDMA base station power amplifiers,” Microw. J., vol. 42, no. 2, pp. 76–83, Feb. 1999. [2] Y. Yang, Y. Woo, and B. Kim, “Optimization for error-cancelling loop of the feedforward amplifier using a new system-level mathematical model,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 2, pp. 475–482, Feb. 2003. [3] M. A. Nizamuddin, P. J. Balister, W. H. Tranter, and J. H. Reed, “Nonlinear tapped delay line digital predistorter for power amplifiers with memory,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., 2003, pp. 607–611. [4] J. Kim, Y. Y. Woo, J. Moon, and B. Kim, “A new wideband adaptive digital predistortion technique employing feedback linearization,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 2, pp. 385–392, Feb. 2008. [5] N. Ceylan, J. Mueller, and R. Weigel, “Optimization of EDGE terminal power amplifiers using memoryless digital predistortion,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 515–522, Feb. 2005. [6] P. Roblin, S. K. Myoung, D. Chaillot, Y. G. Kim, A. Fathimulla, J. Strahler, and S. Bibyk, “Frequency-selective predistortion linearization of RF power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 1, pp. 65–76, Jan. 2008. [7] T. Nojima and T. Konno, “Cuber predistortion linearizer for relay equipment in 800 MHz band land mobile telephone system,” IEEE Trans. Veh. Technol., vol. VT-34, no. 11, pp. 169–177, Nov. 1985. [8] W. Bosch and G. Gatti, “Measurement and simulation of memory effect in predistortion linearizers,” IEEE Trans. Microw. Theory Tech., vol. 37, no. 12, pp. 1885–1890, Dec. 1989. [9] J. Yi, Y. Yang, M. Park, W. Kang, and B. Kim, “Analog predistortion linearizer for high-power RF amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 12, pp. 2709–2713, Dec. 2000. [10] J. Cha, J. Yi, J. Kim, and B. Kim, “Optimum design of a predistortion RF power amplifier for multicarrier WCDMA applications,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 2, pp. 655–663, Feb. 2004. [11] S. Jung, H. Park, M. Kim, G. Ahn, J. Van, H. Hwangbo, C. Park, S. Park, and Y. Yang, “A new envelope predistorter with envelope delay taps for memory effect compensation,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 1, pp. 52–59, Jan. 2007. [12] J. H. K. Vuolevi, T. Rahkonen, and J. P. A. Manninen, “Measurement technique for characterizing memory effects in RF power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 8, pp. 1383–1389, Aug. 2001.
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A 60-W Multicarrier WCDMA Power Amplifier Using an RF Predistorter Kyung-Hoon Lim, Gunhyun Ahn, Sungchan Jung, Hyun-Chul Park, Student Member, IEEE, Min-Su Kim, Ju-Ho Van, Hanjin Cho, Jong-Hyuk Jeong, Cheon-Seok Park, and Youngoo Yang, Member, IEEE
Abstract—In this brief, we present a 60-W power amplifier that is linearized using an RF predistorter for multicarrier wideband code-division multiple-access (WCDMA) applications. The proposed RF predistorter is fully composed of RF or analog circuits, and it has a moderate memory effect compensation capability using a delayed third-order intermodulation (IM3) component path. It also includes the IM5 generation circuits and a compact IM3 generator that is capable of autocanceling for the fundamental component. The proposed RF predistorter was implemented and applied to a 60-W high-power WCDMA amplifier. For a fourcarrier downlink WCDMA signal, the RF predistorter improved the adjacent channel leakage power ratio at a 5-MHz offset by 6.19 dB at an average output power of 48 dBm. The total efficiency of the system is as high as 13.6% at the same output power level. At an output power level of 60 W, the linearized power amplifier complies with the linearity specification of the WCDMA system. Index Terms—Intermodulation distortion (IMD), memory effect, multicarrier power amplifier, power amplifier, predistorter.
I. I NTRODUCTION
M
OST of the wireless communication systems require highly linear and efficient signal transmission. However, high-power amplifiers are inherently nonlinear and inefficient; thus, they should be linearized using proper linearization techniques [1]–[11]. There have been two main linearization methods: feedforward and predistortion. Feedforward has popularly been adopted, particularly for high-power multicarrier applications, due to its excellent ability to improve linearity. Because it uses a subsidiary error amplifier, an output delay line, and a coupler for error signal cancellation, it has relatively low efficiency and high complexity [1], [2]. There have also been various predistortion techniques that can be classified as classic RF/analog and digital predistortion methods. Recently, digital-based predistortion techniques have been highlighted as an alternative choice for the feedforward
Manuscript received July 30, 2008; revised December 8, 2008. First published March 6, 2009; current version published April 17, 2009. This work was supported by the Ministry of Science and Technology, Korean Government, under the Korea Science and Engineering Foundation Grant R01-2007-00020377-0. This paper was recommended by Associate Editor L. Larson. K.-H. Lim, S. Jung, H.-C. Park, M.-S. Kim, J.-H. Van, H. Cho, J.-H. Jeong, C.-S. Park, and Y. Yang are with the School of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746 Korea (e-mail: [email protected]). G. Ahn is with Korea Electrotechnology Research Institute (KERI), Ansan 426-170, Korea. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2009.2015385
technique. By virtue of fast evolving digital signal processing technologies and signal converting circuits such as analog-todigital and digital-to-analog converters, we can more accurately and adaptively compensate for the nonlinearity of the high-power amplifiers [3]–[6]. However, it is still considerably expensive and power consuming to adopt high-speed and high-resolution digital signal processing and data converting circuits that are suitable for systems in which linear power amplifiers amplify multicarrier wideband code-division multipleaccess (WCDMA) signals. Many RF or analog predistortion methods have been reported. Since they have generally been composed of incomparably simple circuits, most of the previously published RF/analog predistortion techniques have performed well only for wellbehaving nonlinear circuits that are likely to generate thirdorder dominant intermodulation (IM3) terms without having a considerable memory effect [7]–[11]. However, high-power amplifiers generally exhibit considerable higher order IM terms and a memory effect [11], [12]. This is why the RF/analog predistortion techniques are not considered adequate for linearizing high-power amplifiers for multicarrier applications. In this brief, we demonstrate an improved RF predistorter that is able to compensate for the memory effect. A delayed IM3 component is added to the main IM3 path to compensate for the memory effect of the high-power amplifier. The IM3 and IM5 components are generated and independently controlled with compact RF IM generators and analog vector modulation circuits. For experimental verification, the proposed RF predistorter is applied to a high-power multicarrier WCDMA amplifier. II. O PERATION AND C ONFIGURATION OF THE RF P REDISTORTER A. Circuit Configuration Fig. 1 shows a schematic of the proposed RF predistorter. The input signal is split into the fundamental and IM paths. The signal that is split into the IM path is again split into the IM3 and IM5 paths. The three signals from the fundamental, IM3, and IM5 paths are controlled, combined, amplified, and then applied to the power amplifier under test. The IM3 path includes an IM3 generator that has an automatic cancellation capability for the fundamental component and dominantly generates the IM3 component. The generated IM3 component is split into three paths. The signal in the first path is adjusted and combined with the signal generated in the IM5 generator to cancel out the unwanted IM3 component in
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the condition for a perfect cancellation is ΓS,3 = −ΓS,4 . The impedances of ZS,4 and ZS,3 can be written as ZS,4 = Z0
1 + ΓS,4 1 − ΓS,4
(1)
ZS,3 = Z0
1 + ΓS,3 . 1 − ΓS,3
(2)
ZS,3 from (2) can further be simplified using the perfect cancellation condition as ZS,3 = Z0
Fig. 1. Circuit diagram of the proposed RF predistorter.
Fig. 2. Schematic and operational diagram of the compact IM generator.
the IM5 path. The signal in the second path (main IM3 path) is just adjusted using a vector modulator that consists of a variable attenuator and a variable phase shifter. The signal in the third path (delayed IM3 path) has a vector modulator and an additional delay line to take the memory effect into account, which was first proposed for an envelope predistorter [11]. Since we extracted almost pure IM3 and IM5 components, we can independently control their magnitudes and phases using the vector modulators in each path. The delays of each path should exactly be matched except for the delayed IM3 path, which includes a delay that is intentionally added.
1 − ΓS,4 Z2 = 0 . 1 + ΓS,4 ZS,4
(3)
We must select the values of the shunt inductor and resistor that are connected to port 3 so that the condition from (3) is satisfied for the cancellation of the fundamental. In contrast with the fundamental component, the IM component generated from the antiparallel diode at port 3 can directly be reflected to port 2. The basic IM3 generator was designed using the circuit configuration shown in Fig. 2. We also used the same circuit configuration and chose a different input level for the IM5 generator that generates the IM5 component in the presence of a moderate IM3 component. The unwanted IM3 component in the IM5 path was suppressed to below the IM5 level using an additional cancellation path that was already shown in Fig. 1. Fig. 3(a) and (b) shows the measured output power spectral densities (PSDs) for the IM components in the IM3 and IM5 paths, respectively. C. Memory Effect Compensation To verify the memory effect compensation capability, the main and delayed IM3 paths are simplified, as presented in Fig. 4(a). For the narrow-band equal-amplitude two-tone input signal with ω1 and ω2 frequencies, while ω1 < ω2 , IM3 tones with 2ω1 − ω2 and 2ω2 − ω1 frequencies will be generated. The normalized input IM3 signal can be represented in the phasor form with each frequency index as
B. Compact IM Generator
IM3in [2ω1 − ω2 ] = 1∠0
(4)
Fig. 2 shows a schematic of the compact IM generation circuit. It consists of a 90◦ hybrid and an antiparallel Schottky diode pair, and a parallel-connected inductor–resistor pair. If we select port 1 as the input port, the output port should be an isolation port (port 2). The phases of S31 and S41 of the fourport hybrid coupler are 0◦ and −90◦ , respectively. The IM generator can be very compact because it has a cancellation capability for the fundamental component. The input signal is equally split into port 3 and port 4, with a 90◦ phase difference due to the characteristics of the hybrid coupler. Then, the reflected signals from port 3 and port 4 due to nonzero values of ΓS,3 and ΓS,4 are combined at port 2, again with a 90◦ phase difference. To achieve a perfect fundamental cancellation, we need to have the reflected signals from port 3 and port 4 with the same magnitudes and a phase difference of 180◦ . Therefore,
IM3in [2ω2 − ω1 ] = 1∠0.
(5)
Then, the delayed IM3 components using an optimized delay length of τd are given as IM3d [2ω1 − ω2 ] = 1∠ − (2ω1 − ω2 )τd = 1∠ − θ1
(6)
IM3d [2ω2 − ω1 ] = 1∠ − (2ω2 − ω1 )τd = 1∠ − θ2 .
(7)
The amplitudes and phases of the delayed IM3 components can equally be adjusted using a vector modulator as follows: IM3vm [2ω1 − ω2 ] = A∠(−θ1 − φ) = A∠ − θ1
(8)
IM3vm [2ω2 − ω1 ] = A∠(−θ2 − φ) = A∠ − θ2
(9)
where A and φ are attenuation and phase-shift coefficients of the vector modulator, respectively.
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Fig. 5. Experimental configuration, including the high-power main amplifier.
Finally, the delayed and main IM3 components are combined to make output IM3 components whose magnitudes and phases, respectively, are expressed as (10) |IM3out [2ω1 − ω2 ]| = 1 + A2 + 2A cos θ1 (11) |IM3out [2ω2 − ω1 ]| = 1 + A2 + 2A cos θ2
Fig. 3.
(a) Output PSD of the IM3 generator. (b) Output PSD in the IM5 path.
∠IM3out [2ω1 − ω2 ] = tan−1
−A sin θ1 1 + A cos θ1
(12)
∠IM3out [2ω2 − ω1 ] = tan−1
−A sin θ2 1 + A cos θ2
(13)
where θ1 and θ2 are different values and can be controlled as we adjust the values of τd , A, and φ. As shown in (10)–(13), we can control the magnitudes and phases of the lower and upper IM3 tones to have different magnitudes and phases by selecting a length of additional delay line τd , an attenuation A, and a phase shift φ for the vector modulator in the delayed IM3 path. This process is graphically represented in Fig. 4(b). III. E XPERIMENTAL V ERIFICATION
Fig. 4. (a) Simplified operational diagram for the main and delayed IM3 paths. (b) Vector representations of the memory effect compensation process for the lower (2ω1 − ω2 ) and upper (2ω2 − ω1 ) IM3 tones.
For the experimental validation, we implemented a highpower class-AB amplifier for the 2.16-GHz band. Four 190-W peak–envelope–power push–pull laterally diffused metal– oxide–semiconductor field-effect transistors (LDMOSFETs) were parallel combined for the final stage of the main amplifier. It is driven by a three-stage driver amplifier, which consists of a 190-W LDMOSFET, a 45-W LDMOSFET, and a 2-W GaAs metal–semiconductor field-effect transistor, as shown in Fig. 5. The proposed predistorter was designed and implemented in a 17.3 × 11.8 cm2 area, as shown in Fig. 6. Experiments were carried out with and without the additional delayed IM3 path to verify the memory effect compensation capability of the proposed predistorter. An additional delay was experimentally optimized to be 1.2 ns for the additional IM3 path. A 2.16-GHz two-tone signal with a tone spacing of 5 MHz was applied to measure the IM distortion (IMD) performance before and after linearization. The control voltages of the vector modulators in the IM paths were exhaustively optimized to have the best performance for each given condition. Fig. 7(a)
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 4, APRIL 2009
Fig. 6. Photograph of the implemented RF predistorter.
Fig. 8. Linearization results using a four-carrier downlink WCDMA signal. (a) PSD at an output power level of 48 dBm. (b) ACLR performances at ±5-MHz offsets.
Fig. 7. Linearization results using a two-tone signal with a tone spacing of 5 MHz. (a) PSD at an output power level of 51 dBm. (b) IMD performances.
shows the PSDs at an output power of 51 dBm for the two-tone signal input. The IMD3 performance was improved by about 10 dB using the proposed predistorter with the delayed IM3 path, as compared with that using the same predistorter without the delayed IM3 path. This verifies that the delayed IM3 path is successfully compensating for the memory effect. Fig. 7(b) shows the IMD performance for various output power levels.
Fig. 8(a) shows the PSDs at an output power level of 48 dBm for the four-carrier downlink WCDMA signal whose peak-toaverage power ratio is 9.82 dB at a complementary cumulative distribution function of 0.01%. The initial control voltages of the vector modulators that were obtained from the two-tone test were further optimized for these three conditions: 1) using no predistorter; 2) using a predistorter without the delayed IM3 path; and 3) using a predistorter with the delayed IM3 path. The adjacent channel leakage power ratio (ACLR) level at a −5-MHz offset was improved to −47.53 dBc (a 3.77-dB improvement from −43.76 dBc) using the predistorter without the delayed IM3 path. It was improved even more to −49.95 dBc (a 2.42-dB improvement from −47.76 dBc) after including the delayed IM3 path. At an output power level of 60 W, the linearized amplifier with the delayed IM3 path exhibits an ACLR of −50 dBc, which complies with the WCDMA system specifications. This is about 2 dB more output power than that achieved without the delayed IM3 path at the same ACLR level. Table I presents a summary of the experimental results, including the power-added efficiency (PAE) performances. As shown in the table, the RF predistorter has a negligible effect on the overall efficiency. We achieved a high overall efficiency of 13.6% at an output power level of 48 dBm while obtaining an
LIM et al.: 60-W MULTICARRIER WCDMA POWER AMPLIFIER USING AN RF PREDISTORTER
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TABLE I PERFORMANCE SUMMARY FOR THE HIGH-POWER AMPLIFIER USING THE PROPOSED RF PREDISTORTER
ACLR of −49.95 dBc using the predistorter with the delayed IM3 path, which is a 3.88% improvement compared with the 9.72% efficiency that was achieved when the output power level was 46 dBm, and the ACLR was −49.9 dBc using a predistorter without the delayed IM3 path. IV. C ONCLUSION In this brief, an advanced RF predistorter, including a moderate compensation capability for the memory effect, has been demonstrated. We used compact IM3 generation circuits with an automatic cancellation capability for the fundamental component. In addition to the IM3 generation, the IM5 was also generated using a compact IM5 generator and an IM3 cancellation process. The generated IM3 and IM5 were independently controlled to cancel the IM components generated from the main amplifier. We proposed an additional IM3 path with an optimized delay line for the main IM3 signal. The magnitudes and phases of both IM3 signals were controlled to achieve the maximum compensation for the memory effect of the main amplifier. The proposed predistorter was implemented and applied to a 60-W high-power multicarrier amplifier for WCDMA applications. We achieved an additional ACLR improvement of 2.42 dB (−47.53 versus −49.95 dBc) at an output power of 48 dBm after applying the delayed IM3 path to the predistorter. This experimentally verifies the memory effect compensation process using the delayed IM3 path, which was also theoretically analyzed. The power amplifier, after being linearized using the proposed predistorter, delivered a 60-W average output power for a four-carrier downlink WCDMA signal while complying with the linearity specification for WCDMA systems.
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