A Fully Integrated Dual-Channel Log-Domain ... - Semantic Scholar
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS ,VOL. 51, NO. 10, OCTOBER 2004
A Fully Integrated Dual-Channel Log-Domain Programmable Preamplifier and Filter for an Implantable Cardiac Pacemaker Andrea Gerosa, Member, IEEE, Andrea Maniero, and Andrea Neviani
Abstract—A programmable-gain preamplifier and filter for detection of spontaneous heart activity in an implantable cardiac pacemaker is presented. The system is fully integrated in a standard 0.35- m CMOS technology, including all auxiliary circuits. Two channels are available in order to process both atrial and ventricular signals. CMOS translinear circuits, with particular emphasis on log-domain techniques, have been exploited in order to contain current consumption and to allow correct operation with a reduced supply voltage, due to battery discharging. Indeed, the realized system can operate down to 1.8 V of supply voltage and dissipates at most 1.8 A, granting at least 47 dB of dynamic range (DR) for the atrial chain, which is compatible with advanced digital sensing. Current consumption can be further reduced at the expense of DR if a simpler sensing like peak detection is adopted. All system performance have been verified by measurements results and are compatible with the requirements of cardiac pacemakers. This work, therefore, demonstrates how a proper design approach, exploiting low-power and low-voltage techniques, allows one to optimize performance for the cardiac pacemaker. Index Terms—Biomedical, companding, log domain, low power (LP), low voltage (LV), pacemaker, translinear (TL) circuits.
I. INTRODUCTION
T
HIS PAPER presents a fully integrated programmable preamplifier and filter for the sensing stage of an implantable cardiac pacemaker. The natural heart activity is in fact acquired in responsive pacemakers, in order to set the proper stimulation strategy. The heart activity detection can be performed in different ways [1], from simple peak detection in the analog domain [2] to more complex algorithms based on a digitized version of the signal [3]. In any case, the received signal needs to be amplified and bandpass filtered, which is the functionality performed by the circuit presented in this paper. The circuit was designed with the main goal of containing as much as possible its power consumption and of fully integrating the whole system on a standard CMOS technology, aiming at a cardiac pacemaker fully integrated on a single chip, with almost no external components [4]–[6]. These two factors are of fundamental importance to improve the quality of life of people treated with cardiac pacemakers, because they imply increasing
Manuscript received October 16, 2003; revised March 9, 2004. This work was supported by Medico S.p.A., Rubano, Italy. This paper was recommended by Associate Editor J. Silva-Martinez. The authors are with Department of Information Engineering, University of Padova, 35131 Padova, Italy (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSI.2004.835027
the implanted device duration and reducing its size. Circuit designers have developed low-power (LP) design techniques that can actually be profitably exploited to achieve the desired result. In particular, the proposed system has been realized by means of current-mode translinear (TL) circuits [7], with particular emphasis on log-domain circuits [8], [9]. Log-domain circuits are naturally realized using bipolar transistors [10]–[14], because they are based on the exponential current versus voltage characteristic; however, their CMOS implementation, based on transistor biased in weak inversion, soon became interesting, especially for micropower applications [15], [16]. In fact, circuit solutions for biomedical devices, exploiting CMOS TL circuits can be singled out in literature [17]–[19]. The log-domain approach looks beneficial also for the considered pacemaker application from different points of view. First of all, in these circuits, voltage swings are really limited thanks to the logarithmic compression performed by currentdriven transistors. This characteristic allows to overcome typ- filters, which may require a ical problems of standard transconductor with rail-to-rail input swing and a large range of linearity. Furthermore, the reduced voltage swing makes current-mode TL circuits suited for low-voltage (LV) operation. Although our application does not require extremely LV circuits, correct operation while the supply battery is discharging is required. In fact, the proposed circuits operate with a supply voltage from 2.8 down to 1.8 V, which is 200 mV below the typical end-of-life (EOL) voltage of the battery. More importantly, TL circuits realized with CMOS transistors operating in weak inversion regime have demonstrated significant potential in terms of power efficiency, which is, as mentioned previously, a very important task for this design. Furthermore, the drawback of limited maximum bandwidth of CMOS realizations of TL circuits, with respect to bipolar realization [20], [21], is not a concern at all in this case, due to the characteristic frequencies of cardiac signals. In summary, this paper presents a design example in which some LP and LV design techniques for CMOS circuits have been profitably exploited in order to optimize performance in a specific application, namely the cardiac pacemaker. As a result of the used design procedure, we achieved a total current consumption of 1.8 A, which is fully compatible with available power budget in the implantable device. The system is fully integrated in a 0.35- m CMOS technology, which allows to benefit from the high level of integration of a submicrometer CMOS technology, while does not excessively limit the stimulation pulse
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Fig. 1. Block diagram of one of the two sensing channels for the cardiac pacemaker.
amplitude due to voltage ratings, as explained in [2]. In this case, stimulation voltages must be within 5.5 V (unless the extra cost of high-voltage masks is accepted), but anyway comply with the requirements of a significant segment of the pacemaker market. The proposed circuit operates with a supply voltage from 2.8 V down to 1.8 V, covering the whole voltage range of typical battery that discharges from its initial voltage down to EOL voltage. The system integrates two sensing channels, for detecting both atrial and ventricular activities. Both channels have programmable gain and beyond amplification also perform bandpass filtering, centered at 100 and 70 Hz for atrial and ventricular data paths, respectively. Finally, the system accuracy can be traded off for current consumption by means of a control bit, in order to match the requirements both of simple analog detection and more complex digital sensing. Auxiliary circuits, such as bias currents and clock phases generators are included on-chip and contribute to make the filters frequency response highly insensitive to temperature and process parameters spread, as it is explained in detail in Section III-E. The system-level description of the realized circuit is reported in Section II, while the corresponding circuit-level details are reported in Section III, where design criteria for each basic block are discussed. All performances and figures of merit have been verified by means of measurements, which are described in Section IV. Finally, conclusions are drawn in Section V. II. PACEMAKER INPUT STAGE Independently of the kind of processing chosen in order to extract the information of interest from the acquired signal, a cardiac pacemaker sensing stage definitely needs to amplify the signal: indeed, the peak amplitude for the atrial signal can be as low as 100 V, while, for the ventricular signal, it can be as low as 400 V. Furthermore, in some cases, the signal can actually exhibit a 4-mV or 8-mV peak amplitude for the atrial and ventricular paths respectively. It is therefore apparent that making the gain programmable can significantly relax dynamic range (DR) performance required to the other blocks in the data paths. Beyond the required functionality of a programmable-gain preamplifier, the proposed system also introduces a bandpass filtering in order to suppress noise and signal components out of the band of interest. In our case, the atrial filter is centered at 100 Hz, while the ventricular one is centered at 70 Hz, which is a common choice for pacemker applications [1]. The block diagram of one sensing channel is reported in Fig. 1. Both the atrial and ventricular channels can be represented by the diagram of Fig. 1 because they only differ for the gain range and center frequency. The signal coming from
Fig. 2. Circuit schematic of the input transconductor. The input stage of the linear amplifier loads the two output nodes with a circuit like the one drawn in dashed line.
the heart is in the voltage domain, while TL circuits operate in the current domain. Therefore, the first block in the diagram of Fig. 1 is a transconductor that realizes the voltage-to-current ) conversion. As will be explained in Section III-A, this ( block is actually the most critical from the noise point of view and hence it will result the most current consuming block. The current signal coming from the transconductor passes through a current-domain programmable amplifier. Finally, the bandpass filtering is performed by a log-domain biquad. As shown in Fig. 1, this filter requires proper signal compression and conditioning at the input (performed by the splitter) and expansion at the output (performed by the expander). The details of circuit design for the blocks in Fig. 1 are reported in Section III, while the corresponding measured results will be discussed in Section IV. III. CIRCUIT REALIZATION The system described in Section II has been fully integrated in a double-poly triple-metal 0.35- m CMOS technology. Most of the MOS transistors are operated in the weak inversion regime, in order to achieve the exponential characteristic, as required by the log-domain approach, and in order to exploit the best efficiency in terms of transconductance over bias current. Conversely, current mirrors are operated in strong inversion, in order to minimize the effect of device mismatch. The basic building blocks of Fig. 1 are described in the following subsections. The atrial and ventricular channels use one replica each of the circuit block described below. In fact, the two channels are identical from the point of view of circuit topologies, the only difference being in terms of some bias current and device size. These differences will be highlighted in the description below as well. A. Input Transconductor In order to convert the single-ended input voltage in a differential current signal, the transconductor of Fig. 2 is used. Basically, the conversion is performed by the p-MOS differential pair (p-MOS devices have been chosen because they noise with respect to n-MOS ones), hence, introduce less simply relates to the input the output differential current according to voltage (1)
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where is the transconductance of p-MOS M1 and M2. A folded architecture for the circuit of Fig. 2 has been preferred with respect to a simpler differential pair with an active load, in order to optimize the circuit bias condition. In order to understand this issue, it is worth observing that, according to the diagram of Fig. 1, the transconductor drives the current amplifier, whose input stage acts as a virtual ground. Such an input stage is drawn in a dashed line for the positive data path in Fig. 2. The transconductor output node is, in fact, connected to a node , where is the gate-to-source that is biased at voltage of the p-MOS M12, which is biased with a constant current of 25 nA. Since M12 is in weak inversion regime, its gate . Forcing at such results just few hundreds of millivolt below a voltage, the drain of M1 and M2 would severely limit the input common-mode range of the transconductor, while in the cardiac pacemaker, a large range is required in order to improve high frequency disturbances suppression. Therefore, the folded-cascode configuration is exploited as shown in Fig. 2 in order to bias the drain of M1 and M2 at the lowest possible value that keeps M3 and M4 saturated, independently from the bias voltage of the output nodes. Furthermore, the cascode configuration improves the mirroring accuracy of n-MOS (M3 and M4) and p-MOS (M9 and M10), thus reducing the transconductor offset. It is worth stressing that a self-cascode configuration is used, operating the mirroring transistors in strong inversion and the cascode ones in weak inversion, as explained in [22]. This solution requires a really limited voltage headroom for the cascode, hence this circuit solution is compatible with output bias point close to . The key issue in the design of the transconductor is circuit noise, because the input-referred noise of this block sums directly to the input signal before any amplification. As demonstrated in the Appendix , the spectral density of the input-reand flicker noise can be expressed ferred thermal noise as in (2) and (3) (2) (3) is the Boltzman constant, is the absolute temperwhere is the oxide capacitance, and are techature, and are, respectively, nology-dependent constants, and the transconductance and the channel length of transistor Mi in Fig. 2. Remembering that the differential pair is operated in weak inversion and hence the transconductance linearly depends on flowing in the transistor, while for M3 and the bias current M9 the square-root dependence typical of strong inversion applies, it is apparent from (2) that in order to reduce the circuit noise it is necessary to increase the bias current . Similar considerations apply to flicker noise, according to (3). These considerations highlight a critical design tradeoff, because power consumption of this system has to be contained as much as possible. The proposed system is intended for a digital sensing chain, where the acquired signal is digitized with an 8-bit accuracy.
TABLE I TRANSISTOR W=L (IN MICROMETERS) FOR CIRCUIT OF FIG. 2
The maximum input signal expected when the gain is programmed to its highest value is 280 V . Therefore, an upper limit for the input-referred noise is 280 V
1.1 V
(4)
Exploiting (2) and (3), a good design tradeoff between power and noise resulted in a differential pair size of 400 m/12 m of 200 nA for the atrial chain. The channel and a bias current ( 200 m, length of M3 and M9 is much larger than 32 m), in order to force the devices in strong inversion, as mentioned previously (size of all devices are reported in Table I). This choice is also beneficial from the noise perspecresults in being larger tive. Indeed, the transconductance and ; hence, the last two terms in (2) are minithan mized. Furthermore, having long channels also minimizes the terms in (3). Noise performance has been verified by accurate simulations and the measurement results will be discussed in Section IV. The proposed preamplifier is also compatible with a simpler analog detection circuitry, where the required accuracy is lower. In this case, in order to save power, the bias current in the atrial transconductor can be reduced to 50 nA. For this reason, the bias current to the transconductor is delivered by a programmable current mirror, which replicates a 25-nA reference current with a multiplying factor that can be set to 4 or 16. In the case of the ventricular chain, where the minimum input signal is twice that with respect to the atrial case, the bias current is constantly set to 50 nA and the transistors size is identical to the atrial case. The effect of device mismatch is not as critical as noise, because the resulting offset is a dc signal and hence is suppressed by the bandpass filter following in the data path. However, the offset must not be too large in order to prevent overloading for the current amplifier input stage. Anyway, this is not the case for the offset resulting from transistors with the aforementioned sizes. Finally, the conversion gain is equal to 625 nS and 2.5 S in the case of the bias current equal to 50 and 200 nA, respectively. Such a gain difference is compensated in the last stage of the preamplifier, as will be explained in Section III-D. B. Seevinck Integrator The other blocks composing the preamplifier are based on the log-domain integrator proposed by Seevinck in [23]. Such a circuit has been chosen because it represents a good compromise between circuit complexity and LV operation: this integrator indeed is slightly more complex than the integrator in [16], but requires less voltage headroom. Recently, a modified version of this integrator, suited for a LV operation, has been proposed
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Fig. 3. Circuit schematic of the log-domain integrator introduced by Seevinck. Fig. 5. Circuit schematic of the biquadratic filter. The transconductors are replaced by log-domain integrators.
Fig. 4. Circuit schematic of the linear current-mode programmable amplifier.
[24], but the original version can anyway fit into the limits imposed by our EOL supply battery. The fully differential version of the integrator is reported in Fig. 3. It can be demonstrated [6], [23] that this circuit actually performs a current-domain integration, according to the expression (5) where is the differential input signal, is the is the thermal potential. technology slope factor, and C. Programmable Amplifier Assuming that in the circuit of Fig. 3, the two integrating capacitors C are replaced by two current sources , then the circuit of Fig. 4 is obtained if we momentarily ignore the transistors within the shaded area. In this case, the circuit transfer function becomes [6] (6) Equation (6) clearly represents a current-mode linear amplifier. This circuit has been used both in the atrial and ventricular by means of programmable curchain, delivering the current rent mirrors that replicate a reference current, equal to , multiplied by four possible values: 1, 1/4, 1/7, and 1/10. Therefore, this block clearly introduces gain programmability for the whole data path. However, varying the reference current implies modifying the quiescent currents in the circuit, too. As a consequence, the output current of the amplifier exhibits a nonzero commonmode component that depends on the value programmed for , which obviously complicates interfacing with the following
blocks in the data path. This issue is actually solved by the transistors in the shaded area in Fig. 4 that null the output commonmode component independently on the programmed gain. The drain currents of M10 and M9 are in fact replicated by M14 and M13, respectively, and then summed together in the drain of M15 and M16. Half of such a current is subtracted from the drain current of M10 and M9 by M12 and M11, respectively. The net effect is that only the differential component of the two currents in M10 and M9 is delivered to the log-domain filter that follows the amplifier. The value of must be larger than the maximum value expected for the input signal, in order to grant that a nonzero current flows in M4 and M3. However, is not required to be much larger than the input current, in order to linearize input transistors. Indeed, the circuit of Fig. 4 is a TL circuit, therefore, it exploits the nonlinear behavior of the MOS devices. In summary, the maximum input signal is 8 mV, which is converted to a 20-nA current by the transconductor. Therefore, is set to 25 nA in order to account for a safety margin for the current signal swing. Transistors are then sized wide enough in order to grant that their current density is sufficiently low to keep the devices in weak inversion. Device mismatch can also be a critical issue for this block. Indeed, as a result of transistor mismatch, a differential offset current can arise, which is eventually amplified by a factor of 10 when the gain is programmed to its maximum value. Although any dc component should be suppressed by the bandpass filter following in the data path, if the offset current is too large, it can actually force the transistors in the filter significantly out of weak inversion, degrading the system response. For this reason, devices have been made sufficiently large in order to reduce such an effect. Namely, transistors in Fig. 4 are 80 m/7 m, with the exception of M11, M12, M15, and M16, which are 2 m/200 m, to be forced in strong inversion and hence to enhance the current mirrors accuracy. D. Filter Signal and noise components out of the band of interest are suppressed by means of a second-order bandpass biquadratic log-domain filter. It is well established [10]–[13] that the filter - filter block diagram, as can be represented as an usual reported in Fig. 5, assuming that each transconductor is replaced
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TABLE II MAIN PARAMETERS FOR BIQUADRATIC FILTERS
by a replica of the log-domain integrator of Fig. 3. The filter transfer function can be expressed as
Fig. 6.
Circuit schematic of the splitter.
Fig. 7.
Circuit schematic of the expander.
(7) where is the bias current of the integrator. Observing the transfer function (7), the relationship between the filter center frequency and quality factor can be expressed in terms of the circuit parameters as (8) The required center frequency is 100 and 70 Hz for the atrial and ventricular channel, respectively, while the quality factor is 2 for both channels. Observing from (8) that the factor depends on capacitors value only, it is convenient from a layout point of view to set identical capacitors value for the atrial and ventricular channels. The lowest possible value for should be chosen in order to reduce power consumption, but a lower limit is set by feasibility and noise issues. Furthermore, in order to maintain the desired center frequency, if the bias current is reduced, then, the capacitor value must be reduced by the same factor, according to (8). This is of course beneficial, but once again implies circuit noise increase and could make the effect of MOS parasitic capacitances significant. A good design com37.5 pF and 9 pF and promise resulted in setting 400 pA and 280 pA for the atrial and a bias current ventricular chain, respectively, as summarized in Table II. The generation of these low currents will be covered in Section III-E. It is worth observing that the bias current in the filter is significantly lower than the one in the input transconductor, therefore a further reduction of the bias current in the filters would not significantly reduce the total power dissipation of the system. Transistor size is again chosen in order to keep the maximum current density safely below the transition current between weak and strong inversion. With this in mind, it is worth considering that although the bias current in the integrators is in the order of a few hundreds of picoamperes, the current signal coming from the linear amplifier can be as high as 20 nA. Therefore, such a current range must be considered to size the transistors. In summary, the size for the transistors in all the four replicas of the Seevink integrator (two for the atrial chain and two for the ventricular one) ranges from 25 m/5 m to 75 m/5 m. A log-domain filter requires a proper compression of the input signal. Furthermore, the proposed filter operates in CLass AB [10] in order to extend the output current range and to limit current consumption with low signals. Therefore, the input signal
must also be properly conditioned. These two tasks are performed by the splitter circuit reported in Fig. 6 [26]. The TL principle can be applied to two loops in this circuit, namely M1–M3–M5–M6 and M2–M4–M5–M6. As a result, the drain and obey (9) currents of M1 and M2
(9) Hence, and represent, respectively, the positive and negative components of the input signal to the filter, while the geometric mean of these two components is kept constant. This approach has indeed demonstrated to be the most effective for log-domain filters [14]. Finally, the input signal compression is compensated by the expander circuit of Fig. 7. The two compressed output voltage and are applied to the gates of signals of the filter M3–M4 and M1–M2, respectively; therefore, the drain current of these p-MOS transistors represents the uncompressed filtered signal. The sum of these two currents flows in M6 and M7, and half of such a sum is subtracted from both the drain currents of M1 and M4, using M5 and M8, respectively. Therefore, a differential output current with a zero common-mode component is finally delivered to the output. In the case of the atrial chain, the size of p-MOS transistors is programmable in order to compensate for the different transconductor gain in the case of digital or analog sensing, as discussed previously in Section III-A. E. Bias Current Generation As explained in Section III-D, the filter requires the generation of two currents in the order of few hundreds of picoamperes. These currents are generated using the switched-capacitor (SC) current generator reported in Fig. 8 [25]. The generated current is equal to (10)
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Fig. 8.
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is basically identical in the eight cases, proving that the bias curvariations. The gain variation that can rent compensates the be appreciated in Fig. 10(b) is mainly due to variation in the transconductance of the first stage in the data path. This impairment is acceptable due to gain programmability in the whole chain. Recently in [27], an alternative technique for the generation of low currents has been discussed: that current generator is however well suited for the generation of a reference current that is independent from process parameters that can be hardly controlled. In the circuit proposed in this paper however, we need a reference current that depends on a capacitor, as explained previously. This makes the used SC current generator definitely preferable with respect to the technique discussed in [27]. Finally, the need of a clock signal for the SC current generator does not significantly complicate the circuit, because a reference clock is likely to be present in the whole pacemaker circuit (e.g., sampling clocks in the converter, phase clocks in the charge pump that generates the stimulation voltage [4] and reference clock for the digital processing core).
Circuit schematic of SC low-current generator.
F. Circuit Layout
Fig. 9. Circuit schematic of the reference voltage generation.
where is the duration of clock signal at high level and is a reference voltage. In particular, such a voltage in obtained by the circuit reported in Fig. 9, which, assuming that the two transistors are in weak inversion regime, generates a voltage equal to (11) It is apparent from (11) that voltage is highly insensitive to process parameters variations, assuming that the transistors in Fig. 9 are well matched, while it is proportional to absolute temperature. It is interesting to exploit this information in order to inspect the dependence of filter center frequency on parameters and temperature variation. Combining (8) and (10), it can be observed that the filter center frequency is proportional to (12) The first ratio on the right-hand side of (12) is obviously highly insensitive to capacitor non idealities, provided that the capacitors are properly laid out, and hence, matched. The second term is the ratio of two quantities both proportional to the thermal potential; therefore, temperature dependence cancels out. Finally, we can assume that the reference clock is generated with high accuracy using a crystal oscillator. Therefore, the filter transfer function results highly insensitive to process parameter and temperature spread. This statement is supported by the results of corner simulations, performed varying both process parameters and temperature. Fig. 10(a) reports the value of the generated reference current for eight different corners: the current variation is apparent. Fig. 10(b) reports the corresponding frequency response of the filter: it can be observed that the poles position
The microphotograph of the circuit, realized in a 0.35- m CMOS technology is reported in Fig. 11. The two channels can be singled out in the upper and lower part of the photo, while in the right-side part the capacitor arrays for the two bandpass filters can be recognized. As mentioned in Section III-D, the two filters differ in the bias current and not in capacitor values, hence the two arrays are identical. Of course, for capacitor arrays and critical transistors, typical common-centroid layout techniques have been used. The total area of the two channels is 1.3 mm . IV. EXPERIMENTAL RESULTS The system performance has been evaluated measuring different prototypes of the realized circuit at supply voltages of 2.8 and 1.8 V. The circuit is stimulated by a signal generator ac coupled to the prototype mounted on a printed circuit board. The output current signals are converted to the voltage domain using two precise 1-M resistors. The obtained voltage signals are then amplified by means of an instrumentation amplifier, which also converts the fully differential signals in a single-ended one. Finally, such a signal is delivered to an oscilloscope or a spectrum analyzer. Thefrequencyresponseofthetwochannelsmeasuredata1.8-V supply voltage is reported in Fig. 12. The measured center frequency is 105 and 72 Hz for the atrial and ventricular channels, respectively, while the factor is equal to 1.98 and 2. Another important parameter for the sensing chain is the gain at center frequency .Thesensingchainhasbeingdesignedinordertodeliver an output differential current of 20 nA when the input signal is maximum. In order to express the center band gain with a non-dimensionalquantityratherthaninamperespervolt,weassumethat a 20-nA output current corresponds to a voltage signal with amplitude 1 V . Given this clarification, the measured gain values can be inspected in Table III and in Table IV for the atrial and ventricular chains, respectively. As underlined in the two tables, the realized sensing chains allow to program 4 different values for the
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Fig. 10. Corner simulation results. (a) Generated reference current for eight different corners. (b) Corresponding frequency response of the filter.
Fig. 12. Measured frequency response of the two channels at supply voltage of 1.8 V. TABLE III MEASURED CENTERBAND GAIN FOR ATRIAL CHAIN
TABLE IV MEASURED CENTERBAND GAIN FOR VENTRICULAR CHAIN
Fig. 11. Chip microphotograph.
center band gain, using two control bits. Finally, the two tables report the theoretical gain values. The total harmonic distortion (THD) measured in the worst case is 32 dB: such a distortion level is acceptable for the car-
diac signal acquisition, because the heart signal degradation is anyway not so significant to impair the estimate of the spontaneous heart activity. In the light of this characteristic of the pacemaker application, the log-domain filter design has not been optimized from the linearity perspective. Another important parameter is the noise generated by the realized circuit. The most critical configuration corresponds to the gain programmed to the maximum value, because the transconductor noise is amplified by the current-domain programmable
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TABLE VI MAIN CHARACTERISTICS OF REALIZED PROTOTYPE
Fig. 13.
Measured worst case noise spectrum for the atrial chain.
TABLE V MEASURED PERFORMANCE FOR TWO-CHANNEL SENSING STAGE
amplifier. The output noise spectrum measured in this configuration and for a supply voltage of 1.8 V is shown in Fig. 13: the frequency shaping due to the bandpass filter is apparent, hence this measurement confirms that the main noise contributor is the input transconductor, as claimed in Section III-A. The noise amplitude measured at 2.8- and 1.8-V supply voltage are reported in Table V, along with the other parameters of the frequency response discussed above. In the atrial chain, which must receive the lowest signal, a worst case measured noise amplitude equals 42 pA , which corresponds to about 47 dB of DR. The maximum measured current consumption of the whole system is 1.8 A (it is worth reminding that in battery operated systems the current consumption is much more meaningful than power consumption). This consumption has been measured with a maximum amplitude input signal to both the channels, in order to force the Class AB stages to deliver their maximum currents. The consumption is due to the atrial chain for 60% and to the ventricular one for 33%, while the remaining consumption is due to auxiliary circuits (e.g., bias current and clock phases generation) that are all integrated on-chip. The atrial chain exhibits a larger consumption because during the measurement it was programmed to operate in high accuracy-mode, compatible with digital sensing (refer to Section III-A). If the atrial chain is in low accuracy mode, then the total current consumption is reduced to 1.3 A. The achieved results in terms of current consumption, along with the consideration that the system operates with supply voltage within 2.8 and 1.8 V, prove that the designed sensing stage is fully compatible with the requirements imposed to
implantable cardiac pacemaker by the battery technology. Moreover, the measured performance, which is summarized in Table VI, is in accordance with initial specification, therefore the realized circuit is a realistic fully integrated sensing stage for cardiac pacemaker, giving a significant contribution to full integration on a single chip of this kind of biomedical implantable devices. V. CONCLUSION A system suited for amplification and filtering of natural heart activity in implantable pacemakers has been fully integrated in standard 0.35- m CMOS technology. Two channels are available for processing both atrial and ventricular signals. CMOS TL circuits and log-domain filtering have been exploited in order to contain current consumption and to allow the system to operate with an EOL battery. As a result of such an approach, the measured current consumption is at most 1.8 A, with a minimum power supply of 1.8 V and achieving a DR for the atrial channel of at least 47 dB, which is compatible with an advanced digital sensing. According to measurement results, both the channels exhibit the expected programmable gain and implement a biquadratic filter with a quality factor of about 2 and a center frequency at 105 and 72 Hz for atrial and ventricular channels respectively, which are the expected characteristic for the realized processing block. Furthermore 1.8 V is about 200 mV below the EOL battery voltage, while the measured consumption is definitely acceptable for the power budget typically available in pacemakers, hence the realized circuit can realistically be part of a fully integrated pacemaker, with advanced pacing strategy. This work therefore demonstrates how a proper design approach, exploiting low-power and LV techniques, allows one to optimize circuit performance for the cardiac pacemaker application. APPENDIX NOISE IN INPUT TRANSCONDUCTOR The aim of this appendix is to demonstrate (2) and (3) about the noise in the transconductor. The thermal noise of MOS transistors can be expressed as noise current in the channel, whose spectral density is (13) where equals 2/3 for saturated transistors operating in strong inversion, while it becomes 1/2 for saturated transistors in weak inversion regime. Recalling from Section III-A that the input pair in the transconductor of Fig. 2 operates in weak inversion, while the mirroring transistors are in strong inversion regime,
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the total output current due to thermal noise exhibits the spectral density (14) (14) where term 2 accounts for the fact that the circuit is differential. Such a noise can be input-referred dividing the spectral density by the squared transconductance of the input pair, obtaining (15) that is identical to (2) The spectral density of the channel current due to flicker noise can be expressed both for transistors in strong and weak inversion as (16) The spectral density of the total flicker noise current can be evaluated with a similar approach with respect to thermal noise, obtaining the following expression (17) Finally, the noise can be input referred using the input pair transconductance, obtaining (18) that is identical to (3). ACKNOWLEDGMENT The authors would like to thank Prof. E. Zanoni for supporting this research activity. REFERENCES [1] J. G. Webster, Design of Cardiac Pacemakers. Piscataway, NJ: IEEE Press, 1995. [2] L. Lentola, A. Mozzi, A. Neviani, and A. Baschirotto, “A 1-A front end for pacemaker atrial sensing channels with early sensing capability,” IEEE Trans. Circuits Syst. II, vol. 50, pp. 397–403, Aug. 2003. [3] J. N. Rodrigues, V. Owall, and L. Sornmo, “QRS detection for pacemakers in a noisy environment using a time lagged artificial neural network,” in Proc. Int. Symp. Circuits Systems (ISCAS’01), vol. 3, Sydney, Australia, 2001, pp. 596–599. [4] A. Novo, A. Gerosa, and A. Neviani, “A submicrometer CMOS programmable charge pump for implantable pacemaker,” Anal. Integr. Circuits Signal Processing, vol. 27, no. 3, pp. 211–217, 2001. [5] A. Gerosa and A. Neviani, “A very low-power 8-bit sigma-delta converter in a 0.8 m CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V,” in Proc. Int. Symp. Circuits Systems (ISCAS’03), vol. 5, Bangkok, Thailand, May 2003, pp. 49–52. [6] A. Gerosa, A. Novo, A. Mengalli, and A. Neviani, “A micro-power, low-noise, log-domain amplifier for the sensing chain of a cardiac pacemaker,” in Proc. Int. Symp. Circuits Systems (ISCAS’01), vol. 1, Sydney, Australia, May 2001, pp. 296–299. [7] B. Gilbert, “Translinear circuits: A Proposed classification,” Electron. Lett., vol. 11, no. 1, pp. 14–16, 1975. [8] D. R. Frey, “Log-domain filtering: An approach to current-mode filtering,” Proc. Inst. Elect. Eng. , pt. G, vol. 140, pp. 406–416, Dec. 1993. , “Log-domain filtering for RF applications,” IEEE J. Solid-State [9] Circuits, vol. 31, pp. 1468–1475, Oct. 1996.
[10] M. N. El-Gamal, R. A. Baki, and A. Bar-Dor, “30–100-MHz NPN-only variable-gain class-AB instantaneous companding filters for 1.2-V applications,” IEEE J. Solid-State Circuits, vol. 35, pp. 1853–1864, Dec. 2000. [11] V. W. Leung and G. W. Roberts, “Effects of transistor nonidealities on high-order log-domain ladder filter frequency responses,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 373–387, May 2000. [12] J. Mahattanakul and C. Toumazou, “Modular log-domain filters based upon linear Gm-C filter synthesis,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 1421–1430, Dec. 1999. [13] G. van Ruymbeke, C. C. Enz, F. Krummenacher, and M. Declercq, “A BiCMOS programmable continuous-time filter using image-parameter method synthesis and voltage-companding technique,” IEEE J. SolidState Circuits, vol. 32, pp. 377–387, Mar. 97. [14] M. Punzenberger and C. C. Enz, “A 1.2-V low-power BiCMOS class-AB CMOS log-domain filter,” IEEE J. Solid-State Circuits, vol. 32, pp. 1968–1978, Dec. 1997. [15] C. Enz, M. Punzenberger, and D. Python, “Low-voltage log-domain signal processing in CMOS and BiCMOS,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 279–289, Mar. 1999. [16] D. Pyton and C. C. Enz, “A micropower class-AB CMOS log-domain filter for DECT applications,” IEEE J. Solid-State Circuits, vol. 36, pp. 1067–1075, July 2003. [17] S. A. P. Haddad, R. Houben, and W. A. Serdijn, “Analog wavelet transform employing dynamic translinear circuits for cardiac signal characterization,” in Proc. Int. Symp. Circuits Systems (ISCAS’03), vol. 1, Bangkok, Thailand, May 2003, pp. 121–124. [18] S. A. P. Haddad, S. Gieltjes, R. Houben, and W. A. Serdijn, “An ultra low-power dynamic translinear cardiac sense amplifier for pacemaker,” in Proc. Int. Symp. Circuits Systems (ISCAS’03), vol. 5, Bangkok, Thailand, May 2003, pp. 37–40. [19] J. Georgiou and C. Toumazou, “A micropower cochlear prosthesis system,” in Proc. Int. Symp. Circuits Systems (ISCAS’03), vol. 3, Bangkok, Thailand, May 2003, pp. 834–837. [20] G. D. Duerden, G. W. Roberts, and M. J. Deen, “The development of bipolar log domain filters in a standard CMOS process,” in Proc. Int. Symp. Circuits Systems (ISCAS’01), vol. 1, Sydney, Australia, May 2001, pp. 145–148. [21] N. Krishnapura and Y. Tsividis, “Micropower low-voltage analog filter in digital CMOS process,” IEEE J. Solid-State Circuits, vol. 38, pp. 1063–1067, June 2003. [22] A. Gerosa and A. Neviani, “Enhancing output voltage swing in lowvoltage micro-power OTA using self-cascode,” Electron. Lett., vol. 39, no. 8, pp. 638–639, 2003. [23] E. Seevinck, “Companding current-mode integrator: A new circuit principle for continuous-time monolithic filters,” Electron. Lett., vol. 26, no. 24, pp. 2046–2047, 1990. [24] E. Seevinck, E. A. Vittoz, M. du Plessis, T. H. Joubert, and W. Beetge, “CMOS translinear circuits for minimum supply voltage,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 1560–1564, Dec. 2000. [25] H. W. Kleinand and W. L. Engl, “A voltage-current-converter based on a SC-controller,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC’83), Lausanne, Switzerland, Sept. 1983, pp. 119–122. [26] D. R. Frey, “Current-mode CLass AB second-order filter,” Electron. Lett., vol. 30, no. 3, pp. 205–206, 1994. [27] B. Linares-Barranco and T. Serrano-Gotarredona, “On the design and characterization of femptoampere current-mode circuits,” IEEE J. SolidState Circuits, vol. 38, pp. 1353–1363, Aug. 2003.
Andrea Gerosa (S’97–M’99) received the laurea and the Ph.D. degrees in electronic and telecommunication engineering from the University of Padova, Padova, Italy, in 1995 and 1999, respectively. He is currently an Assistant Professor at the University of Padova. From August 1997 to July 1998, he was an Exchange Visiting Graduate Student at the University of California, Berkeley. He is mainly interested in analog integrated circuit design for data-retrieving applications, like hard-disk equalizers or biological signal sensing. He has also dealt with signal processing applications, designing integrated filters, and analog–digital converters. He has authored more than 30 papers in international journal or conference proceedings.
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Andrea Maniero was born in Piove di Sacco, Italy, in 1977. He received the laurea degree in electronics engineering from the University of Padova, Padova, Italy, in 2002. He is currently working toward the Ph.D. degree at the University of Padova. He was a Researcher in the Department of Information Engineering, University of Padova, from May 2002 to May 2003, working on the design and testing of low-power CMOS analog integrated circuits for biomedical applications.
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Andrea Neviani received the laurea degree (cum laude) in physics from the University of Modena, Modena, Italy, and the Ph.D. degree in electronics and telecommunication engineering from the University of Padova, Italy, in 1989 and 1994, respectively. From 1994 to 1998, he was a Research Associate at the University of Padova, where, from November 1998, he holds an Associate Professor position. At present, he is mainly interested in the design of analog and mixed-signal CMOS circuits for analog signal processing (read channels for hard-disk drives, analog turbo decoders, log-domain filters), and for low-power implantable biomedical devices. He is the coauthor of around 60 journal articles and conference papers.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS ,VOL. 51, NO. 10, OCTOBER 2004
A Fully Integrated Dual-Channel Log-Domain Programmable Preamplifier and Filter for an Implantable Cardiac Pacemaker Andrea Gerosa, Member, IEEE, Andrea Maniero, and Andrea Neviani
Abstract—A programmable-gain preamplifier and filter for detection of spontaneous heart activity in an implantable cardiac pacemaker is presented. The system is fully integrated in a standard 0.35- m CMOS technology, including all auxiliary circuits. Two channels are available in order to process both atrial and ventricular signals. CMOS translinear circuits, with particular emphasis on log-domain techniques, have been exploited in order to contain current consumption and to allow correct operation with a reduced supply voltage, due to battery discharging. Indeed, the realized system can operate down to 1.8 V of supply voltage and dissipates at most 1.8 A, granting at least 47 dB of dynamic range (DR) for the atrial chain, which is compatible with advanced digital sensing. Current consumption can be further reduced at the expense of DR if a simpler sensing like peak detection is adopted. All system performance have been verified by measurements results and are compatible with the requirements of cardiac pacemakers. This work, therefore, demonstrates how a proper design approach, exploiting low-power and low-voltage techniques, allows one to optimize performance for the cardiac pacemaker. Index Terms—Biomedical, companding, log domain, low power (LP), low voltage (LV), pacemaker, translinear (TL) circuits.
I. INTRODUCTION
T
HIS PAPER presents a fully integrated programmable preamplifier and filter for the sensing stage of an implantable cardiac pacemaker. The natural heart activity is in fact acquired in responsive pacemakers, in order to set the proper stimulation strategy. The heart activity detection can be performed in different ways [1], from simple peak detection in the analog domain [2] to more complex algorithms based on a digitized version of the signal [3]. In any case, the received signal needs to be amplified and bandpass filtered, which is the functionality performed by the circuit presented in this paper. The circuit was designed with the main goal of containing as much as possible its power consumption and of fully integrating the whole system on a standard CMOS technology, aiming at a cardiac pacemaker fully integrated on a single chip, with almost no external components [4]–[6]. These two factors are of fundamental importance to improve the quality of life of people treated with cardiac pacemakers, because they imply increasing
Manuscript received October 16, 2003; revised March 9, 2004. This work was supported by Medico S.p.A., Rubano, Italy. This paper was recommended by Associate Editor J. Silva-Martinez. The authors are with Department of Information Engineering, University of Padova, 35131 Padova, Italy (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSI.2004.835027
the implanted device duration and reducing its size. Circuit designers have developed low-power (LP) design techniques that can actually be profitably exploited to achieve the desired result. In particular, the proposed system has been realized by means of current-mode translinear (TL) circuits [7], with particular emphasis on log-domain circuits [8], [9]. Log-domain circuits are naturally realized using bipolar transistors [10]–[14], because they are based on the exponential current versus voltage characteristic; however, their CMOS implementation, based on transistor biased in weak inversion, soon became interesting, especially for micropower applications [15], [16]. In fact, circuit solutions for biomedical devices, exploiting CMOS TL circuits can be singled out in literature [17]–[19]. The log-domain approach looks beneficial also for the considered pacemaker application from different points of view. First of all, in these circuits, voltage swings are really limited thanks to the logarithmic compression performed by currentdriven transistors. This characteristic allows to overcome typ- filters, which may require a ical problems of standard transconductor with rail-to-rail input swing and a large range of linearity. Furthermore, the reduced voltage swing makes current-mode TL circuits suited for low-voltage (LV) operation. Although our application does not require extremely LV circuits, correct operation while the supply battery is discharging is required. In fact, the proposed circuits operate with a supply voltage from 2.8 down to 1.8 V, which is 200 mV below the typical end-of-life (EOL) voltage of the battery. More importantly, TL circuits realized with CMOS transistors operating in weak inversion regime have demonstrated significant potential in terms of power efficiency, which is, as mentioned previously, a very important task for this design. Furthermore, the drawback of limited maximum bandwidth of CMOS realizations of TL circuits, with respect to bipolar realization [20], [21], is not a concern at all in this case, due to the characteristic frequencies of cardiac signals. In summary, this paper presents a design example in which some LP and LV design techniques for CMOS circuits have been profitably exploited in order to optimize performance in a specific application, namely the cardiac pacemaker. As a result of the used design procedure, we achieved a total current consumption of 1.8 A, which is fully compatible with available power budget in the implantable device. The system is fully integrated in a 0.35- m CMOS technology, which allows to benefit from the high level of integration of a submicrometer CMOS technology, while does not excessively limit the stimulation pulse
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Fig. 1. Block diagram of one of the two sensing channels for the cardiac pacemaker.
amplitude due to voltage ratings, as explained in [2]. In this case, stimulation voltages must be within 5.5 V (unless the extra cost of high-voltage masks is accepted), but anyway comply with the requirements of a significant segment of the pacemaker market. The proposed circuit operates with a supply voltage from 2.8 V down to 1.8 V, covering the whole voltage range of typical battery that discharges from its initial voltage down to EOL voltage. The system integrates two sensing channels, for detecting both atrial and ventricular activities. Both channels have programmable gain and beyond amplification also perform bandpass filtering, centered at 100 and 70 Hz for atrial and ventricular data paths, respectively. Finally, the system accuracy can be traded off for current consumption by means of a control bit, in order to match the requirements both of simple analog detection and more complex digital sensing. Auxiliary circuits, such as bias currents and clock phases generators are included on-chip and contribute to make the filters frequency response highly insensitive to temperature and process parameters spread, as it is explained in detail in Section III-E. The system-level description of the realized circuit is reported in Section II, while the corresponding circuit-level details are reported in Section III, where design criteria for each basic block are discussed. All performances and figures of merit have been verified by means of measurements, which are described in Section IV. Finally, conclusions are drawn in Section V. II. PACEMAKER INPUT STAGE Independently of the kind of processing chosen in order to extract the information of interest from the acquired signal, a cardiac pacemaker sensing stage definitely needs to amplify the signal: indeed, the peak amplitude for the atrial signal can be as low as 100 V, while, for the ventricular signal, it can be as low as 400 V. Furthermore, in some cases, the signal can actually exhibit a 4-mV or 8-mV peak amplitude for the atrial and ventricular paths respectively. It is therefore apparent that making the gain programmable can significantly relax dynamic range (DR) performance required to the other blocks in the data paths. Beyond the required functionality of a programmable-gain preamplifier, the proposed system also introduces a bandpass filtering in order to suppress noise and signal components out of the band of interest. In our case, the atrial filter is centered at 100 Hz, while the ventricular one is centered at 70 Hz, which is a common choice for pacemker applications [1]. The block diagram of one sensing channel is reported in Fig. 1. Both the atrial and ventricular channels can be represented by the diagram of Fig. 1 because they only differ for the gain range and center frequency. The signal coming from
Fig. 2. Circuit schematic of the input transconductor. The input stage of the linear amplifier loads the two output nodes with a circuit like the one drawn in dashed line.
the heart is in the voltage domain, while TL circuits operate in the current domain. Therefore, the first block in the diagram of Fig. 1 is a transconductor that realizes the voltage-to-current ) conversion. As will be explained in Section III-A, this ( block is actually the most critical from the noise point of view and hence it will result the most current consuming block. The current signal coming from the transconductor passes through a current-domain programmable amplifier. Finally, the bandpass filtering is performed by a log-domain biquad. As shown in Fig. 1, this filter requires proper signal compression and conditioning at the input (performed by the splitter) and expansion at the output (performed by the expander). The details of circuit design for the blocks in Fig. 1 are reported in Section III, while the corresponding measured results will be discussed in Section IV. III. CIRCUIT REALIZATION The system described in Section II has been fully integrated in a double-poly triple-metal 0.35- m CMOS technology. Most of the MOS transistors are operated in the weak inversion regime, in order to achieve the exponential characteristic, as required by the log-domain approach, and in order to exploit the best efficiency in terms of transconductance over bias current. Conversely, current mirrors are operated in strong inversion, in order to minimize the effect of device mismatch. The basic building blocks of Fig. 1 are described in the following subsections. The atrial and ventricular channels use one replica each of the circuit block described below. In fact, the two channels are identical from the point of view of circuit topologies, the only difference being in terms of some bias current and device size. These differences will be highlighted in the description below as well. A. Input Transconductor In order to convert the single-ended input voltage in a differential current signal, the transconductor of Fig. 2 is used. Basically, the conversion is performed by the p-MOS differential pair (p-MOS devices have been chosen because they noise with respect to n-MOS ones), hence, introduce less simply relates to the input the output differential current according to voltage (1)
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where is the transconductance of p-MOS M1 and M2. A folded architecture for the circuit of Fig. 2 has been preferred with respect to a simpler differential pair with an active load, in order to optimize the circuit bias condition. In order to understand this issue, it is worth observing that, according to the diagram of Fig. 1, the transconductor drives the current amplifier, whose input stage acts as a virtual ground. Such an input stage is drawn in a dashed line for the positive data path in Fig. 2. The transconductor output node is, in fact, connected to a node , where is the gate-to-source that is biased at voltage of the p-MOS M12, which is biased with a constant current of 25 nA. Since M12 is in weak inversion regime, its gate . Forcing at such results just few hundreds of millivolt below a voltage, the drain of M1 and M2 would severely limit the input common-mode range of the transconductor, while in the cardiac pacemaker, a large range is required in order to improve high frequency disturbances suppression. Therefore, the folded-cascode configuration is exploited as shown in Fig. 2 in order to bias the drain of M1 and M2 at the lowest possible value that keeps M3 and M4 saturated, independently from the bias voltage of the output nodes. Furthermore, the cascode configuration improves the mirroring accuracy of n-MOS (M3 and M4) and p-MOS (M9 and M10), thus reducing the transconductor offset. It is worth stressing that a self-cascode configuration is used, operating the mirroring transistors in strong inversion and the cascode ones in weak inversion, as explained in [22]. This solution requires a really limited voltage headroom for the cascode, hence this circuit solution is compatible with output bias point close to . The key issue in the design of the transconductor is circuit noise, because the input-referred noise of this block sums directly to the input signal before any amplification. As demonstrated in the Appendix , the spectral density of the input-reand flicker noise can be expressed ferred thermal noise as in (2) and (3) (2) (3) is the Boltzman constant, is the absolute temperwhere is the oxide capacitance, and are techature, and are, respectively, nology-dependent constants, and the transconductance and the channel length of transistor Mi in Fig. 2. Remembering that the differential pair is operated in weak inversion and hence the transconductance linearly depends on flowing in the transistor, while for M3 and the bias current M9 the square-root dependence typical of strong inversion applies, it is apparent from (2) that in order to reduce the circuit noise it is necessary to increase the bias current . Similar considerations apply to flicker noise, according to (3). These considerations highlight a critical design tradeoff, because power consumption of this system has to be contained as much as possible. The proposed system is intended for a digital sensing chain, where the acquired signal is digitized with an 8-bit accuracy.
TABLE I TRANSISTOR W=L (IN MICROMETERS) FOR CIRCUIT OF FIG. 2
The maximum input signal expected when the gain is programmed to its highest value is 280 V . Therefore, an upper limit for the input-referred noise is 280 V
1.1 V
(4)
Exploiting (2) and (3), a good design tradeoff between power and noise resulted in a differential pair size of 400 m/12 m of 200 nA for the atrial chain. The channel and a bias current ( 200 m, length of M3 and M9 is much larger than 32 m), in order to force the devices in strong inversion, as mentioned previously (size of all devices are reported in Table I). This choice is also beneficial from the noise perspecresults in being larger tive. Indeed, the transconductance and ; hence, the last two terms in (2) are minithan mized. Furthermore, having long channels also minimizes the terms in (3). Noise performance has been verified by accurate simulations and the measurement results will be discussed in Section IV. The proposed preamplifier is also compatible with a simpler analog detection circuitry, where the required accuracy is lower. In this case, in order to save power, the bias current in the atrial transconductor can be reduced to 50 nA. For this reason, the bias current to the transconductor is delivered by a programmable current mirror, which replicates a 25-nA reference current with a multiplying factor that can be set to 4 or 16. In the case of the ventricular chain, where the minimum input signal is twice that with respect to the atrial case, the bias current is constantly set to 50 nA and the transistors size is identical to the atrial case. The effect of device mismatch is not as critical as noise, because the resulting offset is a dc signal and hence is suppressed by the bandpass filter following in the data path. However, the offset must not be too large in order to prevent overloading for the current amplifier input stage. Anyway, this is not the case for the offset resulting from transistors with the aforementioned sizes. Finally, the conversion gain is equal to 625 nS and 2.5 S in the case of the bias current equal to 50 and 200 nA, respectively. Such a gain difference is compensated in the last stage of the preamplifier, as will be explained in Section III-D. B. Seevinck Integrator The other blocks composing the preamplifier are based on the log-domain integrator proposed by Seevinck in [23]. Such a circuit has been chosen because it represents a good compromise between circuit complexity and LV operation: this integrator indeed is slightly more complex than the integrator in [16], but requires less voltage headroom. Recently, a modified version of this integrator, suited for a LV operation, has been proposed
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Fig. 3. Circuit schematic of the log-domain integrator introduced by Seevinck. Fig. 5. Circuit schematic of the biquadratic filter. The transconductors are replaced by log-domain integrators.
Fig. 4. Circuit schematic of the linear current-mode programmable amplifier.
[24], but the original version can anyway fit into the limits imposed by our EOL supply battery. The fully differential version of the integrator is reported in Fig. 3. It can be demonstrated [6], [23] that this circuit actually performs a current-domain integration, according to the expression (5) where is the differential input signal, is the is the thermal potential. technology slope factor, and C. Programmable Amplifier Assuming that in the circuit of Fig. 3, the two integrating capacitors C are replaced by two current sources , then the circuit of Fig. 4 is obtained if we momentarily ignore the transistors within the shaded area. In this case, the circuit transfer function becomes [6] (6) Equation (6) clearly represents a current-mode linear amplifier. This circuit has been used both in the atrial and ventricular by means of programmable curchain, delivering the current rent mirrors that replicate a reference current, equal to , multiplied by four possible values: 1, 1/4, 1/7, and 1/10. Therefore, this block clearly introduces gain programmability for the whole data path. However, varying the reference current implies modifying the quiescent currents in the circuit, too. As a consequence, the output current of the amplifier exhibits a nonzero commonmode component that depends on the value programmed for , which obviously complicates interfacing with the following
blocks in the data path. This issue is actually solved by the transistors in the shaded area in Fig. 4 that null the output commonmode component independently on the programmed gain. The drain currents of M10 and M9 are in fact replicated by M14 and M13, respectively, and then summed together in the drain of M15 and M16. Half of such a current is subtracted from the drain current of M10 and M9 by M12 and M11, respectively. The net effect is that only the differential component of the two currents in M10 and M9 is delivered to the log-domain filter that follows the amplifier. The value of must be larger than the maximum value expected for the input signal, in order to grant that a nonzero current flows in M4 and M3. However, is not required to be much larger than the input current, in order to linearize input transistors. Indeed, the circuit of Fig. 4 is a TL circuit, therefore, it exploits the nonlinear behavior of the MOS devices. In summary, the maximum input signal is 8 mV, which is converted to a 20-nA current by the transconductor. Therefore, is set to 25 nA in order to account for a safety margin for the current signal swing. Transistors are then sized wide enough in order to grant that their current density is sufficiently low to keep the devices in weak inversion. Device mismatch can also be a critical issue for this block. Indeed, as a result of transistor mismatch, a differential offset current can arise, which is eventually amplified by a factor of 10 when the gain is programmed to its maximum value. Although any dc component should be suppressed by the bandpass filter following in the data path, if the offset current is too large, it can actually force the transistors in the filter significantly out of weak inversion, degrading the system response. For this reason, devices have been made sufficiently large in order to reduce such an effect. Namely, transistors in Fig. 4 are 80 m/7 m, with the exception of M11, M12, M15, and M16, which are 2 m/200 m, to be forced in strong inversion and hence to enhance the current mirrors accuracy. D. Filter Signal and noise components out of the band of interest are suppressed by means of a second-order bandpass biquadratic log-domain filter. It is well established [10]–[13] that the filter - filter block diagram, as can be represented as an usual reported in Fig. 5, assuming that each transconductor is replaced
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TABLE II MAIN PARAMETERS FOR BIQUADRATIC FILTERS
by a replica of the log-domain integrator of Fig. 3. The filter transfer function can be expressed as
Fig. 6.
Circuit schematic of the splitter.
Fig. 7.
Circuit schematic of the expander.
(7) where is the bias current of the integrator. Observing the transfer function (7), the relationship between the filter center frequency and quality factor can be expressed in terms of the circuit parameters as (8) The required center frequency is 100 and 70 Hz for the atrial and ventricular channel, respectively, while the quality factor is 2 for both channels. Observing from (8) that the factor depends on capacitors value only, it is convenient from a layout point of view to set identical capacitors value for the atrial and ventricular channels. The lowest possible value for should be chosen in order to reduce power consumption, but a lower limit is set by feasibility and noise issues. Furthermore, in order to maintain the desired center frequency, if the bias current is reduced, then, the capacitor value must be reduced by the same factor, according to (8). This is of course beneficial, but once again implies circuit noise increase and could make the effect of MOS parasitic capacitances significant. A good design com37.5 pF and 9 pF and promise resulted in setting 400 pA and 280 pA for the atrial and a bias current ventricular chain, respectively, as summarized in Table II. The generation of these low currents will be covered in Section III-E. It is worth observing that the bias current in the filter is significantly lower than the one in the input transconductor, therefore a further reduction of the bias current in the filters would not significantly reduce the total power dissipation of the system. Transistor size is again chosen in order to keep the maximum current density safely below the transition current between weak and strong inversion. With this in mind, it is worth considering that although the bias current in the integrators is in the order of a few hundreds of picoamperes, the current signal coming from the linear amplifier can be as high as 20 nA. Therefore, such a current range must be considered to size the transistors. In summary, the size for the transistors in all the four replicas of the Seevink integrator (two for the atrial chain and two for the ventricular one) ranges from 25 m/5 m to 75 m/5 m. A log-domain filter requires a proper compression of the input signal. Furthermore, the proposed filter operates in CLass AB [10] in order to extend the output current range and to limit current consumption with low signals. Therefore, the input signal
must also be properly conditioned. These two tasks are performed by the splitter circuit reported in Fig. 6 [26]. The TL principle can be applied to two loops in this circuit, namely M1–M3–M5–M6 and M2–M4–M5–M6. As a result, the drain and obey (9) currents of M1 and M2
(9) Hence, and represent, respectively, the positive and negative components of the input signal to the filter, while the geometric mean of these two components is kept constant. This approach has indeed demonstrated to be the most effective for log-domain filters [14]. Finally, the input signal compression is compensated by the expander circuit of Fig. 7. The two compressed output voltage and are applied to the gates of signals of the filter M3–M4 and M1–M2, respectively; therefore, the drain current of these p-MOS transistors represents the uncompressed filtered signal. The sum of these two currents flows in M6 and M7, and half of such a sum is subtracted from both the drain currents of M1 and M4, using M5 and M8, respectively. Therefore, a differential output current with a zero common-mode component is finally delivered to the output. In the case of the atrial chain, the size of p-MOS transistors is programmable in order to compensate for the different transconductor gain in the case of digital or analog sensing, as discussed previously in Section III-A. E. Bias Current Generation As explained in Section III-D, the filter requires the generation of two currents in the order of few hundreds of picoamperes. These currents are generated using the switched-capacitor (SC) current generator reported in Fig. 8 [25]. The generated current is equal to (10)
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Fig. 8.
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is basically identical in the eight cases, proving that the bias curvariations. The gain variation that can rent compensates the be appreciated in Fig. 10(b) is mainly due to variation in the transconductance of the first stage in the data path. This impairment is acceptable due to gain programmability in the whole chain. Recently in [27], an alternative technique for the generation of low currents has been discussed: that current generator is however well suited for the generation of a reference current that is independent from process parameters that can be hardly controlled. In the circuit proposed in this paper however, we need a reference current that depends on a capacitor, as explained previously. This makes the used SC current generator definitely preferable with respect to the technique discussed in [27]. Finally, the need of a clock signal for the SC current generator does not significantly complicate the circuit, because a reference clock is likely to be present in the whole pacemaker circuit (e.g., sampling clocks in the converter, phase clocks in the charge pump that generates the stimulation voltage [4] and reference clock for the digital processing core).
Circuit schematic of SC low-current generator.
F. Circuit Layout
Fig. 9. Circuit schematic of the reference voltage generation.
where is the duration of clock signal at high level and is a reference voltage. In particular, such a voltage in obtained by the circuit reported in Fig. 9, which, assuming that the two transistors are in weak inversion regime, generates a voltage equal to (11) It is apparent from (11) that voltage is highly insensitive to process parameters variations, assuming that the transistors in Fig. 9 are well matched, while it is proportional to absolute temperature. It is interesting to exploit this information in order to inspect the dependence of filter center frequency on parameters and temperature variation. Combining (8) and (10), it can be observed that the filter center frequency is proportional to (12) The first ratio on the right-hand side of (12) is obviously highly insensitive to capacitor non idealities, provided that the capacitors are properly laid out, and hence, matched. The second term is the ratio of two quantities both proportional to the thermal potential; therefore, temperature dependence cancels out. Finally, we can assume that the reference clock is generated with high accuracy using a crystal oscillator. Therefore, the filter transfer function results highly insensitive to process parameter and temperature spread. This statement is supported by the results of corner simulations, performed varying both process parameters and temperature. Fig. 10(a) reports the value of the generated reference current for eight different corners: the current variation is apparent. Fig. 10(b) reports the corresponding frequency response of the filter: it can be observed that the poles position
The microphotograph of the circuit, realized in a 0.35- m CMOS technology is reported in Fig. 11. The two channels can be singled out in the upper and lower part of the photo, while in the right-side part the capacitor arrays for the two bandpass filters can be recognized. As mentioned in Section III-D, the two filters differ in the bias current and not in capacitor values, hence the two arrays are identical. Of course, for capacitor arrays and critical transistors, typical common-centroid layout techniques have been used. The total area of the two channels is 1.3 mm . IV. EXPERIMENTAL RESULTS The system performance has been evaluated measuring different prototypes of the realized circuit at supply voltages of 2.8 and 1.8 V. The circuit is stimulated by a signal generator ac coupled to the prototype mounted on a printed circuit board. The output current signals are converted to the voltage domain using two precise 1-M resistors. The obtained voltage signals are then amplified by means of an instrumentation amplifier, which also converts the fully differential signals in a single-ended one. Finally, such a signal is delivered to an oscilloscope or a spectrum analyzer. Thefrequencyresponseofthetwochannelsmeasuredata1.8-V supply voltage is reported in Fig. 12. The measured center frequency is 105 and 72 Hz for the atrial and ventricular channels, respectively, while the factor is equal to 1.98 and 2. Another important parameter for the sensing chain is the gain at center frequency .Thesensingchainhasbeingdesignedinordertodeliver an output differential current of 20 nA when the input signal is maximum. In order to express the center band gain with a non-dimensionalquantityratherthaninamperespervolt,weassumethat a 20-nA output current corresponds to a voltage signal with amplitude 1 V . Given this clarification, the measured gain values can be inspected in Table III and in Table IV for the atrial and ventricular chains, respectively. As underlined in the two tables, the realized sensing chains allow to program 4 different values for the
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Fig. 10. Corner simulation results. (a) Generated reference current for eight different corners. (b) Corresponding frequency response of the filter.
Fig. 12. Measured frequency response of the two channels at supply voltage of 1.8 V. TABLE III MEASURED CENTERBAND GAIN FOR ATRIAL CHAIN
TABLE IV MEASURED CENTERBAND GAIN FOR VENTRICULAR CHAIN
Fig. 11. Chip microphotograph.
center band gain, using two control bits. Finally, the two tables report the theoretical gain values. The total harmonic distortion (THD) measured in the worst case is 32 dB: such a distortion level is acceptable for the car-
diac signal acquisition, because the heart signal degradation is anyway not so significant to impair the estimate of the spontaneous heart activity. In the light of this characteristic of the pacemaker application, the log-domain filter design has not been optimized from the linearity perspective. Another important parameter is the noise generated by the realized circuit. The most critical configuration corresponds to the gain programmed to the maximum value, because the transconductor noise is amplified by the current-domain programmable
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TABLE VI MAIN CHARACTERISTICS OF REALIZED PROTOTYPE
Fig. 13.
Measured worst case noise spectrum for the atrial chain.
TABLE V MEASURED PERFORMANCE FOR TWO-CHANNEL SENSING STAGE
amplifier. The output noise spectrum measured in this configuration and for a supply voltage of 1.8 V is shown in Fig. 13: the frequency shaping due to the bandpass filter is apparent, hence this measurement confirms that the main noise contributor is the input transconductor, as claimed in Section III-A. The noise amplitude measured at 2.8- and 1.8-V supply voltage are reported in Table V, along with the other parameters of the frequency response discussed above. In the atrial chain, which must receive the lowest signal, a worst case measured noise amplitude equals 42 pA , which corresponds to about 47 dB of DR. The maximum measured current consumption of the whole system is 1.8 A (it is worth reminding that in battery operated systems the current consumption is much more meaningful than power consumption). This consumption has been measured with a maximum amplitude input signal to both the channels, in order to force the Class AB stages to deliver their maximum currents. The consumption is due to the atrial chain for 60% and to the ventricular one for 33%, while the remaining consumption is due to auxiliary circuits (e.g., bias current and clock phases generation) that are all integrated on-chip. The atrial chain exhibits a larger consumption because during the measurement it was programmed to operate in high accuracy-mode, compatible with digital sensing (refer to Section III-A). If the atrial chain is in low accuracy mode, then the total current consumption is reduced to 1.3 A. The achieved results in terms of current consumption, along with the consideration that the system operates with supply voltage within 2.8 and 1.8 V, prove that the designed sensing stage is fully compatible with the requirements imposed to
implantable cardiac pacemaker by the battery technology. Moreover, the measured performance, which is summarized in Table VI, is in accordance with initial specification, therefore the realized circuit is a realistic fully integrated sensing stage for cardiac pacemaker, giving a significant contribution to full integration on a single chip of this kind of biomedical implantable devices. V. CONCLUSION A system suited for amplification and filtering of natural heart activity in implantable pacemakers has been fully integrated in standard 0.35- m CMOS technology. Two channels are available for processing both atrial and ventricular signals. CMOS TL circuits and log-domain filtering have been exploited in order to contain current consumption and to allow the system to operate with an EOL battery. As a result of such an approach, the measured current consumption is at most 1.8 A, with a minimum power supply of 1.8 V and achieving a DR for the atrial channel of at least 47 dB, which is compatible with an advanced digital sensing. According to measurement results, both the channels exhibit the expected programmable gain and implement a biquadratic filter with a quality factor of about 2 and a center frequency at 105 and 72 Hz for atrial and ventricular channels respectively, which are the expected characteristic for the realized processing block. Furthermore 1.8 V is about 200 mV below the EOL battery voltage, while the measured consumption is definitely acceptable for the power budget typically available in pacemakers, hence the realized circuit can realistically be part of a fully integrated pacemaker, with advanced pacing strategy. This work therefore demonstrates how a proper design approach, exploiting low-power and LV techniques, allows one to optimize circuit performance for the cardiac pacemaker application. APPENDIX NOISE IN INPUT TRANSCONDUCTOR The aim of this appendix is to demonstrate (2) and (3) about the noise in the transconductor. The thermal noise of MOS transistors can be expressed as noise current in the channel, whose spectral density is (13) where equals 2/3 for saturated transistors operating in strong inversion, while it becomes 1/2 for saturated transistors in weak inversion regime. Recalling from Section III-A that the input pair in the transconductor of Fig. 2 operates in weak inversion, while the mirroring transistors are in strong inversion regime,
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the total output current due to thermal noise exhibits the spectral density (14) (14) where term 2 accounts for the fact that the circuit is differential. Such a noise can be input-referred dividing the spectral density by the squared transconductance of the input pair, obtaining (15) that is identical to (2) The spectral density of the channel current due to flicker noise can be expressed both for transistors in strong and weak inversion as (16) The spectral density of the total flicker noise current can be evaluated with a similar approach with respect to thermal noise, obtaining the following expression (17) Finally, the noise can be input referred using the input pair transconductance, obtaining (18) that is identical to (3). ACKNOWLEDGMENT The authors would like to thank Prof. E. Zanoni for supporting this research activity. REFERENCES [1] J. G. Webster, Design of Cardiac Pacemakers. Piscataway, NJ: IEEE Press, 1995. [2] L. Lentola, A. Mozzi, A. Neviani, and A. Baschirotto, “A 1-A front end for pacemaker atrial sensing channels with early sensing capability,” IEEE Trans. Circuits Syst. II, vol. 50, pp. 397–403, Aug. 2003. [3] J. N. Rodrigues, V. Owall, and L. Sornmo, “QRS detection for pacemakers in a noisy environment using a time lagged artificial neural network,” in Proc. Int. Symp. Circuits Systems (ISCAS’01), vol. 3, Sydney, Australia, 2001, pp. 596–599. [4] A. Novo, A. Gerosa, and A. Neviani, “A submicrometer CMOS programmable charge pump for implantable pacemaker,” Anal. Integr. Circuits Signal Processing, vol. 27, no. 3, pp. 211–217, 2001. [5] A. Gerosa and A. Neviani, “A very low-power 8-bit sigma-delta converter in a 0.8 m CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V,” in Proc. Int. Symp. Circuits Systems (ISCAS’03), vol. 5, Bangkok, Thailand, May 2003, pp. 49–52. [6] A. Gerosa, A. Novo, A. Mengalli, and A. Neviani, “A micro-power, low-noise, log-domain amplifier for the sensing chain of a cardiac pacemaker,” in Proc. Int. Symp. Circuits Systems (ISCAS’01), vol. 1, Sydney, Australia, May 2001, pp. 296–299. [7] B. Gilbert, “Translinear circuits: A Proposed classification,” Electron. Lett., vol. 11, no. 1, pp. 14–16, 1975. [8] D. R. Frey, “Log-domain filtering: An approach to current-mode filtering,” Proc. Inst. Elect. Eng. , pt. G, vol. 140, pp. 406–416, Dec. 1993. , “Log-domain filtering for RF applications,” IEEE J. Solid-State [9] Circuits, vol. 31, pp. 1468–1475, Oct. 1996.
[10] M. N. El-Gamal, R. A. Baki, and A. Bar-Dor, “30–100-MHz NPN-only variable-gain class-AB instantaneous companding filters for 1.2-V applications,” IEEE J. Solid-State Circuits, vol. 35, pp. 1853–1864, Dec. 2000. [11] V. W. Leung and G. W. Roberts, “Effects of transistor nonidealities on high-order log-domain ladder filter frequency responses,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 373–387, May 2000. [12] J. Mahattanakul and C. Toumazou, “Modular log-domain filters based upon linear Gm-C filter synthesis,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 1421–1430, Dec. 1999. [13] G. van Ruymbeke, C. C. Enz, F. Krummenacher, and M. Declercq, “A BiCMOS programmable continuous-time filter using image-parameter method synthesis and voltage-companding technique,” IEEE J. SolidState Circuits, vol. 32, pp. 377–387, Mar. 97. [14] M. Punzenberger and C. C. Enz, “A 1.2-V low-power BiCMOS class-AB CMOS log-domain filter,” IEEE J. Solid-State Circuits, vol. 32, pp. 1968–1978, Dec. 1997. [15] C. Enz, M. Punzenberger, and D. Python, “Low-voltage log-domain signal processing in CMOS and BiCMOS,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 279–289, Mar. 1999. [16] D. Pyton and C. C. Enz, “A micropower class-AB CMOS log-domain filter for DECT applications,” IEEE J. Solid-State Circuits, vol. 36, pp. 1067–1075, July 2003. [17] S. A. P. Haddad, R. Houben, and W. A. Serdijn, “Analog wavelet transform employing dynamic translinear circuits for cardiac signal characterization,” in Proc. Int. Symp. Circuits Systems (ISCAS’03), vol. 1, Bangkok, Thailand, May 2003, pp. 121–124. [18] S. A. P. Haddad, S. Gieltjes, R. Houben, and W. A. Serdijn, “An ultra low-power dynamic translinear cardiac sense amplifier for pacemaker,” in Proc. Int. Symp. Circuits Systems (ISCAS’03), vol. 5, Bangkok, Thailand, May 2003, pp. 37–40. [19] J. Georgiou and C. Toumazou, “A micropower cochlear prosthesis system,” in Proc. Int. Symp. Circuits Systems (ISCAS’03), vol. 3, Bangkok, Thailand, May 2003, pp. 834–837. [20] G. D. Duerden, G. W. Roberts, and M. J. Deen, “The development of bipolar log domain filters in a standard CMOS process,” in Proc. Int. Symp. Circuits Systems (ISCAS’01), vol. 1, Sydney, Australia, May 2001, pp. 145–148. [21] N. Krishnapura and Y. Tsividis, “Micropower low-voltage analog filter in digital CMOS process,” IEEE J. Solid-State Circuits, vol. 38, pp. 1063–1067, June 2003. [22] A. Gerosa and A. Neviani, “Enhancing output voltage swing in lowvoltage micro-power OTA using self-cascode,” Electron. Lett., vol. 39, no. 8, pp. 638–639, 2003. [23] E. Seevinck, “Companding current-mode integrator: A new circuit principle for continuous-time monolithic filters,” Electron. Lett., vol. 26, no. 24, pp. 2046–2047, 1990. [24] E. Seevinck, E. A. Vittoz, M. du Plessis, T. H. Joubert, and W. Beetge, “CMOS translinear circuits for minimum supply voltage,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 1560–1564, Dec. 2000. [25] H. W. Kleinand and W. L. Engl, “A voltage-current-converter based on a SC-controller,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC’83), Lausanne, Switzerland, Sept. 1983, pp. 119–122. [26] D. R. Frey, “Current-mode CLass AB second-order filter,” Electron. Lett., vol. 30, no. 3, pp. 205–206, 1994. [27] B. Linares-Barranco and T. Serrano-Gotarredona, “On the design and characterization of femptoampere current-mode circuits,” IEEE J. SolidState Circuits, vol. 38, pp. 1353–1363, Aug. 2003.
Andrea Gerosa (S’97–M’99) received the laurea and the Ph.D. degrees in electronic and telecommunication engineering from the University of Padova, Padova, Italy, in 1995 and 1999, respectively. He is currently an Assistant Professor at the University of Padova. From August 1997 to July 1998, he was an Exchange Visiting Graduate Student at the University of California, Berkeley. He is mainly interested in analog integrated circuit design for data-retrieving applications, like hard-disk equalizers or biological signal sensing. He has also dealt with signal processing applications, designing integrated filters, and analog–digital converters. He has authored more than 30 papers in international journal or conference proceedings.
GEROSA et al.: FULLY INTEGRATED PREAMPLIFIER AND FILTER FOR CARDIAC PACEMAKER
Andrea Maniero was born in Piove di Sacco, Italy, in 1977. He received the laurea degree in electronics engineering from the University of Padova, Padova, Italy, in 2002. He is currently working toward the Ph.D. degree at the University of Padova. He was a Researcher in the Department of Information Engineering, University of Padova, from May 2002 to May 2003, working on the design and testing of low-power CMOS analog integrated circuits for biomedical applications.
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Andrea Neviani received the laurea degree (cum laude) in physics from the University of Modena, Modena, Italy, and the Ph.D. degree in electronics and telecommunication engineering from the University of Padova, Italy, in 1989 and 1994, respectively. From 1994 to 1998, he was a Research Associate at the University of Padova, where, from November 1998, he holds an Associate Professor position. At present, he is mainly interested in the design of analog and mixed-signal CMOS circuits for analog signal processing (read channels for hard-disk drives, analog turbo decoders, log-domain filters), and for low-power implantable biomedical devices. He is the coauthor of around 60 journal articles and conference papers.
