Automatic phase alignment for a fully integrated ... - Semantic Scholar
ISSCC 2003 / SESSION 15 / CELLULAR COMMUNICATIONS / PAPER 15.1
15.1
Automatic Phase Alignment for a Fully Integrated CMOS Cartesian Feedback Power Amplifier System
Joel L. Dawson, Thomas H. Lee Department of Electrical Engineering, Stanford University, Palo Alto, CA The need for accurate phase alignment between modulator and demodulator local oscillators (LOs) has frustrated attempts to realize Cartesian feedback in integrated form. Past efforts to solve this problem have resulted in cumbersome implementations not amenable to integration [1]. In this paper we report the first known fully integrated Cartesian feedback linearization system, and describe in detail the automatic phase alignment system that makes it possible. The power amplifier itself, which is integrated on the same die, delivers a maximum power of 14.2dBm at 2GHz into a 50Ω load. Figure 15.1.1 illustrates the principle of the technique, which was first described in [2]. Phase alignment is achieved via a nonlinear dynamic system that is mathematically described as dθ/dt = G(IQ' - QI') = -Grr'sin(∆θ). Variables (I,Q) and (r,θ) are baseband symbols in Cartesian and polar representations, respectively; unprimed coordinates denote symbols as they enter the modulator, primed coordinates denote demodulated symbols. The original prototype described in [2] realized the required rotation by directly phase shifting the modulator LO; substantial power savings result from doing symbol rotation at baseband, as shown here. Regardless, rotation should be performed in the forward path of the Cartesian feedback loop, where the unavoidable artifacts of imperfect rotation are maximally suppressed. The achieved accuracy of phase alignment is limited by errors in computing the sum of products IQ' - QI'. A major source of these errors is offsets in the analog multipliers. Our basic multiplier cell is shown in Fig. 15.1.2 [3]. A mathematically complete description of a multiplier's offset behavior requires at least three quantities: δI and δQ, the offsets attributable to the inputs, and δO, the offset introduced in the current-to-voltage conversion performed at the output of the multiplier. Minimizing these offsets is difficult: one might imagine, for example, some combination of careful, symmetrical layout and a calibration step. We introduce instead the technique shown in Fig. 15.1.2. The underlying idea is to employ chopper stabilization to eliminate (or at least greatly suppress) these multiplier offsets which produce the dominant phase alignment errors in conventional realizations. The critical modifications to the traditional chopping technique are chopping the two inputs in quadrature, and then chopping down at twice the original chopping frequency. To the extent that the quadrature relationship in the chopping clocks is perfect, offsets δI, δQ, and δO are completely circumvented. In Fig. 15.1.3, we show how the phase error calculation and integration are carried out on the fabricated IC. The chopping frequency f0 is 2.5MHz, down chopping occurs at 5MHz, and all clocks are derived from a 20MHz off-chip crystal oscillator. As can be seen in the diagram, a switched-capacitor integrator provides the integration, and two factors motivate this choice over continuous time methods. The first factor is that much of the offset removal shown in Fig. 15.1.2 is wasted if the integrator that follows has a large input-referred offset. Accordingly, an autozeroing switched-capacitor integrator is used1. The second factor is that high speed in the phase alignment system is unnecessary, as the proper phase setting typically evolves on time scales no
• 2003 IEEE International Solid-State Circuits Conference
shorter than those of temperature change, aging, and process variation. A slow integrator is thus appropriate, and easily realized with a slowly clocked S.C. integrator. Its fully differential op-amp draws 524µA, and has a simulated DC gain of 115dB. The unwanted chopping artifacts centered at 2.5MHz and 5MHz are not filtered out. Instead, the integrator is clocked at 39.2kHz, which has the property of aliasing tones at 2.5MHz and 5MHz to π/4 and π/2, respectively, in the z-domain2. As a result, aliasing of these artifacts does not result in DC errors. The chopping clocks’ transitions occur on the rising edge of the 20MHz source, while the integrator clock transitions occur on the falling edge. This ensures that edges of the chopping clocks do not occur at a sampling instant. The chosen means of realizing analog symbol rotation is depicted in Fig. 15.1.4, where four analog multiplier cells form the core of the matrix rotator block. The sinθ input to the rotator block is taken directly from the integrator, while the cosθ input is computed by an analog feedback loop. This loop acts to preserve the 1-norm of the (vsinθ, vcosθ) pair: |vsinθ| + |vcosθ| = Vref, where Vref is set by the resistive divider. This is a departure from [2], where in order to achieve pure rotation without affecting the magnitude of the symbol the 2-norm, |vsinθ|2 + |vcosθ|2 = Vref, was used. Use of the 1-norm was a purely simplifying decision that removed analog squarers from the system. Fortunately, the resultant warping of the symbol magnitude is rejected by the Cartesian feedback loop. For |vsinθ| ≤ Vref, the circuit in Fig. 15.1.4 enables rotations over a range of ±90 degrees. This implementation accounts for 3.1mW of the overall power dissipation. Figure 15.1.5 summarizes the phase regulation of the prototype IC. It is seen that the phase error never exceeds 9 degrees over the full range of disturbances, which is more than adequate to keep the Cartesian feedback loop stable. Figure 15.1.6 shows the offset of the phase error computation circuit in Fig. 15.1.3 referred to the input of the first gain stage. This offset for a chopping frequency of 2.5MHz is 414µV, and here the effectiveness of the chopping strategy is evident: the differential pair of the first gain stage alone has a 1-σ Vt mismatch of 7.8mV. By way of comparison, complete failure of the phase alignment system corresponds to an offset of 4.4mV. The complete IC was fabricated in National's 0.25µm CMOS process. Figure 15.1.7 shows a die micrograph of the chip, which occupies 4.1x4.1mm2. The complete Cartesian feedback linearization system draws 9.5mA from a 2.5-volt supply. All signal paths are fully differential. 1 Its offset is further mitigated by the two preceding gain stages shown in Fig. 15.1.3. 2 Any frequency determined by 4f0/n, where n is an odd integer, will have this property. For this IC, n is 255.
Acknowledgements The authors gratefully acknowledge National Semiconductor for fabrication of the prototype IC. References [1] B. Razavi, RF Microelectronics, Prentice-Hall, Inc., Upper Saddle River, NJ, 1998. [2] J.L. Dawson and T.H. Lee, “Automatic Phase Alignment for High Bandwidth Cartesian Feedback Power Amplifiers,” IEEE Radio and Wireless Conference, pp. 71-74, 2000. [3] G. Han and E. Sanchez-Sinencio, “CMOS Transconductance Multipliers: A Tutorial,” IEEE Transactions on Circuits and Systems-II, vol. 45, no. 12, pp. 1550-1563, December 1998.
0-7803-7707-9/03/$17.00
©2003 IEEE
,
2QFKLS
FRVș VLQș VLQș FRVș ș
4
, 5)
4
/2
,4
ș GșGW
V
*
4XDGUDWXUH FKRS# I
,
4
, 4
/2
&VPDOO
5)
&KRS
9PLG
,
[ [ 4
4
,
4XDG 4 GUDWXUH &KRS
&KRS
\ \
[\
,R ,R
SELDV
\ \
, 4
4
4
δ4 $QDORJPXOWLSO\FHOO
9PLG
, 4
7RV\PERO URWDWLRQ
,QWHJUDWRU
,R
I &KRS
,R
FRVș VLQș VLQș FRVș FRVș VLQș
7RXSFRQ YHUVLRQ
SELDV
[\
Σ
,
Figure 15.1.2: New technique for offset-free analog multiplication.
4
4XDG , GUDWXUH &KRS
4
*P
7RLQWHJUDWRU
[ [
Σ
&ODUJH
Figure 15.1.1: Phase alignment concept.
,
Σ
&KRS# I
&KRS# I
δ,
,
Σ
4,
δ2
(UURUGLVSODFHGWRI δ,δ4 δ2 (UURUGLVSODFHGWRI δ,4 δ4, 3URGXFWFHQWHUHG#'& ,4
3$
9PLG &0)%
)URP LQWHJUDWRU _9LQ_
*P
*P
15
Figure 15.1.3: Phase error computation and S.C. integrator.
Figure 15.1.4: Implementation of symbol rotation.
Figure 15.1.5: Phase alignment performance.
Figure 15.1.6: Effective output offset, δ0, of chopper-stabilized multipliers.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
0L[HUV
5RWDWH
/RRS DPS OLILHUV
QRUP 'RZQFRQ FRPSXWH YHUVLRQ
3$
3KDVH ,QWHJUDWRU HUURU
&ORFN VLJQDOV
Figure 15.1.7: Die micrograph.
15
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
, 4
2QFKLS
FRVș VLQș VLQș FRVș ș
, 4
3$
/2
,4
ș
V
5)
GșGW
*
Σ
4,
,
4
, 4
/2 5)
&VPDOO &ODUJH
Figure 15.1.1: Phase alignment concept.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
δ2
(UURUGLVSODFHGWRI δ,δ4 δ2 (UURUGLVSODFHGWRI δ,4 δ4, 3URGXFWFHQWHUHG#'& ,4
Σ
δ,
, &KRS# I 4XDGUDWXUH FKRS# I
4
&KRS# I
Σ Σ
,
, 4
4
4
δ4 $QDORJPXOWLSO\FHOO
Figure 15.1.2: New technique for offset-free analog multiplication.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
,
&KRS
9PLG
,
[ [ 4
4
,
4XDG 4 GUDWXUH &KRS
&KRS
\ \
[\
,R ,R
SELDV
7RV\PERO URWDWLRQ
9PLG
,QWHJUDWRU
7RLQWHJUDWRU
4
4XDG , GUDWXUH &KRS
[ [
I &KRS
,R
[\ \ ,R \
Figure 15.1.3: Phase error computation and S.C. integrator.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
, 4
FRVș VLQș VLQș FRVș FRVș VLQș
7RXSFRQ YHUVLRQ
SELDV
*P 9PLG &0)%
)URP LQWHJUDWRU _9LQ_
*P
*P
Figure 15.1.4: Implementation of symbol rotation.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
Figure 15.1.5: Phase alignment performance.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
Figure 15.1.6: Effective output offset, δ0, of chopper-stabilized multipliers.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
0L[HUV
5RWDWH
/RRS DPS OLILHUV
QRUP 'RZQFRQ FRPSXWH YHUVLRQ
3$
3KDVH ,QWHJUDWRU HUURU
&ORFN VLJQDOV
Figure 15.1.7: Die micrograph.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
15.1
Automatic Phase Alignment for a Fully Integrated CMOS Cartesian Feedback Power Amplifier System
Joel L. Dawson, Thomas H. Lee Department of Electrical Engineering, Stanford University, Palo Alto, CA The need for accurate phase alignment between modulator and demodulator local oscillators (LOs) has frustrated attempts to realize Cartesian feedback in integrated form. Past efforts to solve this problem have resulted in cumbersome implementations not amenable to integration [1]. In this paper we report the first known fully integrated Cartesian feedback linearization system, and describe in detail the automatic phase alignment system that makes it possible. The power amplifier itself, which is integrated on the same die, delivers a maximum power of 14.2dBm at 2GHz into a 50Ω load. Figure 15.1.1 illustrates the principle of the technique, which was first described in [2]. Phase alignment is achieved via a nonlinear dynamic system that is mathematically described as dθ/dt = G(IQ' - QI') = -Grr'sin(∆θ). Variables (I,Q) and (r,θ) are baseband symbols in Cartesian and polar representations, respectively; unprimed coordinates denote symbols as they enter the modulator, primed coordinates denote demodulated symbols. The original prototype described in [2] realized the required rotation by directly phase shifting the modulator LO; substantial power savings result from doing symbol rotation at baseband, as shown here. Regardless, rotation should be performed in the forward path of the Cartesian feedback loop, where the unavoidable artifacts of imperfect rotation are maximally suppressed. The achieved accuracy of phase alignment is limited by errors in computing the sum of products IQ' - QI'. A major source of these errors is offsets in the analog multipliers. Our basic multiplier cell is shown in Fig. 15.1.2 [3]. A mathematically complete description of a multiplier's offset behavior requires at least three quantities: δI and δQ, the offsets attributable to the inputs, and δO, the offset introduced in the current-to-voltage conversion performed at the output of the multiplier. Minimizing these offsets is difficult: one might imagine, for example, some combination of careful, symmetrical layout and a calibration step. We introduce instead the technique shown in Fig. 15.1.2. The underlying idea is to employ chopper stabilization to eliminate (or at least greatly suppress) these multiplier offsets which produce the dominant phase alignment errors in conventional realizations. The critical modifications to the traditional chopping technique are chopping the two inputs in quadrature, and then chopping down at twice the original chopping frequency. To the extent that the quadrature relationship in the chopping clocks is perfect, offsets δI, δQ, and δO are completely circumvented. In Fig. 15.1.3, we show how the phase error calculation and integration are carried out on the fabricated IC. The chopping frequency f0 is 2.5MHz, down chopping occurs at 5MHz, and all clocks are derived from a 20MHz off-chip crystal oscillator. As can be seen in the diagram, a switched-capacitor integrator provides the integration, and two factors motivate this choice over continuous time methods. The first factor is that much of the offset removal shown in Fig. 15.1.2 is wasted if the integrator that follows has a large input-referred offset. Accordingly, an autozeroing switched-capacitor integrator is used1. The second factor is that high speed in the phase alignment system is unnecessary, as the proper phase setting typically evolves on time scales no
• 2003 IEEE International Solid-State Circuits Conference
shorter than those of temperature change, aging, and process variation. A slow integrator is thus appropriate, and easily realized with a slowly clocked S.C. integrator. Its fully differential op-amp draws 524µA, and has a simulated DC gain of 115dB. The unwanted chopping artifacts centered at 2.5MHz and 5MHz are not filtered out. Instead, the integrator is clocked at 39.2kHz, which has the property of aliasing tones at 2.5MHz and 5MHz to π/4 and π/2, respectively, in the z-domain2. As a result, aliasing of these artifacts does not result in DC errors. The chopping clocks’ transitions occur on the rising edge of the 20MHz source, while the integrator clock transitions occur on the falling edge. This ensures that edges of the chopping clocks do not occur at a sampling instant. The chosen means of realizing analog symbol rotation is depicted in Fig. 15.1.4, where four analog multiplier cells form the core of the matrix rotator block. The sinθ input to the rotator block is taken directly from the integrator, while the cosθ input is computed by an analog feedback loop. This loop acts to preserve the 1-norm of the (vsinθ, vcosθ) pair: |vsinθ| + |vcosθ| = Vref, where Vref is set by the resistive divider. This is a departure from [2], where in order to achieve pure rotation without affecting the magnitude of the symbol the 2-norm, |vsinθ|2 + |vcosθ|2 = Vref, was used. Use of the 1-norm was a purely simplifying decision that removed analog squarers from the system. Fortunately, the resultant warping of the symbol magnitude is rejected by the Cartesian feedback loop. For |vsinθ| ≤ Vref, the circuit in Fig. 15.1.4 enables rotations over a range of ±90 degrees. This implementation accounts for 3.1mW of the overall power dissipation. Figure 15.1.5 summarizes the phase regulation of the prototype IC. It is seen that the phase error never exceeds 9 degrees over the full range of disturbances, which is more than adequate to keep the Cartesian feedback loop stable. Figure 15.1.6 shows the offset of the phase error computation circuit in Fig. 15.1.3 referred to the input of the first gain stage. This offset for a chopping frequency of 2.5MHz is 414µV, and here the effectiveness of the chopping strategy is evident: the differential pair of the first gain stage alone has a 1-σ Vt mismatch of 7.8mV. By way of comparison, complete failure of the phase alignment system corresponds to an offset of 4.4mV. The complete IC was fabricated in National's 0.25µm CMOS process. Figure 15.1.7 shows a die micrograph of the chip, which occupies 4.1x4.1mm2. The complete Cartesian feedback linearization system draws 9.5mA from a 2.5-volt supply. All signal paths are fully differential. 1 Its offset is further mitigated by the two preceding gain stages shown in Fig. 15.1.3. 2 Any frequency determined by 4f0/n, where n is an odd integer, will have this property. For this IC, n is 255.
Acknowledgements The authors gratefully acknowledge National Semiconductor for fabrication of the prototype IC. References [1] B. Razavi, RF Microelectronics, Prentice-Hall, Inc., Upper Saddle River, NJ, 1998. [2] J.L. Dawson and T.H. Lee, “Automatic Phase Alignment for High Bandwidth Cartesian Feedback Power Amplifiers,” IEEE Radio and Wireless Conference, pp. 71-74, 2000. [3] G. Han and E. Sanchez-Sinencio, “CMOS Transconductance Multipliers: A Tutorial,” IEEE Transactions on Circuits and Systems-II, vol. 45, no. 12, pp. 1550-1563, December 1998.
0-7803-7707-9/03/$17.00
©2003 IEEE
,
2QFKLS
FRVș VLQș VLQș FRVș ș
4
, 5)
4
/2
,4
ș GșGW
V
*
4XDGUDWXUH FKRS# I
,
4
, 4
/2
&VPDOO
5)
&KRS
9PLG
,
[ [ 4
4
,
4XDG 4 GUDWXUH &KRS
&KRS
\ \
[\
,R ,R
SELDV
\ \
, 4
4
4
δ4 $QDORJPXOWLSO\FHOO
9PLG
, 4
7RV\PERO URWDWLRQ
,QWHJUDWRU
,R
I &KRS
,R
FRVș VLQș VLQș FRVș FRVș VLQș
7RXSFRQ YHUVLRQ
SELDV
[\
Σ
,
Figure 15.1.2: New technique for offset-free analog multiplication.
4
4XDG , GUDWXUH &KRS
4
*P
7RLQWHJUDWRU
[ [
Σ
&ODUJH
Figure 15.1.1: Phase alignment concept.
,
Σ
&KRS# I
&KRS# I
δ,
,
Σ
4,
δ2
(UURUGLVSODFHGWRI δ,δ4 δ2 (UURUGLVSODFHGWRI δ,4 δ4, 3URGXFWFHQWHUHG#'& ,4
3$
9PLG &0)%
)URP LQWHJUDWRU _9LQ_
*P
*P
15
Figure 15.1.3: Phase error computation and S.C. integrator.
Figure 15.1.4: Implementation of symbol rotation.
Figure 15.1.5: Phase alignment performance.
Figure 15.1.6: Effective output offset, δ0, of chopper-stabilized multipliers.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
0L[HUV
5RWDWH
/RRS DPS OLILHUV
QRUP 'RZQFRQ FRPSXWH YHUVLRQ
3$
3KDVH ,QWHJUDWRU HUURU
&ORFN VLJQDOV
Figure 15.1.7: Die micrograph.
15
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
, 4
2QFKLS
FRVș VLQș VLQș FRVș ș
, 4
3$
/2
,4
ș
V
5)
GșGW
*
Σ
4,
,
4
, 4
/2 5)
&VPDOO &ODUJH
Figure 15.1.1: Phase alignment concept.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
δ2
(UURUGLVSODFHGWRI δ,δ4 δ2 (UURUGLVSODFHGWRI δ,4 δ4, 3URGXFWFHQWHUHG#'& ,4
Σ
δ,
, &KRS# I 4XDGUDWXUH FKRS# I
4
&KRS# I
Σ Σ
,
, 4
4
4
δ4 $QDORJPXOWLSO\FHOO
Figure 15.1.2: New technique for offset-free analog multiplication.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
,
&KRS
9PLG
,
[ [ 4
4
,
4XDG 4 GUDWXUH &KRS
&KRS
\ \
[\
,R ,R
SELDV
7RV\PERO URWDWLRQ
9PLG
,QWHJUDWRU
7RLQWHJUDWRU
4
4XDG , GUDWXUH &KRS
[ [
I &KRS
,R
[\ \ ,R \
Figure 15.1.3: Phase error computation and S.C. integrator.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
, 4
FRVș VLQș VLQș FRVș FRVș VLQș
7RXSFRQ YHUVLRQ
SELDV
*P 9PLG &0)%
)URP LQWHJUDWRU _9LQ_
*P
*P
Figure 15.1.4: Implementation of symbol rotation.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
Figure 15.1.5: Phase alignment performance.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
Figure 15.1.6: Effective output offset, δ0, of chopper-stabilized multipliers.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
0L[HUV
5RWDWH
/RRS DPS OLILHUV
QRUP 'RZQFRQ FRPSXWH YHUVLRQ
3$
3KDVH ,QWHJUDWRU HUURU
&ORFN VLJQDOV
Figure 15.1.7: Die micrograph.
• 2003 IEEE International Solid-State Circuits Conference
0-7803-7707-9/03/$17.00
©2003 IEEE
