A High Speed, Low Voltage to High Voltage Level ... - IEEE Xplore
A High speed, Low Voltage to High Voltage Level Shifter in Standard 1.2V 0.13µm CMOS Bert Serneels, Michiel Steyaert and Wim Dehaene Catholic University of Leuven Department ESAT-MICAS Email: bert.serneels, michiel.steyaert, [email protected]
Abstract— The design of a high speed, low voltage to high voltage level shifter in a digital 1.2 V, 0.13µm CMOS technology is presented. The topology uses two differentially switched cascoded transistor ladders. The output signal has an offset of two times the nominal supply voltage of the used technology with respect to the input signal. Oxide stress and hot carrier degradation is minimized since all transistors of the level shifter operate within the voltage limits imposed by the design rules of a mainstream CMOS technology.
nVDD
nVDD
(n-1)VDD VDD
cascode transistors and bias circuit
Mp (n-1)VDD
out
Mn
I. I NTRODUCTION
gnd gnd
While the research on nanometer scale technologies intensively continuous, high voltage design techniques in these technologies are emerging [1]–[3]. The nanometer technologies provide an answer to the growing integration density of VLSI circuits and the low power requirements of complex digital signal processing applications, while the high voltage circuits provide the high voltage driving capability required for power amplifiers, line drivers, etc. Moreover these high voltage design techniques permit full integration of the power interface circuits with the digital circuitry. The objective of high voltage design in standard low voltage technologies is to find the correct operating point so that the voltage across the terminals of the transistors is within the limits of the used technology. This is called the transistors safe operating region. By working in the transistors safe operating region breakdown mechanisms and hot carrier degradation are minimized and reliable operation is guaranteed. A commonly used topology for high voltage circuits in a low voltage technology is the stacking of nMOS and pMOS transistors to form a pushpull output stage [1]–[3]. This structure requires a pre-driver circuit, which generates the pull-up and the pull-down control signals. Figure 1 shows a schematic of such a high voltage driver circuit with the necessary control signals. The dashed rectangle represents the cascode transistors with their gate bias circuit. This circuit ensures that that every cascode transistor is in its safe operating region during operation of the driver. The output of the high voltage driver switches between gnd and n times VDD , the nominal supply voltage of the technology used. The output level is controlled by switching the nMOS and the pMOS transistors Mn and Mp on and off. Therefore the following control signals are necessary: gnd and VDD for the nMOS and (n − 1) times VDD and n times VDD for the pMOS. The control signal for the pMOS is generated by a voltage level shifter. The level shifter converts the low voltage
1-4244-0395-2/06/$20.00 ©2006 IEEE.
668
Fig. 1.
A high voltage driver circuit with its control signals.
control signal of the nMOS to the high voltage control signal for the pMOS with a DC offset of (n − 1) times VDD . Since the level shifter itself operates at high voltage, specialized circuit techniques need to be used to ensure reliable operation. Moreover, it is important that the delay between the low level and the high level control signal is small enough to minimize the short circuit current in the high voltage driver. Level shift circuit topologies in low voltage technologies found in literature nowadays suffer from large delays between input and output and are not able to drive capacitive loads in an efficient way. This can lead to an excess power dissipation in the following circuits. Moreover, they are restricted to an output offset of one VDD limiting the supply voltage of the high voltage driver to only two times VDD . This paper describes a new high speed, low voltage to high voltage level shift circuit in a digital low voltage technology with an offset of two times VDD . First, a standard level shift topology is discussed. In the next section, the presented level shift topology is described and a comparison with the standard topology is made. Then the methodology to increase the output voltage offset of the presented level shift circuit is explained, followed by the simulation results. Finally some conclusions are drawn. II. P RIOR S OLUTIONS A standard level shifter is shown in figure 2. This circuit gives an offset of one VDD . It consists of two branches of cascoded transistors that are differentially switched. The cascoded transistors keep the voltages across the terminals of the transistors within the technology limits.
2VDD
2VDD
MR4
ML4
Cup1
nL1
ML1
in
gnd
5
4
3 2 Time [ns]
1
0
gnd
Fig. 3. Fig. 2.
1
0
MR1
gnd
1.5
0.5
MR2
nR1
I1
CL VDD
Cup2 nR2
VDD
Voltage [V]
MR3 nL2
ML2
in out
2
out
nL3
ML3 VDD
2.5
Input-output characteristic of the standard level shift circuit.
A standard level shift circuit. 2VDD
The working principle is as follows: Assume the input in high. Transistor ML1 switches on and node nL1 is pulled down to gnd. At the same time inverter I1 switches transistor MR1 off and node nR1 is charged till VDD . Since the gate voltages of the transistors ML2 and MR2 are fixed to VDD , the transistors ML2 and MR2 are respectively switched on and off. Therefore, the node nL2 is pulled down to gnd and node nR2 is charged to the maximum voltage of two times VDD . The voltage on the nodes nL3 and out will not drop below VDD since the gate voltage of the transistors ML3 and MR3 are also fixed at VDD . The cross coupled transistors ML4 and MR4 operate like a current sense circuit. As a consequence, the node nL3 will be discharged till VDD + |VT p |. This will switch on transistor MR4 which charges the output node out till two times VDD and switches transistor ML4 off. The same reasoning can be used for when the input in is low. The two capacitors Cup1 and Cup2 respectively couple the gates of the transistors ML1 and MR1 with the gates of the transistors ML4 and MR4 . If the input square wave has an amplitude of VDD , the voltage on the nodes nL3 and out couples up or down with a factor ∆V : ∆V =
1
1+
Cpar Cup
VDD
(1)
Cpar is the parasitic capacitance on node out for the capacitor Cup1 or on node nL3 for the capacitor Cup2 . The advantage of this capacitive coupling is that the cross coupled pair ML4 and MR4 switches faster from one state to the other. Without the coupling capacitors the delay of the circuit increases significantly. Figure 3 shows the input-output characteristic of this topology. An input square wave with a frequency of 1 GHz is applied to transistor ML1 and to transistor MR1 through inverter I1 . The output is loaded with a capacitance of 200f F . The values of the coupling capacitors were arbitrarely set at 4pF to create a sufficiently large ∆V and to minimize the delay. The main problem of this circuit remains the driving capability. The output can only be discharged by the pMOS transistor MR3 . This means that the discharging of the output capacitance is sublinear [4] and that there is a threshold loss at the output, which is clearly visible in figure 3. Moreover,
669
ML4 nL3
2VDD I2 VDD
2VDD
MR4 out
CL VDD
in
ML1 gnd
Fig. 4.
VDD
Cup2
VDD I1 gnd
MR1 gnd
A schematic of the presented level shift circuit.
according to (1) the ∆V correspondig with capacitor Cup1 decreases, since the output load, CL adds with the parasitic capacitance on the output node. Therefore, Cup1 should be increased, which in turn increases the input capacitance of the level shift circuit. III. S YSTEM D ESCRIPTION Figure 4 shows a schematic of the presented level shift circuit. Compared with figure 2, the capacitor Cup1 is omited and an inverter between the gates of the transistors MR4 and ML4 is added. Now, only the gates of the transistors MR1 and MR4 couple up or down with ∆V (1). If ∆V is larger than the switching threshold (VT ) of inverter I2 , the gate voltage of transistor ML4 immediately changes with the input signal and thereby, increases also the switching speed of transistor MR4 . Actually, the inverter improves the function of Cup1 without increasing the input capacitance. Another advantage is that the inverter I2 helps to charge and discharge the output capacitor and hence can be scaled accordingly. The threshold loss at the output is now dissapeared, since the discharging of the ouput capacitance now largely occurs by the nMOS transistor of the inverter I2 [4]. Figure 5 shows the input-output characteristic of the presented level shift circuit. A 1 GHz input square wave is applied to the circuit. Transistor sizes, inverter scaling factors, output load and pull up capacitance are the same as in the standard level shift circuit. Only inverter I2 is now scaled to drive the output load. It can clearly be seen that the threshold loss at the output has dissapeared thanks to the addition of inverter I2 .
2.5
in out
Voltage [V]
2 1.5 1 0.5 0
0
Fig. 5.
1
3 2 Time [ns]
5
4
Input-output characteristic of the presented level shift circuit. TABLE I D ELAY COMPARISON OF THE DIFFERENT TOPOLOGIES
standard level shifter this work
Tdlh [ps] 42 81
Tdhl [ps] 70 76
τr [ps] 106 57
τf [ps] 102 54
One can also notice the steep edges of the input signal, which proves the low input capacitance compared to the topology of figure 2. Table I gives a comparison of the delays and the rise and fall times of the two topologies. The time from a half VDD point of the input to a VDD /2 + Vof f point of the output is defined as a delay, Tdlh , in the charging case. In the discharging case, the delay Tdhl is defined in the same way. Vof f stands for the offset voltage of the level shift circuit. The rise and fall times, τr and τf are defined to be the time between the 10% VDD + Vof f and 90% VDD + Vof f points of the output. For the standard level shift circuit a voltage level of 10% VDD + Vof f is not met. Therefore the 10% VDD + Vlow point is taken. Vlow is the lowest voltage the topology can reach. The delay in the discharging case of the presented level shift circuit is similar to the delay of the standard level shift circuit. In the charging case, a smaller delay for the standard level shift circuit is seen. This is due to the fact that the output node is never completely discharged because of the threshold loss. The rise and fall times of the presented circuit are halved with respect to the standard level shift circuit, nevertheless its larger output swing. The inverter I2 now takes care of the charging and discharging of the output load. In this way, a part of the tapered buffer to drive the output transistor of the push-pull stage can be integrated in the level shift circuit. An advantage of the halved rise and fall times is the reduction of the short circuit dissipation in the tapered buffer driven by the level shift circuit. According to [5], the short circuit dissipation of an inverter is linearely proportional with the rise and fall time of the input signal. IV. O UTPUT VOLTAGE O FFSET Until now, only level shift circuits with an offset of one VDD were discussed. These allow only a maximum of 2VDD power supply driver circuits. In this section the methodology
670
to increase the output voltage offset to two times VDD is described, allowing 3VDD driver circuits. The starting point is the presented level shift circuit of figure 4. By adding extra cascode transistors in the transistor ladder structure, the supply voltage and as a consequence the output voltage offset can be increased. Figure 6 shows the resulting level shift circuit with an output voltage offset of two times VDD . The working principle of this level shift topology has been explained in the previous sections, so the focus will be set on the behaviour of the transistor ladders during operation. Consider the case where the input in changes from gnd to VDD . Transistor ML1 switches on and from section III it is known that the gate of transistor ML6 almost immediately changes with the input signal. This means that transistor ML6 switches off. As a consequence the nodes nL1 and nL7 are respectively discharged to gnd and 2VDD + |VT p |. Since the gate of transistor ML2 is set at a fixed bias voltage of VDD and the gate of transistor ML5 is set at a fixed bias voltage of 2VDD , the transistors ML2 and ML5 respectively switch on and off. The on-state of transistor ML2 causes node nL2 to be discharged to gnd. In order to prevent the oxide breakdown of transistor ML3 , its gate voltage needs to be biased at VDD . This is done by transistor MLB1 which was switched on during the discharging of node nL2 . The offstate of transistor ML5 causes node nL6 to be discharged to VDD + |VT p |, since the gate bias voltage of transistor ML4 was set at VDD by transistor MLB1 . This will switch off transistor ML4 and prevents transistor MLB2 from further charging the gates of transistors ML3 and ML4 till 2VDD . The diode configured transistors MDn and MDp are added between the cascode transistors ML3 and ML4 . They provide a voltage headroom to set off the transient voltage peaks across the cascode transistors in order to ensure reliable operation. In the same way the switching principle of the transistors in the right transistor ladder network can be explained. Figure 7 shows a transient simulation, at 1 GHz, of the drain-source, gate-source and gate-drain voltages of the transistors in the left transistor ladder network. Since all the voltages across the terminals of the transistors are within the voltage limit of one VDD , breakdown of the gate oxides is prevented and hot carrier generation is minimized. The same simulation results are obtained for the transistors in the right transistor ladder network. V. S IMULATION R ESULTS The simulation result of the presented level shift circuit with an output voltage offset of two times VDD is shown in figure 8. A 1 GHz square wave with gnd and VDD as low and high voltage levels is applied at the input. Transistor sizes of the cascoded transistors in the ladder networks, scaling factors, pull-up capacitance and output load are unaltered with respect to the previous topology. The delays, Tdlh and Tdhl , are respectively 81ps and 75ps. The rise and fall times are 65ps and 57ps. These results are almost the same compared to the results of the presented level shift circuit with an output voltage offset of one VDD from table I. This shows that the
3VDD
3VDD 3VDD
nL6
nR6
ML4
MR4
nL5
nR5
Cup2
MDn
-0.2
0.8 0.6 0.4
nL2
nR2
ML2
MR2
-1
0
-1.2
Time [ns]
Time [ns]
MRB1 VDD
ML4 MDp
ML6 ML5
ML3 MDn
ML1 ML2
(a) Drain-Source Voltage
nR1
I1
MR1
delay of the level shift circuit does not depend on the speed of charging and/or discharging all internal nodes of the cascoded transistors. However, the delay mainly depends now on the coupling between the nMOS and the pMOS input by Cup2 and the speed of the inverters I1 and I2 . The level shift circuit with an output offset of two times VDD is implemented in a mainstream 1.2V, 0.13µm triple well CMOS technology. The triple well process permits the connection of the source of every transistor in the circuit with its bulk without substrate losses. This guarantees a gate-bulk voltage within the nominal operating conditions. VI. C ONCLUSIONS A high speed, low voltage to high voltage level shift circuit in a standard 1.2 V, 0.13µm CMOS technology was presented. An ouput voltage offset of two times the nominal supply voltage was reached using only low voltage devices allowing full integration of high voltage circuits in a digital design. Reliability is guaranteed since the voltages across the terminals of every transistor stay below the nominal supply voltage during operation. The level shift circuit is optimized for driving capacitive loads which decreases the short circuit power consumption of the complete high voltage circuit.
0
1
-0.2
0.8 0.6 0.4
-0.4 -0.6 -0.8
0.2
-1
0
-1.2
0 0.5 1 1.5 2 2.5 3
0 0.5 1 1.5 2 2.5 3
Time [ns]
Time [ns]
(b) Gate-Source Voltage
1
1
0.5
0.5
0
0
-0.5
-0.5
-1
-1
0 0.5 1 1.5 2 2.5 3
0 0.5 1 1.5 2 2.5 3
Time [ns]
Time [ns]
ML3
ML1 ML2
Fig. 7.
Simulation of the Vds , Vgs and Vgd of ML1 to ML6
in out
3.5
671
ML4
ML6 ML5
(c) Gate-Drain Voltage
R EFERENCES
3
Voltage [V]
[1] A.-J. Annema, G. Geelen, and P. de Jong, “5.5 V I/O in a 2.5 V 0.25µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 528– 538, 2001. [2] B. Serneels, T. Piessens, M. Steyaert, and W. Dehaene, “A high-voltage output driver in a standard 2.5V 0.25µm CMOS technology,” in ISSCC Digest of Technical Papers, Feb. 2004, pp. 146–147. [3] B. Serneels, M. Steyaert, and W. Dehaene, “A 5.5V line driver in a standard 1.2V 0.13µm CMOS technology,” in Proceedings European Solid-State Circuits Conference, Sept. 2005, pp. 303–306. [4] J. M. Rabaey, Digital Integrated Circuits, A Design Perspective. PrenticeHall, Inc., 1996. [5] H. J. Veendrick, “Short circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits, vol. 19, no. 4, pp. 468–473, Aug. 1984.
ML4 MDp
ML6 ML5
ML3 MDn
ML1 ML2
Voltage [V]
Fig. 6. A schematic of the presented level shift circuit with an offset of two times VDD .
1.2
Voltage [V]
gnd Voltage [V]
gnd
0 0.5 1 1.5 2 2.5 3
0 0.5 1 1.5 2 2.5 3
Voltage [V]
VDD
-0.4 -0.6 -0.8
0.2
MDn MR3
gnd
0
1
nR4
ML3
ML1
1.2
nR3
nL3
in
2VDD MRB2
MDp
nL4
nL1
Voltage [V]
CL
MR5
MDp
MLB1 VDD
out
2VDD
ML5
2VDD MLB2
MR6
I2
nL7
Voltage [V]
ML6
2.5 2 1.5 1 0.5 0
0
1
3 2 Time [ns]
4
5
Fig. 8. Input-output characteristic of the presented level shift circuit with an output offset voltage of two times VDD .
Abstract— The design of a high speed, low voltage to high voltage level shifter in a digital 1.2 V, 0.13µm CMOS technology is presented. The topology uses two differentially switched cascoded transistor ladders. The output signal has an offset of two times the nominal supply voltage of the used technology with respect to the input signal. Oxide stress and hot carrier degradation is minimized since all transistors of the level shifter operate within the voltage limits imposed by the design rules of a mainstream CMOS technology.
nVDD
nVDD
(n-1)VDD VDD
cascode transistors and bias circuit
Mp (n-1)VDD
out
Mn
I. I NTRODUCTION
gnd gnd
While the research on nanometer scale technologies intensively continuous, high voltage design techniques in these technologies are emerging [1]–[3]. The nanometer technologies provide an answer to the growing integration density of VLSI circuits and the low power requirements of complex digital signal processing applications, while the high voltage circuits provide the high voltage driving capability required for power amplifiers, line drivers, etc. Moreover these high voltage design techniques permit full integration of the power interface circuits with the digital circuitry. The objective of high voltage design in standard low voltage technologies is to find the correct operating point so that the voltage across the terminals of the transistors is within the limits of the used technology. This is called the transistors safe operating region. By working in the transistors safe operating region breakdown mechanisms and hot carrier degradation are minimized and reliable operation is guaranteed. A commonly used topology for high voltage circuits in a low voltage technology is the stacking of nMOS and pMOS transistors to form a pushpull output stage [1]–[3]. This structure requires a pre-driver circuit, which generates the pull-up and the pull-down control signals. Figure 1 shows a schematic of such a high voltage driver circuit with the necessary control signals. The dashed rectangle represents the cascode transistors with their gate bias circuit. This circuit ensures that that every cascode transistor is in its safe operating region during operation of the driver. The output of the high voltage driver switches between gnd and n times VDD , the nominal supply voltage of the technology used. The output level is controlled by switching the nMOS and the pMOS transistors Mn and Mp on and off. Therefore the following control signals are necessary: gnd and VDD for the nMOS and (n − 1) times VDD and n times VDD for the pMOS. The control signal for the pMOS is generated by a voltage level shifter. The level shifter converts the low voltage
1-4244-0395-2/06/$20.00 ©2006 IEEE.
668
Fig. 1.
A high voltage driver circuit with its control signals.
control signal of the nMOS to the high voltage control signal for the pMOS with a DC offset of (n − 1) times VDD . Since the level shifter itself operates at high voltage, specialized circuit techniques need to be used to ensure reliable operation. Moreover, it is important that the delay between the low level and the high level control signal is small enough to minimize the short circuit current in the high voltage driver. Level shift circuit topologies in low voltage technologies found in literature nowadays suffer from large delays between input and output and are not able to drive capacitive loads in an efficient way. This can lead to an excess power dissipation in the following circuits. Moreover, they are restricted to an output offset of one VDD limiting the supply voltage of the high voltage driver to only two times VDD . This paper describes a new high speed, low voltage to high voltage level shift circuit in a digital low voltage technology with an offset of two times VDD . First, a standard level shift topology is discussed. In the next section, the presented level shift topology is described and a comparison with the standard topology is made. Then the methodology to increase the output voltage offset of the presented level shift circuit is explained, followed by the simulation results. Finally some conclusions are drawn. II. P RIOR S OLUTIONS A standard level shifter is shown in figure 2. This circuit gives an offset of one VDD . It consists of two branches of cascoded transistors that are differentially switched. The cascoded transistors keep the voltages across the terminals of the transistors within the technology limits.
2VDD
2VDD
MR4
ML4
Cup1
nL1
ML1
in
gnd
5
4
3 2 Time [ns]
1
0
gnd
Fig. 3. Fig. 2.
1
0
MR1
gnd
1.5
0.5
MR2
nR1
I1
CL VDD
Cup2 nR2
VDD
Voltage [V]
MR3 nL2
ML2
in out
2
out
nL3
ML3 VDD
2.5
Input-output characteristic of the standard level shift circuit.
A standard level shift circuit. 2VDD
The working principle is as follows: Assume the input in high. Transistor ML1 switches on and node nL1 is pulled down to gnd. At the same time inverter I1 switches transistor MR1 off and node nR1 is charged till VDD . Since the gate voltages of the transistors ML2 and MR2 are fixed to VDD , the transistors ML2 and MR2 are respectively switched on and off. Therefore, the node nL2 is pulled down to gnd and node nR2 is charged to the maximum voltage of two times VDD . The voltage on the nodes nL3 and out will not drop below VDD since the gate voltage of the transistors ML3 and MR3 are also fixed at VDD . The cross coupled transistors ML4 and MR4 operate like a current sense circuit. As a consequence, the node nL3 will be discharged till VDD + |VT p |. This will switch on transistor MR4 which charges the output node out till two times VDD and switches transistor ML4 off. The same reasoning can be used for when the input in is low. The two capacitors Cup1 and Cup2 respectively couple the gates of the transistors ML1 and MR1 with the gates of the transistors ML4 and MR4 . If the input square wave has an amplitude of VDD , the voltage on the nodes nL3 and out couples up or down with a factor ∆V : ∆V =
1
1+
Cpar Cup
VDD
(1)
Cpar is the parasitic capacitance on node out for the capacitor Cup1 or on node nL3 for the capacitor Cup2 . The advantage of this capacitive coupling is that the cross coupled pair ML4 and MR4 switches faster from one state to the other. Without the coupling capacitors the delay of the circuit increases significantly. Figure 3 shows the input-output characteristic of this topology. An input square wave with a frequency of 1 GHz is applied to transistor ML1 and to transistor MR1 through inverter I1 . The output is loaded with a capacitance of 200f F . The values of the coupling capacitors were arbitrarely set at 4pF to create a sufficiently large ∆V and to minimize the delay. The main problem of this circuit remains the driving capability. The output can only be discharged by the pMOS transistor MR3 . This means that the discharging of the output capacitance is sublinear [4] and that there is a threshold loss at the output, which is clearly visible in figure 3. Moreover,
669
ML4 nL3
2VDD I2 VDD
2VDD
MR4 out
CL VDD
in
ML1 gnd
Fig. 4.
VDD
Cup2
VDD I1 gnd
MR1 gnd
A schematic of the presented level shift circuit.
according to (1) the ∆V correspondig with capacitor Cup1 decreases, since the output load, CL adds with the parasitic capacitance on the output node. Therefore, Cup1 should be increased, which in turn increases the input capacitance of the level shift circuit. III. S YSTEM D ESCRIPTION Figure 4 shows a schematic of the presented level shift circuit. Compared with figure 2, the capacitor Cup1 is omited and an inverter between the gates of the transistors MR4 and ML4 is added. Now, only the gates of the transistors MR1 and MR4 couple up or down with ∆V (1). If ∆V is larger than the switching threshold (VT ) of inverter I2 , the gate voltage of transistor ML4 immediately changes with the input signal and thereby, increases also the switching speed of transistor MR4 . Actually, the inverter improves the function of Cup1 without increasing the input capacitance. Another advantage is that the inverter I2 helps to charge and discharge the output capacitor and hence can be scaled accordingly. The threshold loss at the output is now dissapeared, since the discharging of the ouput capacitance now largely occurs by the nMOS transistor of the inverter I2 [4]. Figure 5 shows the input-output characteristic of the presented level shift circuit. A 1 GHz input square wave is applied to the circuit. Transistor sizes, inverter scaling factors, output load and pull up capacitance are the same as in the standard level shift circuit. Only inverter I2 is now scaled to drive the output load. It can clearly be seen that the threshold loss at the output has dissapeared thanks to the addition of inverter I2 .
2.5
in out
Voltage [V]
2 1.5 1 0.5 0
0
Fig. 5.
1
3 2 Time [ns]
5
4
Input-output characteristic of the presented level shift circuit. TABLE I D ELAY COMPARISON OF THE DIFFERENT TOPOLOGIES
standard level shifter this work
Tdlh [ps] 42 81
Tdhl [ps] 70 76
τr [ps] 106 57
τf [ps] 102 54
One can also notice the steep edges of the input signal, which proves the low input capacitance compared to the topology of figure 2. Table I gives a comparison of the delays and the rise and fall times of the two topologies. The time from a half VDD point of the input to a VDD /2 + Vof f point of the output is defined as a delay, Tdlh , in the charging case. In the discharging case, the delay Tdhl is defined in the same way. Vof f stands for the offset voltage of the level shift circuit. The rise and fall times, τr and τf are defined to be the time between the 10% VDD + Vof f and 90% VDD + Vof f points of the output. For the standard level shift circuit a voltage level of 10% VDD + Vof f is not met. Therefore the 10% VDD + Vlow point is taken. Vlow is the lowest voltage the topology can reach. The delay in the discharging case of the presented level shift circuit is similar to the delay of the standard level shift circuit. In the charging case, a smaller delay for the standard level shift circuit is seen. This is due to the fact that the output node is never completely discharged because of the threshold loss. The rise and fall times of the presented circuit are halved with respect to the standard level shift circuit, nevertheless its larger output swing. The inverter I2 now takes care of the charging and discharging of the output load. In this way, a part of the tapered buffer to drive the output transistor of the push-pull stage can be integrated in the level shift circuit. An advantage of the halved rise and fall times is the reduction of the short circuit dissipation in the tapered buffer driven by the level shift circuit. According to [5], the short circuit dissipation of an inverter is linearely proportional with the rise and fall time of the input signal. IV. O UTPUT VOLTAGE O FFSET Until now, only level shift circuits with an offset of one VDD were discussed. These allow only a maximum of 2VDD power supply driver circuits. In this section the methodology
670
to increase the output voltage offset to two times VDD is described, allowing 3VDD driver circuits. The starting point is the presented level shift circuit of figure 4. By adding extra cascode transistors in the transistor ladder structure, the supply voltage and as a consequence the output voltage offset can be increased. Figure 6 shows the resulting level shift circuit with an output voltage offset of two times VDD . The working principle of this level shift topology has been explained in the previous sections, so the focus will be set on the behaviour of the transistor ladders during operation. Consider the case where the input in changes from gnd to VDD . Transistor ML1 switches on and from section III it is known that the gate of transistor ML6 almost immediately changes with the input signal. This means that transistor ML6 switches off. As a consequence the nodes nL1 and nL7 are respectively discharged to gnd and 2VDD + |VT p |. Since the gate of transistor ML2 is set at a fixed bias voltage of VDD and the gate of transistor ML5 is set at a fixed bias voltage of 2VDD , the transistors ML2 and ML5 respectively switch on and off. The on-state of transistor ML2 causes node nL2 to be discharged to gnd. In order to prevent the oxide breakdown of transistor ML3 , its gate voltage needs to be biased at VDD . This is done by transistor MLB1 which was switched on during the discharging of node nL2 . The offstate of transistor ML5 causes node nL6 to be discharged to VDD + |VT p |, since the gate bias voltage of transistor ML4 was set at VDD by transistor MLB1 . This will switch off transistor ML4 and prevents transistor MLB2 from further charging the gates of transistors ML3 and ML4 till 2VDD . The diode configured transistors MDn and MDp are added between the cascode transistors ML3 and ML4 . They provide a voltage headroom to set off the transient voltage peaks across the cascode transistors in order to ensure reliable operation. In the same way the switching principle of the transistors in the right transistor ladder network can be explained. Figure 7 shows a transient simulation, at 1 GHz, of the drain-source, gate-source and gate-drain voltages of the transistors in the left transistor ladder network. Since all the voltages across the terminals of the transistors are within the voltage limit of one VDD , breakdown of the gate oxides is prevented and hot carrier generation is minimized. The same simulation results are obtained for the transistors in the right transistor ladder network. V. S IMULATION R ESULTS The simulation result of the presented level shift circuit with an output voltage offset of two times VDD is shown in figure 8. A 1 GHz square wave with gnd and VDD as low and high voltage levels is applied at the input. Transistor sizes of the cascoded transistors in the ladder networks, scaling factors, pull-up capacitance and output load are unaltered with respect to the previous topology. The delays, Tdlh and Tdhl , are respectively 81ps and 75ps. The rise and fall times are 65ps and 57ps. These results are almost the same compared to the results of the presented level shift circuit with an output voltage offset of one VDD from table I. This shows that the
3VDD
3VDD 3VDD
nL6
nR6
ML4
MR4
nL5
nR5
Cup2
MDn
-0.2
0.8 0.6 0.4
nL2
nR2
ML2
MR2
-1
0
-1.2
Time [ns]
Time [ns]
MRB1 VDD
ML4 MDp
ML6 ML5
ML3 MDn
ML1 ML2
(a) Drain-Source Voltage
nR1
I1
MR1
delay of the level shift circuit does not depend on the speed of charging and/or discharging all internal nodes of the cascoded transistors. However, the delay mainly depends now on the coupling between the nMOS and the pMOS input by Cup2 and the speed of the inverters I1 and I2 . The level shift circuit with an output offset of two times VDD is implemented in a mainstream 1.2V, 0.13µm triple well CMOS technology. The triple well process permits the connection of the source of every transistor in the circuit with its bulk without substrate losses. This guarantees a gate-bulk voltage within the nominal operating conditions. VI. C ONCLUSIONS A high speed, low voltage to high voltage level shift circuit in a standard 1.2 V, 0.13µm CMOS technology was presented. An ouput voltage offset of two times the nominal supply voltage was reached using only low voltage devices allowing full integration of high voltage circuits in a digital design. Reliability is guaranteed since the voltages across the terminals of every transistor stay below the nominal supply voltage during operation. The level shift circuit is optimized for driving capacitive loads which decreases the short circuit power consumption of the complete high voltage circuit.
0
1
-0.2
0.8 0.6 0.4
-0.4 -0.6 -0.8
0.2
-1
0
-1.2
0 0.5 1 1.5 2 2.5 3
0 0.5 1 1.5 2 2.5 3
Time [ns]
Time [ns]
(b) Gate-Source Voltage
1
1
0.5
0.5
0
0
-0.5
-0.5
-1
-1
0 0.5 1 1.5 2 2.5 3
0 0.5 1 1.5 2 2.5 3
Time [ns]
Time [ns]
ML3
ML1 ML2
Fig. 7.
Simulation of the Vds , Vgs and Vgd of ML1 to ML6
in out
3.5
671
ML4
ML6 ML5
(c) Gate-Drain Voltage
R EFERENCES
3
Voltage [V]
[1] A.-J. Annema, G. Geelen, and P. de Jong, “5.5 V I/O in a 2.5 V 0.25µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 528– 538, 2001. [2] B. Serneels, T. Piessens, M. Steyaert, and W. Dehaene, “A high-voltage output driver in a standard 2.5V 0.25µm CMOS technology,” in ISSCC Digest of Technical Papers, Feb. 2004, pp. 146–147. [3] B. Serneels, M. Steyaert, and W. Dehaene, “A 5.5V line driver in a standard 1.2V 0.13µm CMOS technology,” in Proceedings European Solid-State Circuits Conference, Sept. 2005, pp. 303–306. [4] J. M. Rabaey, Digital Integrated Circuits, A Design Perspective. PrenticeHall, Inc., 1996. [5] H. J. Veendrick, “Short circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits, vol. 19, no. 4, pp. 468–473, Aug. 1984.
ML4 MDp
ML6 ML5
ML3 MDn
ML1 ML2
Voltage [V]
Fig. 6. A schematic of the presented level shift circuit with an offset of two times VDD .
1.2
Voltage [V]
gnd Voltage [V]
gnd
0 0.5 1 1.5 2 2.5 3
0 0.5 1 1.5 2 2.5 3
Voltage [V]
VDD
-0.4 -0.6 -0.8
0.2
MDn MR3
gnd
0
1
nR4
ML3
ML1
1.2
nR3
nL3
in
2VDD MRB2
MDp
nL4
nL1
Voltage [V]
CL
MR5
MDp
MLB1 VDD
out
2VDD
ML5
2VDD MLB2
MR6
I2
nL7
Voltage [V]
ML6
2.5 2 1.5 1 0.5 0
0
1
3 2 Time [ns]
4
5
Fig. 8. Input-output characteristic of the presented level shift circuit with an output offset voltage of two times VDD .
