A low-power low-voltage MOSFET-only voltage reference - IEEE Xplore
A LOW-POWER LOW-VOLTAGE MOSFET-ONLY VOLTAGE REFERENCE F. Bedeschi1, E. Bonizzoni2, A. Fantini2, C. Resta3, and G. Torelli2 1
STMicroelectronics, Memory Products Group R&D, via Olivetti, 2 - 20041 Agrate Brianza, Italy 2 Department of Electronics, University of Pavia, via Ferrata, 1 - 27100 Pavia, Italy 3 Studio di Microelettronica, STMicroelectronics, via Ferrata, 1 - 27100 Pavia, Italy
efficiency, thereby allowing lower power consumption and faster programming. A typical value of the bulk bias voltage for this purpose is on the order of –1.4 V.
ABSTRACT A low-power low-voltage MOSFET-only voltage reference featuring very good temperature stability and referred to the positive power supply is proposed. It compensates for the temperature dependence of a gate-tosource voltage of an MOS transistor working in the weak inversion region with a proportional-to-absolutetemperature voltage generated by a pair of MOS devices operating in the same region. The circuit, designed for a 0.35-m (0.18-m in the memory array) CMOS Flash memory technology, can operate with a supply voltage as low as 1 V and draws a current of 3 A. The simulated variation of the reference voltage is within 0.2% over the range from –20 to 80 ºC.
Fig. 1 – Negative voltage regulator topology.
A negative voltage can be obtained by using the regulator topology depicted in Fig. 1, where the operational amplifier (op-amp) is operated from a positive (Vdd) and a negative (–Vss) power supply (the latter is provided by an on-chip negative charge pump voltage multiplier). The voltage V neg turns out to be Vr(1 + R2/R1) – VddR2/R1, which shows a large dependence on Vdd as generally R2/R1 is larger than unit. To limit the sensitivity of the generated voltage to V dd variations, a good choice is using a reference voltage negative to the positive supply V dd, namely setting Vr = Vdd + Vref (where Vref has a negative value, as is clear from Fig. 1). This way, V neg can be expressed as V dd + Vref(1 + R2/R1), which reduces the output voltage dependence on Vdd by a factor of R2/R1. In this paper, a low-power, low-voltage, MOSFET-only voltage reference negative to the power supply is proposed. This scheme, which is based on a current-mode approach, can operate with a supply voltage as low as 1 V, and draws a current of 3 A. Circuit design has been optimized for a p-substrate 0.35-m (0.18-m in the memory array) CMOS Flash technology. Moreover, design considerations regarding some critical aspects in the design of voltage references based on subthreshold MOS transistors are presented.
1. INTRODUCTION Voltage references are a key element in a number of integrated applications, including analog-to-digital and digital-to-analog converters, signal processing, and voltage regulators. The most widely used schemes of integrated voltage references with low temperature dependence are based on the bandgap approach. Several bandgap voltage references [1] have been implemented in bipolar and CMOS technology, where they achieve high levels of accuracy and stability. Recently, requirements of low-power and low-voltage devices are more and more vital as a consequence of the technology scaling down and the widespread applications of portable equipment (such as cellular phones, notebooks, personal data assistants, audio players, digital cameras, portable medical diagnosis systems, etc.). In voltage reference design, the above requirements can be easier met by using fully CMOS circuits. In particular, the use of MOS transistors working in the subthreshold region (hereinafter referred to as subthreshold MOS transistors) dramatically reduces power consumption, and also leads to silicon area saving [2-5]. Typically, bandgap voltage references provide an output voltage referred to ground. However, in some applications, a stable voltage referred to the positive supply V dd is desirable. For instance, Flash memories require high negative gate voltages for the erase operation [6]. In addition, recently, negative-bulk programming [7] has been demonstrated to increase hot-electron injection
;,(((
2. CIRCUIT DESCRIPTION The operating principle of the proposed voltage reference is depicted in Fig. 2. A current-mode approach has been adopted to meet low-voltage requirements. The block
,
,6&$6
PTAT-source generates a voltage proportional to absolute temperature (PTAT) and converts it into a current I R1 by means of resistor R1. The block IVSG generates a current IR2 by forcing the source-to-gate voltage of a subthreshold PMOS transistor through resistor R 2. This voltage decreases linearly with temperature, as will be explained in detail in Section 2.2. The above currents IR1 and I R2 are summed and are then converted into a voltage V ref by means of resistor R3. The scaling factors R3/R1 and R 3/R2 are chosen so as to minimize the temperature dependence of the obtained voltage Vref. R 1, R 2, and R 3 are matched resistors and, hence, their temperature dependence contributions ideally cancel out.
Fig. 3 – Circuit scheme of block PTAT-source.
2.2. IVSG and I-V converter The circuit schemes of blocks IVGS [4, 5] and I-V converter are shown in Fig. 4. The bias current IB is provided by mirroring the current flowing through resistor R1 in the PTAT-source circuit depicted in Fig. 3. Since M7 (which is identical to M 6) operates in weak inversion, I B can be approximated as a fixed bias current, thanks to the drain current logarithmic compression given by a subthreshold MOS device [5]. The source-to-gate voltage of device M 7 shows the following behaviour with temperature [5]:
Fig. 2 – Basic principle of the proposed voltage reference.
2.1. PTAT-source The circuit scheme of the block PTAT-source [2, 3] is shown in Fig. 3. To achieve a PTAT voltage drop across resistor R1, transistors M 5 and M 6 must operate in weak inversion. Assuming zero source-to-body voltage, their I-V characteristic can be described as follows
W I D = I D0 e L
VSG Vth nVT
V SD 1 e VT
(1)
where I D0 is the characteristic current, V T is the thermal voltage, n is the slope factor, and symbols VSG, VSD, Vth, W, and L have their usual meaning. The aspect ratios of transistors M3 and M4 were chosen so as to operate these devices in strong inversion, thus ensuring the best matching performance [8]. Considering that devices M 3 and M 4 are identical, the voltage drop across resistor R 1 turns out to be: S VR1 = nVT ln 5 (2) S6 where Si is the aspect ratio (W/L) i of the i-th transistor. The current through device M4 is therefore I R1 = V R1/R1. Device M5 resides in a separate well connected to its source, thus providing zero source-to-body voltage. In this way, M5 and M 6 operate in the same bias conditions, which ensure best matching. Transistors M 1 and M 2 and capacitor C 1 realize a conventional start-up circuit.
,
T VSG (T ) VSG (T r ) + KT + VSG (T r ) Vth (T r ) 1 (3) Tr
[
]
where Tr is a reference temperature equal to 300 K and KT is a positive constant related to the temperature variation of the threshold voltage (typical value: a few hundreds mV). In the subthreshold region, VSG(Tr) – |Vth(Tr)| has a negative value and the source-to-gate voltage of M 7 decreases linearly with increasing temperature for any fixed drain current. This source-to-gate voltage is forced across resistor R 2, and, hence, the current IM9 through M 9 is I R2S9/S10 = (V SG7/R2)S9/S10, where, again, S i is the aspect ratio of transistor Mi. The currents IR1 and I M9 generated by the block PTATsource and IVSG are forced through resistor R3 by means of devices M11 and M 12, which are identical to M4 and M 9, respectively, thus giving rise to a voltage Vref equal to
nV S V S Vref = R3 T ln 5 + SG7 9 R1 S6 R2 S10
(4)
Considering the ratio m between the absolute value of the negative temperature coefficient of V SG7 and the positive temperature coefficient of the thermal voltage VT:
VSG 7 T m= VT T
= Tr
VSG7 T
Tr
KB q
(5)
where K B is the Boltzmann constant and q the electron charge, first-order compensation of the reference voltage temperature dependence is achieved by setting
S n ln 5 S S6 R2 10 = m . R1 S9
is the resistor width. It is apparent that the lower I R1, the higher the ratio between Ileak and IR1. An adequate value of R1 must therefore be chosen so as to achieve an appropriate value of IR1. Similar considerations apply for other resistors. To choose the biasing condition of MOS transistors which have to operate in weak inversion, the corresponding gm/IDU plot (Fig. 5) can be analyzed, where gm and I DU represent the transconductance and the normalized drain current (I DU = ID/(W/L)), respectively. In this plot, the weak-inversion, the moderate-inversion, and the stronginversion regions are easily identified.
(6)
From (4), the desired value of Vref can be achieved by simply choosing an adequate value of R3. The process dependence of Vref will be compensated for by a trimming circuit (not shown). The topology adopted for the proposed voltage reference allows area saving as compared to conventional schemes. Indeed, by choosing a suitable scaling factor between the aspect ratios of M9 and M10 (S 10 > S9), a reduced value for resistor R2 can be used. Capacitor C3 in the scheme of Fig. 4 acts as a filter against high-frequency ground disturbs. Resistors R 1, R 2, and R 3 are implemented in the n-well layer, as no high-ohmic polysilicon layer is available.
Fig. 5 – Simulated behaviour of gm/IDU as a function of the normalized drain current IDU for a PMOS device.
The appropriate value of IDU comes from a trade-off choice. On the one hand, this current can not be chosen too low, so as to avoid critical leakage current effects, as explained above. On the other hand, IDU can not be set too high, so as to avoid too large deviations of the negative temperature coefficient of the source-to-gate voltage VSG from the ideal. To better illustrate this aspect, Fig. 6 shows the simulated deviation of the negative temperature coefficient of V SG from its value at T r as a function of temperature,
Fig. 4 – Block IVSG and I-V converter (K = S9/S10 is a suitable scaling factor).
3. DESIGN CONSIDERATIONS Low-power consumption requirements demand for minimizing the values of the currents flowing through each branch in the circuit. However, a lower bound exists for these values due to the presence of leakage currents from the n-well resistors to the substrate. In this respect, the increase in leakage currents with temperature must be also taken into account. The leakage current Ileak of any well resistor depends on its geometrical size, temperature, the voltage drop across the resistor itself, V R, and the well-to-substrate voltage VWB (the latter two dependences reach saturation above a given value of the applied voltage). To be specific, let us consider the case of resistor R1 in Fig. 3. From (2), the ratio between Ileak and IR1 turns out to be
=
nV S T ln 5 I leak (W R ,VWB ,VR1,T ) R S6 2 I R1
(7)
where R is the sheet resistance of the n-well layer, Ileak is the n-well-to-substrate leakage current per square, and WR
Fig. 6 – Simulated deviation of the negative temperature coefficient of VSG as a function of temperature for different values of IDU for a PMOS.
,
for different values of the normalized drain current. It is apparent that this deviation dramatically increases when passing from the weak- to the strong-inversion region. The value of IDU should therefore be set sufficiently far from the border between the weak- and the moderate-inversion region. The appropriate device aspect ratio will be consequently obtained by dividing the desired drain current ID by IDU. Finally, Fig. 7 depicts the simulated value of the negative temperature coefficient of V SG as a function of the normalized drain current. From this plot, the value of the temperature coefficient VSG7 to be used in (5) is found for the chosen IDU and, hence, the corresponding value of m is obtained.
The maximum deviation from the value at room temperature is 820 V, which corresponds to about 0.2%. The overall simulated current consumption is about 3 A. The presented voltage reference has also been successfully simulated with different values of R3, showing correct operation for Vref in the range from –100 mV to –850 mV (Vdd = 1 V). Finally, simulations demonstrate that the circuit works correctly for Vdd up to more than 3 V. Tab. 1 – Component size of the proposed voltage reference (transistors: m/m; resistors: k; capacitors: pF). PTAT-source
IVSG and I-V converter
Component
Value
Component
Value
M1, M3, M4
1/12
M7
75/1.5
M2
1/10
M8
10/1.5
M5
300/1.5
M9, M11, M12
1/12
M6
75/1.5
M10
4/12
R1
268
R2
618
C1
2
R3
800
C2, C3
30
5. CONCLUSIONS This paper has presented a voltage reference negative to the power supply based on MOS transistors operating in the weak-inversion region. The circuit can be operated from a supply voltage as low as 1 V and draws about 3 A. The simulated maximum variation of the reference voltage in the range from –20 to +80 ºC is about 0.2%.
Fig. 7 – Simulated value of the negative temperature coefficient of VSG as a function of the normalized drain current IDU for a PMOS device.
4. SIMULATION RESULTS
6. REFERENCES
The proposed circuit has been optimized for the above referred Flash memory technology to provide a reference voltage V ref of –400 mV, assuming a minimum supply voltage of 1 V. The component sizes are shown in Table 1. The value of the normalized current IDU chosen to bias transistor M7 is highlighted in Figures 5, 6, and 7. In our case, m turned out to be about 18. Fig. 8 shows the simulated reference voltage as a function of temperature in the range from –20 to +80 ºC (Vdd = 1 V).
[1] R. J. Widlar, “New developments in IC voltage regulator”, IEEE Journal of Solid-State Circuits, vol. SC-6, no. 1, pp. 2-7, Feb. 1971. [2] G. Tzanateas, C. A. T. Salama, and Y. P. Tsividis, “A CMOS bandgap voltage reference”, IEEE Journal of Solid-State Circuits, vol. SC-14, no. 3, pp. 655-657, June 1979. [3] E. A. Vittoz, and O. Neyroud, “A low-voltage CMOS bandgap reference”, IEEE Journal of Solid-State Circuits, vol. SC-14, no. 3, pp. 573-577, June 1979. [4] G. Ripamonti, M. Bertolaccini, R. Peritore, and S. Schippers, “Low power – low voltage band gap references for Flash-EEPROM integrated circuits: design alternatives and experiments”, Proc. IEEE Int. Conf. on Electronics, Circuits and Systems, vol. 2, pp. 635-638, Sept. 1999. [5] G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutrì, “A lowvoltage low-power voltage reference based on subthreshold MOSFETs”, IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 151-154, Jan. 2003. [6] S. Haddad, C. Chang, A. Wang, J. Bustillo, J. Lien, T. Montalvo, and M. Van Buskirk, “An investigation of erase-mode dependent hole trapping in flash EEPROM memory cell”, IEEE Electron Device Letters, vol. EDL-11, pp. 514-516, Nov. 1990. [7] S. Mahapatra, S. Shukuri, and J. Bude, “CHISEL Flash EEPROM – part I: performance and scaling”, IEEE Transactions on Electron Devices, vol. 49, no. 7, pp. 1296-1301, July 2002. [8] F. Forti, and M. E. Wright, “Measurement of MOS current mismatch in the weak inversion region”, IEEE Journal of Solid-State Circuits, vol. 29, no. 2, pp. 138-142, Feb. 1994.
Fig. 8 – Simulated reference voltage Vref as a function of temperature.
,
STMicroelectronics, Memory Products Group R&D, via Olivetti, 2 - 20041 Agrate Brianza, Italy 2 Department of Electronics, University of Pavia, via Ferrata, 1 - 27100 Pavia, Italy 3 Studio di Microelettronica, STMicroelectronics, via Ferrata, 1 - 27100 Pavia, Italy
efficiency, thereby allowing lower power consumption and faster programming. A typical value of the bulk bias voltage for this purpose is on the order of –1.4 V.
ABSTRACT A low-power low-voltage MOSFET-only voltage reference featuring very good temperature stability and referred to the positive power supply is proposed. It compensates for the temperature dependence of a gate-tosource voltage of an MOS transistor working in the weak inversion region with a proportional-to-absolutetemperature voltage generated by a pair of MOS devices operating in the same region. The circuit, designed for a 0.35-m (0.18-m in the memory array) CMOS Flash memory technology, can operate with a supply voltage as low as 1 V and draws a current of 3 A. The simulated variation of the reference voltage is within 0.2% over the range from –20 to 80 ºC.
Fig. 1 – Negative voltage regulator topology.
A negative voltage can be obtained by using the regulator topology depicted in Fig. 1, where the operational amplifier (op-amp) is operated from a positive (Vdd) and a negative (–Vss) power supply (the latter is provided by an on-chip negative charge pump voltage multiplier). The voltage V neg turns out to be Vr(1 + R2/R1) – VddR2/R1, which shows a large dependence on Vdd as generally R2/R1 is larger than unit. To limit the sensitivity of the generated voltage to V dd variations, a good choice is using a reference voltage negative to the positive supply V dd, namely setting Vr = Vdd + Vref (where Vref has a negative value, as is clear from Fig. 1). This way, V neg can be expressed as V dd + Vref(1 + R2/R1), which reduces the output voltage dependence on Vdd by a factor of R2/R1. In this paper, a low-power, low-voltage, MOSFET-only voltage reference negative to the power supply is proposed. This scheme, which is based on a current-mode approach, can operate with a supply voltage as low as 1 V, and draws a current of 3 A. Circuit design has been optimized for a p-substrate 0.35-m (0.18-m in the memory array) CMOS Flash technology. Moreover, design considerations regarding some critical aspects in the design of voltage references based on subthreshold MOS transistors are presented.
1. INTRODUCTION Voltage references are a key element in a number of integrated applications, including analog-to-digital and digital-to-analog converters, signal processing, and voltage regulators. The most widely used schemes of integrated voltage references with low temperature dependence are based on the bandgap approach. Several bandgap voltage references [1] have been implemented in bipolar and CMOS technology, where they achieve high levels of accuracy and stability. Recently, requirements of low-power and low-voltage devices are more and more vital as a consequence of the technology scaling down and the widespread applications of portable equipment (such as cellular phones, notebooks, personal data assistants, audio players, digital cameras, portable medical diagnosis systems, etc.). In voltage reference design, the above requirements can be easier met by using fully CMOS circuits. In particular, the use of MOS transistors working in the subthreshold region (hereinafter referred to as subthreshold MOS transistors) dramatically reduces power consumption, and also leads to silicon area saving [2-5]. Typically, bandgap voltage references provide an output voltage referred to ground. However, in some applications, a stable voltage referred to the positive supply V dd is desirable. For instance, Flash memories require high negative gate voltages for the erase operation [6]. In addition, recently, negative-bulk programming [7] has been demonstrated to increase hot-electron injection
;,(((
2. CIRCUIT DESCRIPTION The operating principle of the proposed voltage reference is depicted in Fig. 2. A current-mode approach has been adopted to meet low-voltage requirements. The block
,
,6&$6
PTAT-source generates a voltage proportional to absolute temperature (PTAT) and converts it into a current I R1 by means of resistor R1. The block IVSG generates a current IR2 by forcing the source-to-gate voltage of a subthreshold PMOS transistor through resistor R 2. This voltage decreases linearly with temperature, as will be explained in detail in Section 2.2. The above currents IR1 and I R2 are summed and are then converted into a voltage V ref by means of resistor R3. The scaling factors R3/R1 and R 3/R2 are chosen so as to minimize the temperature dependence of the obtained voltage Vref. R 1, R 2, and R 3 are matched resistors and, hence, their temperature dependence contributions ideally cancel out.
Fig. 3 – Circuit scheme of block PTAT-source.
2.2. IVSG and I-V converter The circuit schemes of blocks IVGS [4, 5] and I-V converter are shown in Fig. 4. The bias current IB is provided by mirroring the current flowing through resistor R1 in the PTAT-source circuit depicted in Fig. 3. Since M7 (which is identical to M 6) operates in weak inversion, I B can be approximated as a fixed bias current, thanks to the drain current logarithmic compression given by a subthreshold MOS device [5]. The source-to-gate voltage of device M 7 shows the following behaviour with temperature [5]:
Fig. 2 – Basic principle of the proposed voltage reference.
2.1. PTAT-source The circuit scheme of the block PTAT-source [2, 3] is shown in Fig. 3. To achieve a PTAT voltage drop across resistor R1, transistors M 5 and M 6 must operate in weak inversion. Assuming zero source-to-body voltage, their I-V characteristic can be described as follows
W I D = I D0 e L
VSG Vth nVT
V SD 1 e VT
(1)
where I D0 is the characteristic current, V T is the thermal voltage, n is the slope factor, and symbols VSG, VSD, Vth, W, and L have their usual meaning. The aspect ratios of transistors M3 and M4 were chosen so as to operate these devices in strong inversion, thus ensuring the best matching performance [8]. Considering that devices M 3 and M 4 are identical, the voltage drop across resistor R 1 turns out to be: S VR1 = nVT ln 5 (2) S6 where Si is the aspect ratio (W/L) i of the i-th transistor. The current through device M4 is therefore I R1 = V R1/R1. Device M5 resides in a separate well connected to its source, thus providing zero source-to-body voltage. In this way, M5 and M 6 operate in the same bias conditions, which ensure best matching. Transistors M 1 and M 2 and capacitor C 1 realize a conventional start-up circuit.
,
T VSG (T ) VSG (T r ) + KT + VSG (T r ) Vth (T r ) 1 (3) Tr
[
]
where Tr is a reference temperature equal to 300 K and KT is a positive constant related to the temperature variation of the threshold voltage (typical value: a few hundreds mV). In the subthreshold region, VSG(Tr) – |Vth(Tr)| has a negative value and the source-to-gate voltage of M 7 decreases linearly with increasing temperature for any fixed drain current. This source-to-gate voltage is forced across resistor R 2, and, hence, the current IM9 through M 9 is I R2S9/S10 = (V SG7/R2)S9/S10, where, again, S i is the aspect ratio of transistor Mi. The currents IR1 and I M9 generated by the block PTATsource and IVSG are forced through resistor R3 by means of devices M11 and M 12, which are identical to M4 and M 9, respectively, thus giving rise to a voltage Vref equal to
nV S V S Vref = R3 T ln 5 + SG7 9 R1 S6 R2 S10
(4)
Considering the ratio m between the absolute value of the negative temperature coefficient of V SG7 and the positive temperature coefficient of the thermal voltage VT:
VSG 7 T m= VT T
= Tr
VSG7 T
Tr
KB q
(5)
where K B is the Boltzmann constant and q the electron charge, first-order compensation of the reference voltage temperature dependence is achieved by setting
S n ln 5 S S6 R2 10 = m . R1 S9
is the resistor width. It is apparent that the lower I R1, the higher the ratio between Ileak and IR1. An adequate value of R1 must therefore be chosen so as to achieve an appropriate value of IR1. Similar considerations apply for other resistors. To choose the biasing condition of MOS transistors which have to operate in weak inversion, the corresponding gm/IDU plot (Fig. 5) can be analyzed, where gm and I DU represent the transconductance and the normalized drain current (I DU = ID/(W/L)), respectively. In this plot, the weak-inversion, the moderate-inversion, and the stronginversion regions are easily identified.
(6)
From (4), the desired value of Vref can be achieved by simply choosing an adequate value of R3. The process dependence of Vref will be compensated for by a trimming circuit (not shown). The topology adopted for the proposed voltage reference allows area saving as compared to conventional schemes. Indeed, by choosing a suitable scaling factor between the aspect ratios of M9 and M10 (S 10 > S9), a reduced value for resistor R2 can be used. Capacitor C3 in the scheme of Fig. 4 acts as a filter against high-frequency ground disturbs. Resistors R 1, R 2, and R 3 are implemented in the n-well layer, as no high-ohmic polysilicon layer is available.
Fig. 5 – Simulated behaviour of gm/IDU as a function of the normalized drain current IDU for a PMOS device.
The appropriate value of IDU comes from a trade-off choice. On the one hand, this current can not be chosen too low, so as to avoid critical leakage current effects, as explained above. On the other hand, IDU can not be set too high, so as to avoid too large deviations of the negative temperature coefficient of the source-to-gate voltage VSG from the ideal. To better illustrate this aspect, Fig. 6 shows the simulated deviation of the negative temperature coefficient of V SG from its value at T r as a function of temperature,
Fig. 4 – Block IVSG and I-V converter (K = S9/S10 is a suitable scaling factor).
3. DESIGN CONSIDERATIONS Low-power consumption requirements demand for minimizing the values of the currents flowing through each branch in the circuit. However, a lower bound exists for these values due to the presence of leakage currents from the n-well resistors to the substrate. In this respect, the increase in leakage currents with temperature must be also taken into account. The leakage current Ileak of any well resistor depends on its geometrical size, temperature, the voltage drop across the resistor itself, V R, and the well-to-substrate voltage VWB (the latter two dependences reach saturation above a given value of the applied voltage). To be specific, let us consider the case of resistor R1 in Fig. 3. From (2), the ratio between Ileak and IR1 turns out to be
=
nV S T ln 5 I leak (W R ,VWB ,VR1,T ) R S6 2 I R1
(7)
where R is the sheet resistance of the n-well layer, Ileak is the n-well-to-substrate leakage current per square, and WR
Fig. 6 – Simulated deviation of the negative temperature coefficient of VSG as a function of temperature for different values of IDU for a PMOS.
,
for different values of the normalized drain current. It is apparent that this deviation dramatically increases when passing from the weak- to the strong-inversion region. The value of IDU should therefore be set sufficiently far from the border between the weak- and the moderate-inversion region. The appropriate device aspect ratio will be consequently obtained by dividing the desired drain current ID by IDU. Finally, Fig. 7 depicts the simulated value of the negative temperature coefficient of V SG as a function of the normalized drain current. From this plot, the value of the temperature coefficient VSG7 to be used in (5) is found for the chosen IDU and, hence, the corresponding value of m is obtained.
The maximum deviation from the value at room temperature is 820 V, which corresponds to about 0.2%. The overall simulated current consumption is about 3 A. The presented voltage reference has also been successfully simulated with different values of R3, showing correct operation for Vref in the range from –100 mV to –850 mV (Vdd = 1 V). Finally, simulations demonstrate that the circuit works correctly for Vdd up to more than 3 V. Tab. 1 – Component size of the proposed voltage reference (transistors: m/m; resistors: k; capacitors: pF). PTAT-source
IVSG and I-V converter
Component
Value
Component
Value
M1, M3, M4
1/12
M7
75/1.5
M2
1/10
M8
10/1.5
M5
300/1.5
M9, M11, M12
1/12
M6
75/1.5
M10
4/12
R1
268
R2
618
C1
2
R3
800
C2, C3
30
5. CONCLUSIONS This paper has presented a voltage reference negative to the power supply based on MOS transistors operating in the weak-inversion region. The circuit can be operated from a supply voltage as low as 1 V and draws about 3 A. The simulated maximum variation of the reference voltage in the range from –20 to +80 ºC is about 0.2%.
Fig. 7 – Simulated value of the negative temperature coefficient of VSG as a function of the normalized drain current IDU for a PMOS device.
4. SIMULATION RESULTS
6. REFERENCES
The proposed circuit has been optimized for the above referred Flash memory technology to provide a reference voltage V ref of –400 mV, assuming a minimum supply voltage of 1 V. The component sizes are shown in Table 1. The value of the normalized current IDU chosen to bias transistor M7 is highlighted in Figures 5, 6, and 7. In our case, m turned out to be about 18. Fig. 8 shows the simulated reference voltage as a function of temperature in the range from –20 to +80 ºC (Vdd = 1 V).
[1] R. J. Widlar, “New developments in IC voltage regulator”, IEEE Journal of Solid-State Circuits, vol. SC-6, no. 1, pp. 2-7, Feb. 1971. [2] G. Tzanateas, C. A. T. Salama, and Y. P. Tsividis, “A CMOS bandgap voltage reference”, IEEE Journal of Solid-State Circuits, vol. SC-14, no. 3, pp. 655-657, June 1979. [3] E. A. Vittoz, and O. Neyroud, “A low-voltage CMOS bandgap reference”, IEEE Journal of Solid-State Circuits, vol. SC-14, no. 3, pp. 573-577, June 1979. [4] G. Ripamonti, M. Bertolaccini, R. Peritore, and S. Schippers, “Low power – low voltage band gap references for Flash-EEPROM integrated circuits: design alternatives and experiments”, Proc. IEEE Int. Conf. on Electronics, Circuits and Systems, vol. 2, pp. 635-638, Sept. 1999. [5] G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutrì, “A lowvoltage low-power voltage reference based on subthreshold MOSFETs”, IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 151-154, Jan. 2003. [6] S. Haddad, C. Chang, A. Wang, J. Bustillo, J. Lien, T. Montalvo, and M. Van Buskirk, “An investigation of erase-mode dependent hole trapping in flash EEPROM memory cell”, IEEE Electron Device Letters, vol. EDL-11, pp. 514-516, Nov. 1990. [7] S. Mahapatra, S. Shukuri, and J. Bude, “CHISEL Flash EEPROM – part I: performance and scaling”, IEEE Transactions on Electron Devices, vol. 49, no. 7, pp. 1296-1301, July 2002. [8] F. Forti, and M. E. Wright, “Measurement of MOS current mismatch in the weak inversion region”, IEEE Journal of Solid-State Circuits, vol. 29, no. 2, pp. 138-142, Feb. 1994.
Fig. 8 – Simulated reference voltage Vref as a function of temperature.
,
